Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1 – 20 are presented for examination.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 120 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 04/02/2025 and 07/23/2025 were received. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 3, and 11 – 16 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, the limitation “an extent of use of the memory” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “extent of use”.
Specifically, paragraph 0097, in one example, discloses the use of a counter to determine extent. However, the examiner asserts the broad understanding of “extent” fails to be limited by an general counting mechanism.
Claim 3 recites the limitation "the read data pattern". There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the read first pattern". There is insufficient antecedent basis for this limitation in the claim.
Any claim not addressed above is rejected due to its dependency on a rejected claim.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 – 20 are rejected on the ground of nonstatutory double patenting over claims 1, 3, 4 – 6, 8 – 15, and 17 of U.S. Patent No. 12,271,262 since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows:
Claim 1 – Application 19/090126
Claim 1 – Patent 12,271,262
A system comprising:
A system comprising:
memory; and
at least one memory configured to store data; and
at least one processing device configured to:
at least one processing device configured to: write a data pattern to the memory.
Claim 7 – Patent 12,271,262
read a data pattern from the memory; and
read the data pattern from the memory;
correct, based on reading the data pattern, an error in first data read from the memory.
wherein correcting the error comprises, in response to identifying the failing bit in the read data pattern, correcting a failing bit in the first data that corresponds to the identified failing bit.
One of ordinary skill in the art would clearly recognize independent claim 1, of application 19/090126 is an obvious variation of the claimed subject matter of independent claim 1 and claim 7, of patent 12,271,262. Specifically, both claim 1, of the current application 19/090126, and claims 1 and 7, of patent 12,271,262 discloses: A system comprising: memory; and at least one processing device configured to: comprising such steps as “read a data pattern from the memory” and correct an error in first data read from the memory.
One of ordinary skill in the art would recognize the system disclosed by claim 1, of the current application 19/090126, as a broad recitation of the operations performed by the system disclosed in claims 1 and 7 of Patent 12,271,262. A system performing the operations and a system capable of performing the disclosed operations would be recognize by one of ordinary skill in the art as obvious variants of each other.
Therefore, one of ordinary skill in the art would recognize the system of claim 1, of the current application 19/090126, as performing the operations of the system of claims 1 and 7, of U.S. Patent 12,271,262, and as such are obvious variants of each other.
Claim 2 – Application 19/090126
Claim 3 – Patent 12,271,262
Claim 3 – Application 19/090126
Claim 1 – Patent 12,271,262
Claim 4 – Application 19/090126
Claim 9 – Patent 12,271,262
Claim 5 – Application 19/090126
Claim 11 – Patent 12,271,262
Claim 6 – Application 19/090126
Claim 12 – Patent 12,271,262
Claim 7 – Application 19/090126
Claim 8 – Patent 12,271,262
Claim 8 – Application 19/090126
Claim 1 – Patent 12,271,262
Claim 9 – Application 19/090126
Claim 1 – Patent 12,271,262
Claim 10 – Application 19/090126
Claim 10 – Patent 12,271,262
Claim 11 – Application 19/090126
Claim 13, 14 – Patent 12,271,262
Claim 12 – Application 19/090126
Claim 14 – Patent 12,271,262
Claim 13 – Application 19/090126
Claim 15 – Patent 12,271,262
Claim 14 – Application 19/090126
Claim 17 – Patent 12,271,262
Claim 15 – Application 19/090126
Claim 14 – Patent 12,271,262
Claim 16 – Application 19/090126
Claim 10 – Patent 12,271,262
Claim 17 – Application 19/090126
Claim 1, 4 – Patent 12,271,262
Claim 18 – Application 19/090126
Claim 4 – Patent 12,271,262
Claim 19 – Application 19/090126
Claim 5 – Patent 12,271,262
Claim 20 – Application 19/090126
Claim 6 – Patent 12,271,262
Claims 1 – 20 are rejected on the ground of nonstatutory double patenting over claims 1, 4, 6, 9, 10, 14 – 20 of U.S. Patent No. 11,403,169 since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows:
Claim 1 – Application 19/090126
Claim 1 – Patent 11,403,169
A system comprising:
A system comprising:
memory; and
at least one memory configured to store data in memory cells;
at least one processing device configured to:
at least one processing device configured to:
read a data pattern from the memory; and
read the data pattern from the location in the memory;
correct, based on reading the data pattern, an error in first data read from the memory.
in response to identifying the failing bit, correcting the identified failing bit in the stored first data to provide corrected data.
One of ordinary skill in the art would clearly recognize independent claim 1, of application 19/090126 is an obvious variation of the claimed subject matter of independent claim 1, of patent 11,403,169. Specifically, both claim 1, of the current application 19/090126, and claim 1, of patent 11,403,169 discloses: A system with a memory and a processing device, comprising “read the data pattern from [the location in] the memory” and correct, based on reading the data pattern, an error in first data.
One of ordinary skill in the art would recognize the system disclosed by claim 1, of the current application 19/090126, as a broad recitation of the operations performed by the system disclosed in claim 1 of Patent 11,403,169. A system performing operations and a system capable of performing the disclosed operations would be recognize by one of ordinary skill in the art as obvious variants of each other.
Therefore, one of ordinary skill in the art would recognize the system claim 1, of the current application 19/090126, as performing the operations of the system of claim 1, of U.S. Patent 11,403,169, and as such are obvious variants of each other.
Claim 2 – Application 19/090126
Claim 20 – Patent 11,403,169
Claim 3 – Application 19/090126
Claim 1 – Patent 11,403,169
Claim 4 – Application 19/090126
Claim 6 – Patent 11,403,169
Claim 5 – Application 19/090126
Claim 14 – Patent 11,403,169
Claim 6 – Application 19/090126
Claim 14 – Patent 11,403,169
Claim 7 – Application 19/090126
Claim 1 – Patent 11,403,169
Claim 8 – Application 19/090126
Claim 1 – Patent 11,403,169
Claim 9 – Application 19/090126
Claim 1 – Patent 11,403,169
Claim 10 – Application 19/090126
Claim 4 – Patent 11,403,169
Claim 11 – Application 19/090126
Claim 10, 17 – Patent 11,403,169
Claim 12 – Application 19/090126
Claim 18 – Patent 11,403,169
Claim 13 – Application 19/090126
Claim 16 – Patent 11,403,169
Claim 14 – Application 19/090126
Claim 10 – Patent 11,403,169
Claim 15 – Application 19/090126
Claim 17 – Patent 11,403,169
Claim 16 – Application 19/090126
Claim 15 – Patent 11,403,169
Claim 17 – Application 19/090126
Claim 19, 20 – Patent 11,403,169
Claim 18 – Application 19/090126
Claim 20 – Patent 11,403,169
Claim 19 – Application 19/090126
Claim 9 – Patent 11,403,169
Claim 20 – Application 19/090126
Claim 9 – Patent 11,403,169
Closest Prior Art of Record
Thiruvengadam et al., U.S. Publication 2014/0245107
Thiruvengadam teaches: hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
LEE; JEONGHO et al. US 20200341843 A1
O'Connor, JR.; James A. et al. US 20190317856 A1
Cho; Sangyeun et al. US 20130332799 A1
correct, based on reading the data pattern, an error in first data read from the memory.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL F MCMAHON whose telephone number is (571)270-3232. The examiner can normally be reached Monday-Thursday 9am - 5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571)270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Daniel F. McMahon/Primary Examiner, Art Unit 2111
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