Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of Application
This Office Action is a response to Applicant’s communication (or preliminary’s amendment) filed on 03/25/2025. In virtue of this communication, claims 1-20 are currently presented in the instant application.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 03/25/2025 in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is considered by the examiner.
If applicant is aware of any prior art or any other co-pending application not already of record, he/she is reminded of his/her duty under 37 CFR 1.97 to disclose the same.
Drawings
Drawings submitted on 03/25/2025 accepted as part of the formal application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 9,
The recitation “a first antenna pattern” in line 6 is considered vague because it is confused with “a first antenna pattern” in line 4. Clarification is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dairiki et al (US 20120146240), hereinafter Dairiki.
Regarding claim 1,
Dairiki discloses a semiconductor device package (a semiconductor device, Fig 1B; paragraph [0048]), comprising:
a first antenna structure (a first antenna 103, Fig 1B) comprising an antenna pattern (a rectangular pattern of the first antenna 103, Fig 1A); and
a second antenna structure (a second antenna 106, Fig 1B) disposed over the first antenna structure and comprising an antenna pattern (a rectangular pattern of the second antenna 106, Fig 1A) overlapping the antenna pattern of the first antenna structure, wherein the second antenna structure connecting the first antenna structure by a bonding material (a bonding layer 107, Fig 1B).
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Regarding claim 3,
Dairiki discloses the claimed invention, as discussed in claim 1.
Dairiki teaches the second antenna structure is spaced apart from the first antenna structure (Fig 2B).
Regarding claim 4,
Dairiki discloses the claimed invention, as discussed in claim 1.
Dairiki teaches the second antenna structure is spaced apart from the first antenna structure by a supporting structure (a substrate 104, Fig 4B).
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Claims 9-14 and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Garcia et al (US 20160056544), hereinafter Garcia.
Regarding claim 9,
Garcia discloses a semiconductor device package (a wireless communications package 10, Fig 1), comprising:
a circuit structure (an RFIC chip 130, Fig 1);
a first antenna structure (an antenna 112, Fig 1) connecting to the circuit structure by a first connecting material (a metallization pattern 126, Fig 1) and including a first antenna pattern (a planar patch antenna 112, Fig 1; paragraph [0037]) at a first elevation (at an elevation H1, Fig 1); and
a second antenna structure (an antenna 122, Fig 1) connecting to the circuit structure by a second connecting material (a connection 150, Fig 1) and including a first antenna pattern (a Yagi pattern antenna 122, Fig 1; paragraph [0037]) at a second elevation (at an elevation H2, Fig 1) different from the first elevation.
[AltContent: arrow][AltContent: textbox (H1)][AltContent: ][AltContent: arrow][AltContent: textbox (H2)][AltContent: ][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: textbox (Garcia (US 20160056544))]
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Regarding claim 10,
Garcia discloses the claimed invention, as discussed in claim 9.
Garcia teaches the second antenna structure includes a second antenna pattern (a Yagi pattern antenna 222, Fig 2A) spaced apart from the first antenna pattern (a Yagi pattern antenna 221, Fig 2A) of the second antenna structure (an antenna array includes antennas 221 and 222, Fig 2A).
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Regarding claim 11,
Garcia discloses the claimed invention, as discussed in claim 9.
Garcia teaches the first antenna structure (an antenna array includes antennas 211 and 212, Fig 2A) is spaced apart from the second antenna structure (an antenna array includes antennas 221 and 222, Fig 2A) by an air space.
Regarding claim 12,
Garcia discloses the claimed invention, as discussed in claim 9.
Garcia teaches a thickness of the first antenna structure or the second antenna structure is less than a thickness of the circuit structure (Fig 1).
Regarding claim 13,
Garcia discloses the claimed invention, as discussed in claim 9.
Garcia teaches a width of the first antenna structure is different from that of the second antenna structure (Fig 2A).
Regarding claim 14,
Garcia discloses a semiconductor device package (a wireless communications package 10, Fig 1), comprising:
a first antenna structure (an antenna 112, Fig 1) including a first dielectric layer (a substrate 110, Fig 1);
a second antenna structure (an antenna 122, Fig 1) including a second dielectric layer (a substrate 120, Fig 1) without laterally overlapping the first dielectric layer; and
a circuit structure (an RFIC chip 130, Fig 1) supporting the first antenna structure and the second antenna structure at a same side of the circuit structure (Fig 1).
Regarding claim 18,
Garcia discloses the claimed invention, as discussed in claim 14.
Garcia teaches the first antenna structure includes a first antenna pattern (a planar patch antenna 112, Fig 1; paragraph [0037]) laterally covered by the first dielectric layer, wherein the second antenna structure includes a second antenna pattern (a Yagi pattern antenna 122, Fig 1; paragraph [0037]) laterally covered by the second dielectric layer, wherein a first elevation (at an elevation H1, Fig 1) of the first antenna pattern is different from a second elevation (at an elevation H2, Fig 1) of the second antenna pattern in respect to the circuit structure.
Regarding claim 19,
Garcia discloses the claimed invention, as discussed in claim 18.
Garcia teaches a first connection structure (a connection 150, Fig 1) connected to the second antenna pattern, and wherein the first connection structure laterally overlaps the first dielectric layer in a cross-sectional view (Fig 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Dairiki et al (US 20120146240), hereinafter Dairiki, in view of Ho et al (US 20180131094), hereinafter Ho.
Regarding claim 2,
Dairiki discloses the claimed invention, as discussed in claim 1.
Dairiki does not teach the bonding material includes a soldering material.
However, Ho teaches a semiconductor device package (a semiconductor device package 2, Fig 2B) comprises a second antenna structure (a second antenna 27, Fig 2B) connecting a first antenna (a first antenna 22, Fig B) by a solder material (an electrical connection 26b may be a solder ball; paragraphs [0031] and [0041]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use a bonding material including a soldering material in Dairiki, as taught by Ho, in order to increase quality of a signal transmitted between the antenna and the communication module.
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Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Dairiki et al (US 20120146240), hereinafter Dairiki, in view of Fujii et al (US 20090009402), hereinafter Fujii.
Regarding claim 5,
Dairiki discloses the claimed invention, as discussed in claim 1.
Dairiki does not teach the first antenna structure includes a first solder resist layer partially covering the antenna pattern of the first antenna structure.
However, Fujii teaches a semiconductor device 10 (Fig 3) comprises an antenna structure 15 (Fig 3) includes a solder resist layer (a solder resist 37, Fig 4) partially covering an antenna pattern (an antenna 33, Fig 4) of the antenna structure.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use a first antenna structure including a first solder resist layer partially covering an antenna pattern of the first antenna structure in Dairiki, as taught by Fujii, in order to provide an antenna element and a semiconductor device capable of achieving miniaturization.
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Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Garcia et al (US 20160056544), hereinafter Garcia, in view of Kim et al (US 20190027804), hereinafter Kim.
Regarding claim 15,
Garcia discloses the claimed invention, as discussed in claim 14.
Garcia does not teach the first dielectric layer non-overlaps the second dielectric layer vertically in a cross-sectional view.
However, Kim teaches a semiconductor device package (an antenna package 100, Fig 1) comprises a first antenna structure (an antenna member 115a, Fig 1) including a first dielectric layer (a dielectric layer 130a, Fig 1), and a second antenna structure (an antenna member 115b, Fig 1) including a second dielectric layer (a dielectric layer 130b, Fig 1), wherein the first dielectric layer non-overlaps the second dielectric layer vertically in a cross-sectional view (Fig 1).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use a first dielectric layer non-overlapping a second dielectric layer vertically in a cross-sectional view in Garcia, as taught by Kim, in order to reduce interference between the antennas.
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Regarding claim 16,
Garcia discloses the claimed invention, as discussed in claim 14.
Garcia does not teach a width of the first dielectric layer is different from that of the second dielectric layer in a cross-sectional view.
However, Kim teaches a semiconductor device package (an antenna package 100, Fig 1) comprises a first antenna structure (an antenna member 115a, Fig 1) including a first dielectric layer (a dielectric layer 130a, Fig 1), and a second antenna structure (an antenna member 115b, Fig 1) including a second dielectric layer (a dielectric layer 130b, Fig 1).
Kim does not explicitly teach a width of the first dielectric layer is different from that of the second dielectric layer in a cross-sectional view.
However, it is well known in the art that a width of a first dielectric layer being different from a width of a second dielectric layer in a cross-sectional view.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use a width of a first dielectric layer being different from that of a second dielectric layer in a cross-sectional view in Garcia, as taught by Kim, in order to reduce interference between the antennas.
Allowable Subject Matter
Claims 6, 7, 8, 17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 6, prior art of record or most closely prior art fails to disclose, “the first antenna structure includes a dielectric layer covered by the first solder resist layer”.
Regarding claim 7, prior art of record or most closely prior art fails to disclose, “the second antenna structure includes a solder resist layer partially covering the antenna pattern of the second antenna structure”.
Regarding claim 8, prior art of record or most closely prior art fails to disclose, “the first antenna structure includes a second solder resist layer partially covering the antenna pattern of the first antenna structure, wherein the first solder resist layer and the second solder resist layer are arranged at opposite sides of the antenna pattern of the first antenna structure”.
Regarding claim 17, prior art of record or most closely prior art fails to disclose, “the width of the second dielectric layer is at least 1.5 times the width of the first dielectric layer in the cross-sectional view”.
Regarding claim 20, prior art of record or most closely prior art fails to disclose, “a second connection structure connected to the first antenna pattern, and wherein the second connection structure non-overlaps the second dielectric layer laterally in the cross-sectional view”.
Conclusion
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Applicant, in preparing the response, should consider fully the entire reference aspotentially teaching all or part of the claimed invention, as well as the context of thepassage as taught by the prior art or disclosed by the Examiner.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hai Tran whose telephone number is (571) 270-7650. The examiner can normally be reached on Monday-Friday 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dimary Lopez can be reached on (571) 270-7893. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAI V TRAN/Primary Examiner, Art Unit 2845
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