DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I, and specie A, claims 1-18, 20 in the reply filed on 4/2/2026 is acknowledged.
Claim Objections
Claims 1, 4-5, 10-11, 17 are objected to because of the following informalities: “mircobump” should be –microbump--. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-7, 11-18 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Lee et al. (KR20110034057A from IDS).
Regarding claim 1, Lee discloses a substrate processing method comprising: (a) forming a first microbump 42 on a first surface of a substrate 40, wherein the first surface faces a semiconductor chip when the substrate and the semiconductor chip are bonded together; (b) forming a second microbump 12 on a second surface of the semiconductor chip 10, wherein the second surface faces the substrate when the substrate and the semiconductor chip are bonded together (figure 4 and see description); (c) forming an insulating film 22 on the first surface, the second surface, the first mircobump and the second microbump (figure 6 and see figure 6 description); (d) removing the insulating film formed on a connection surface of the first mircobump and a connection surface of the second microbump (figures 5-7, see description of figures 5-7); and (e) bonding the connection surface of the first mircobump on the first surface and the connection surface of the second microbump on the second surface (figures 4-7, description of drawings, claims, Lee discloses that removing the insulating film from the substrate and the chip are by the same process).
Regarding claim 5, Lee discloses in (d), the insulating film formed on the connection surface of the first mircobump and the connection surface of the second microbump is removed by a CMP (Chemical Mechanical Polishing) process or an etching process (see description of figure 7).
Regarding claim 6, Lee discloses further comprising (g) forming an underfill film 32 between the substrate and the semiconductor chip after (e) (figure 4).
Regarding claim 7, Lee discloses that the insulating film is capable of being formed on: another insulating film on the first surface or the second surface; a metal film on the first surface or the second surface; the first microbump: and the second microbump (figure 4, see description). There is a second film 22 on the second surface. The claim only requires that the film is capable and is not actually required. Since a film is placed on both surfaces and contacts the microbumps and the conductive resin 32, the claim limitation is met.
Regarding claim 11, Lee discloses, in (c), the insulating film is formed on the first surface, the second surface, the first mircobump and the second microbump by performing a cycle at least once, and wherein the cycle comprises: (c-1) forming an insulating layer on the first surface, the second surface, the first mircobump and the second microbump by supplying a source gas to the first surface, the second surface, the first mircobump and the second microbump; and (c-2) exposing the insulating layer to a reducing atmosphere. Lee discloses that the insulating material can be coated by spin coating, vacuum deposition (sputtering and chemical vapor deposition), spray coating (see description of figures 5-7).
Regarding claim 12, since Lee discloses applying a similar insulating film as the current invention with a similar process, it is the Examiner’s position that the insulating film is formed to prevent a difference in a wettability between the second surface of the semiconductor chip and a surface of the second microbump, or between the first surface of the substrate and a surface of the first microbump.
Regarding claim 13, Lee discloses wherein (g) is performed in a state where the insulating film is exposed on the substrate (figure 4, and see description).
Regarding claim 14, Lee discloses wherein (g) is performed in a state where the insulating film is formed on the substrate (figure 4, see description).
Regarding claim 15, Lee discloses that the insulating film comprises an inorganic insulating film (see description of figures 5-7).
Regarding claim 16, Lee discloses a substrate processing method comprising: performing at least one among:(a) forming an insulating film 22 on a first surface of a substrate 40 and a first microbump 42 formed on the first surface, wherein the first surface faces a semiconductor chip 10 when the substrate and the semiconductor chip are bonded together; and(b) forming the insulating film 20 on a second surface of the semiconductor chip 10 and a second microbump 12 formed on the second surface, wherein the second surface faces the substrate when the substrate and the semiconductor chip are bonded together (figures 3-4, 5-7 and description of drawings).
Regarding claim 17, Lee discloses in (a) or (b), the insulating film is formed on the first surface and the first mircobump, or on the second surface and the second microbump by performing a cycle at least once, and wherein the cycle comprises: (c-1) forming an insulating layer on the first surface and the first mircobump by supplying a source gas to the first surface and the first mircobump, or on the second surface and the second microbump by supplying the source gas to the second surface and the second microbump; and (c-2) exposing the insulating layer to a reducing atmosphere. Lee discloses that the insulating material can be coated by spin coating, vacuum deposition (sputtering and chemical vapor deposition), spray coating (see description of figures 5-7).
Regarding claim 18, Lee method of manufacturing a semiconductor device, comprising: the method of claim 16 (figures 3-4, 5-7 and description of drawings, see rejection of claim 16 above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (KR20110034057A from IDS) as applied to claims 1, 16 above.
Regarding claim 2, Lee discloses that the thickness can be a few microns, but does not disclose a thickness of the insulating film is set to be 50 nm or less. However, based on the current specification, the thickness claimed is only an example. There is no criticality for 50 nm. This appears to be a design choice. With that being said, since it is known to have a insulating layer on the substrate, it would have been obvious to one skilled in the art at the time of the invention to determine the ideal thickness required for protecting the substrate during its use.
Regarding claim 20, Lee discloses the method of claim 16, but does not specifically disclose using a non-transitory computer-readable recording medium storing a program that causes a processing apparatus, by a computer. However, to one skilled in the art at the time of the invention it would have been obvious to use a program to perform the known process due to the size and complexity of the components. This would remove any human error during the bonding process.
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (KR20110034057A from IDS) as applied to claim 1 above and further in view of Honda (JP55166943A).
Regarding claim 3, Lee does not specifically disclose (f) forming a conductive film 4 on the insulating film between (c) and (d). However, Honda discloses putting a conductive film on an insulating layer 3 prior to removing the insulating layer. To one skilled in the art at the time of the invention it would have been obvious to place a conductive film on the substrate in order to shield the substrate from radiation during use (see English translation of abstract).
Regarding claim 4, Honda discloses (d), the conductive film and the insulating film formed on the connection surface of the first microbump and the connection surface of the second microbump are removed (see English translation of abstract).
Allowable Subject Matter
Claims 8-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art was not found wherein (c) comprises: (c-1) forming a first insulating film on the first surface, the first microbump, the second surface and the second microbump; and (c-2) forming a second insulating film on the first insulating film, wherein the second insulating film comprises an organic group-containing insulating film.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIN B SAAD whose telephone number is (571)270-3634. The examiner can normally be reached Monday-Thursday 7:30a-6p.
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/ERIN B SAAD/Primary Examiner, Art Unit 1735
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