Prosecution Insights
Last updated: July 17, 2026
Application No. 19/091,166

INCREASED DATA INTEGRITY FOR AUTHENTICATED ENCRYPTION ALGORITHMS

Non-Final OA §103
Filed
Mar 26, 2025
Priority
Jun 15, 2020 — provisional 62/705,194 +1 more
Examiner
BROWN, ANTHONY D
Art Unit
Tech Center
Assignee
Microchip Technology Incorporated
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
1y 5m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
740 granted / 867 resolved
+25.4% vs TC avg
Strong +15% interview lift
Without
With
+15.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
13 currently pending
Career history
879
Total Applications
across all art units

Statute-Specific Performance

§101
3.8%
-36.2% vs TC avg
§103
78.9%
+38.9% vs TC avg
§102
10.7%
-29.3% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 867 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 3/26/2025 was filed after the mailing date of the application on 3/26/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. The information disclosure statement (IDS) submitted on 8/07/2025 was filed after the mailing date of the application on 3/26/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Double Patenting Claims 18 is rejected on the ground of non statutory double patenting as being unpatentable over claims 1 and 18 of U.S. Patent No. 12,267,409. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations in each claim set relate to the same concept. US Patent 12267409 19/091,166 An apparatus, comprising: a processor configured to: generate a receiver modified block of data at least partially responsive to adding an error detecting code to a block of data, the receiver modified block of data including the error detecting code; generate a receiver authentication code at least partially responsive to the receiver modified block of data; and generate an indication of a difference between the receiver authentication code and a transmitter authentication code. An apparatus, comprising: a processor to: generate a receiver modified block of data including an error detecting code; generate a receiver detection code based, at least in part, on the receiver modified block of data; and generate an indication of a difference between the receiver authentication code and a transmitter authentication code. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Weaver (US Patent 5935268) in view of Barton (US Patent 5646997) and in view of Naeimi (US Patent Pub. 20210211467). As per claim 1 and 10: (Currently Amended) An apparatus, comprising: a processor, the processor configured to: generate an error detecting code at least partially responsive to a plain text data (Col 3, lines 9-35; generate the modified data block. A second error detection code is calculated for the first data. For example, where the original data block is modified by the insertion of the first data into the original data block to generate the modified data block); However, Weaver does not specifically disclose generate a transmitter modified block of data at least partially responsive to adding the error detecting code to a block of data that includes the cipher text data (See Barton; Col 4, lines 10-25; embedding authentication data into a digital block, a digital signature is formed that is a reduced representation of the digital block. The signature and additional information supplied by the user are embedded into the digital block by replacing predetermined bits within the block. Encryption can be used to enhance authentication capability. The encrypted data can be further verified using error correction coding techniques); and Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains, having the teachings of Weaver and Barton in it’s entirety, to modify the technique of Weaver for generating an error detection code for a modified data packet by adopting Barton's teaching for embedding authentication data into a digital block. The motivation would have been to improve authenticated encryption algorithms. Weaver in view of Barton do not specifically disclose generate a cipher text data at least partially responsive to applying an encryption algorithm to the plain text data; generate an authentication code at least partially responsive to the transmitter modified block of data; generate an authenticated encrypted block of data at least partially responsive to the authentication code; and a transmitter, the transmitter configured to transmit an authenticated encrypted block of data (See Naeimi; Paragraph 23; computing platform 200 can provide data for transmission and offload encryption of data to network interface 240 and also control which specific packets, that contain segments of data, are transmitted (or re-transmitted) by network interface 240. For example, data can be encrypted using TLS or other encryption scheme). Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains, having the teachings of Weaver, Barton and Naeimi in it’s entirety, to modify the technique of Weaver for generating an error detection code for a modified data packet by adopting Naeimi's teaching for cryptographic protocols providing security of communications made over a computer network. The motivation would have been to improve authenticated encryption algorithms. As per claim 2 and 11: (Currently Amended) The apparatus of claim 1, wherein the processor is configured to perform a derivation function generate the error detecting code from the plain text data (See Weaver; Col 3, lines 9-35; generate the modified data block. A second error detection code is calculated for the first data. For example, where the original data block is modified by the insertion of the first data into the original data block to generate the modified data block). As per claim 3 and 12: (Currently Amended) The apparatus of claim 1, wherein the process is configured to generate an authenticated encrypted block of data at least partially responsive to the block of data and the authentication code (See Naeimi; Paragraph 23; computing platform 200 can provide data for transmission and offload encryption of data to network interface 240 and also control which specific packets, that contain segments of data, are transmitted (or re-transmitted) by network interface 240. For example, data can be encrypted using TLS or other encryption scheme). As per claim 4: (Original) The apparatus of claim 1, wherein the transmitted block of data includes the cipher text data (See Barton; Col 4, lines 10-25; embedding authentication data into a digital block, a digital signature is formed that is a reduced representation of the digital block. The signature and additional information supplied by the user are embedded into the digital block by replacing predetermined bits within the block. Encryption can be used to enhance authentication capability. The encrypted data can be further verified using error correction coding techniques). As per claim 5 and 13: (Original) The apparatus of claim 1, wherein the transmitted block of data docs not include the error detecting code that was added to the block of data to generate the transmitter modified block of data (See Naeimi; Paragraph 23; computing platform 200 can provide data for transmission and offload encryption of data to network interface 240 and also control which specific packets, that contain segments of data, are transmitted (or re-transmitted) by network interface 240. For example, data can be encrypted using TLS or other encryption scheme). As per claim 6 and 14: (Original) The apparatus of claim 1, wherein the authenticated encryption algorithm is AES-GCM (See Naeimi; Paragraph 43; In accordance with some embodiments, described herein, decryption circuitry 250 can perform TLS data-path offload of decryption and authentication in accordance with AES-GCM). As per claim 7 and 15: (Original) The apparatus of claim 1, wherein the processor is provided at a communication system (See Naeimi; Paragraph 3; Various cryptographic protocols provide security of communications made over a computer network. Secure Sockets Layer (SSL) and Transport Layer Security (TLS) are examples of security protocols). As per claim 8 and 16: (Original) The apparatus of claim 7, wherein the communication system is for a Compute Express Link (CXL) interconnect (See Naeimi; Paragraph 90; Compute Express Link (CXL)). As per claim 9 and 17: (Original) The apparatus of claim 7, wherein the communication system is for a Peripheral Component Interconnect Express (PCIe) interconnect (See Naeimi; Paragraph 90; Peripheral Component Interconnect express). As per claim 18: (New) An apparatus, comprising: a processor to: generate a receiver detection code based, at least in part, on the receiver modified block of data (Col 3, lines 9-35; where the original data block is modified by the insertion of the VLAN header information into the original data block, a CRC is calculated using the VLAN header information shifted to a position corresponding to its position within the modified data block). Weaver does not specifically disclose generate a receiver modified block of data including an error detecting code (See Barton; Col 4, lines 10-25; embedding authentication data into a digital block, a digital signature is formed that is a reduced representation of the digital block. The signature and additional information supplied by the user are embedded into the digital block by replacing predetermined bits within the block. Encryption can be used to enhance authentication capability. The encrypted data can be further verified using error correction coding techniques); Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains, having the teachings of Weaver and Barton in it’s entirety, to modify the technique of Weaver for generating an error detection code for a modified data packet by adopting Barton's teaching for embedding authentication data into a digital block. The motivation would have been to improve authenticated encryption algorithms Weaver in view of Barton do not specifically disclose generate an indication of a difference between the receiver authentication code and a transmitter authentication code (See Naeimi; Paragraph 41; FIG. 2B depicts an example of a receiver system. The receiver system can use similar elements of transmitter system of FIG. 2A and for the sake of illustration, receiver-side elements are described, but elements of transmitter and receiver systems can be combined). Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains, having the teachings of Weaver, Barton and Naeimi in it’s entirety, to modify the technique of Weaver for generating an error detection code for a modified data packet by adopting Naeimi's teaching for cryptographic protocols providing security of communications made over a computer network. The motivation would have been to improve authenticated encryption algorithms. As per claim 19: (New) The apparatus of claim 18, wherein the processor to generate the error detection code based, at least in part, on plain text data (See Weaver; Col 3, lines 9-35; generate the modified data block. A second error detection code is calculated for the first data. For example, where the original data block is modified by the insertion of the first data into the original data block to generate the modified data block). As per claim 20: (New) The apparatus of claim 19, wherein the processor to generate a cipher text data at least partially responsive to applying an encryption algorithm to the plain text data, the encryption algorithm optionally an encryption portion of an authenticated encryption process (See Weaver; Col 3, lines 9-35; generate the modified data block. A second error detection code is calculated for the first data. For example, where the original data block is modified by the insertion of the first data into the original data block to generate the modified data block). Relevant Prior Art References The following prior art is cited as being of interest to the claimed invention but has not been applied in any of the current rejections. Peeters et al. - US Patent Pub. 2025/0117499 A1: The prior art teaches techniques for improving data encryption Kim et al. - US Patent Pub. 2016/0180102 A1: The prior art teaches secure data management Yuan et al. – US Patent Pub. 2013/0305061 A1: The prior art teaches data storage device and data protection by encrypting data Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY D BROWN whose telephone number is (571)270-1472. The examiner can normally be reached 730-330pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey Pwu can be reached on 571-272-6798. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANTHONY D BROWN/Primary Examiner, Art Unit 2433
Read full office action

Prosecution Timeline

Mar 26, 2025
Application Filed
Jun 26, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+15.1%)
2y 8m (~1y 5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 867 resolved cases by this examiner. Grant probability derived from career allowance rate.

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