Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 7/2/2026 have been fully considered but they are not persuasive. Cariello states, as pointed out by the applicant on page 12 of the arguments, that the string select 245 line MAY be common to all strings. This also very clearly suggests that it also MAY NOT be common to all strings. Furthermore, Sakui states in p61 and fig. 4 that each string can be activated independently and that a plurality of strings (i.e. a string group) can activated together for example to write data to cells of different strings. It should also be denoted that the term “group” does NOT necessarily denote more than one element of something, especially when it is used in a mathematical sense.
Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
Applicant's arguments do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cariello (US 2024/0264745, as listed on the IDS dated 2/26/2025) in view of Sakui (US 2018/0090208).
In regards to claims 1, 8, and 15, taking claim 1 as exemplary Cariello teaches
A method of operating a memory device, comprising the steps of: (fig. 1, memory device 130)
preparing a memory block that includes an array of memory cells that are arranged in a plurality of word lines and a plurality of string groups; (fig. 2, ¶38-41, a memory block 270 includes an array of memory cells 205 that are arranged in strings 210, and a plurality of word lines 220a-220n. The strings are activated through a string select line 245 that can be common to all string select transistors 230 (i.e. a string group) activated together as a page (i.e. a string group)
performing a first read operation on a first set of memory cells that are in a first selected word line and a first selected string group; (fig. 4, ¶67-77, at time T2-T4 a set of bits from the selected wordline 420-b are read)
determining that a second read operation is to be on a second set of memory cells that is different than the first set of memory cells; (¶72 a second read operation is received to be performed on a different word line)
at least one of:
simultaneously ramping up a voltage applied to a first selected word line from a reference voltage to a pass voltage and ramping down a voltage applied to a second selected word line from the pass voltage to the reference voltage, (fig. 4, at time T4 the first selected word line 420-b voltage is ramped up (to the pass (max voltage), while the second selected word line 420-c voltage is ramped down (i.e. to the reference voltage such that the data can be read (i.e. referenced))
Cariello may not explicitly teach
the plurality of string groups being separately controllable by respective drain-side select gates (SGDs) to independently activate individual string groups of the plurality of string groups
simultaneously ramping down a voltage applied to a first drain-side select gate (SGD) and ramping up a voltage applied to a second SGD.
Carriello does teach in p41 “each string 210 of memory cells 205 in the memory circuit 200 may be coupled with a respective string select transistor (SST) 230 at one end of the string 210 and a respective ground select transistor (GST) 225 at the other end of the string 210. The gate of each SST 230 may be coupled with a string select line 245, which may be common to all SST 230 for the block 270”, note that the term “may” makes it optional on whether or not there is a single string select line for all strings (i.e. common), and at least suggest that there are other possibilities, such as multiple string select lines that are used to select preset groups of strings (via SSTs, i.e. SGDs) or that each string may have its only independent string select line to active a strings SST (via a SGD). Sakui in p61 and fig. 4. further reinforces that a plurality of strings (i.e. groups of strings) can be selectively (independently) activated together by the selection of turning on/off a series of select gates (SGD) in order to active the designated plurality/set/group of strings.
Sakui ¶60 and fig. 2-5 also further teaches that SGD signals can be provided with voltages (i.e. ramped up or ramped down) in order to select which group of strings are to be activated.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to have been able to incorporated the teachings of Sakui to modify Cariello, such that individual and/or sets/groups of strings can be activated/deactivated together via the string/select lines connected to each of the strings SGDs, and that when the access is to a different string and/or set/group of strings, the currently activated string(s) (i.e. string group) can be deactivated (by ramping down a SGD signal) while simultaneously activating (by ramping up a SGD signal) a new string group that is to be read. One of ordinary skill in the art would have been able to make this modification and achieved predictable results. The motivation for making this modification is that this allows different string groups to activated/deactivated such that the correct requested data can be successfully read.
In regards to claims 2, 9, and 16 Cariello and Sakui make obvious
wherein in response to the second set of memory cells being in a different word line and a same string group as the first set of memory cells, then the method; includes the step of simultaneously ramping up the voltage applied to the first selected word line from a reference voltage to the pass voltage and ramping down the voltage applied to the second selected word line from the pass voltage to the reference voltage, and does not include the step of simultaneously ramping down the voltage applied to the first SGD and ramping up the voltage applied to the second SGD. (see the teachings of claim 1 above, if a different set of strings isn’t being accessed, then the changing of the SGDs (i.e. what’s used to select the string groups) is not neccessary
In regards to claims 3, 10, and 17 Cariello and Sakui make obvious
wherein in response to the second set of memory cells being in the same word line and a different string group as the first set of memory cells, then the method; includes the step of simultaneously ramping down the voltage applied to the first SGD and ramping up the voltage applied to the second SGD, and not perform the simultaneous ramping up of the voltage applied to the first selected word line from a reference voltage to the pass voltage and ramping down of the voltage applied to the second selected word line from the pass voltage to the reference voltage. (see the teachings of claim 1 above, if a different set of strings is being accessed, then the voltage of the SGDs needs to be changed to select the different string group. See also ¶53-56 and fig. 3 of Cariello, which shows two consecutive reads to the same word line)
In regards to claims 4-5, 11-12, and 18-19 Cariello and Sakui make obvious
wherein in response to the second set of memory cells being both in a different word line and a different string group than the first set of memory cells, then the method includes both; the step of simultaneously ramping down the voltage applied to the first SGD and ramping up the voltage applied to the second SGD, and the step of simultaneously ramping up the voltage applied to the first selected word line from a reference voltage to the pass voltage and ramping down the voltage applied to the second selected word line from the pass voltage to the reference voltage. wherein the step of simultaneously ramping down the voltage applied to the first SGD and ramping up the voltage applied to the second SGD is performed simultaneously with the step of simultaneously ramping up the voltage applied to the first selected word line from a reference voltage to the pass voltage and ramping down the voltage applied to the second selected word line from the pass voltage to the reference voltage. (see the teachings of claim 1 above, if a different set of strings is being accessed, then the voltage of the SGDs needs to be changed to select the different string group. This can occur simultaneously with the switching of wordline voltages to prepare the new word line.)
In regards to claims 6, 14, and 20 Cariello further teaches
further including the step of performing the second read operation on the second set of memory cells. (fig. 4, ¶67-77, at time T5-T7 a set of bits from the selected wordline 420-c are read(i.e. the second set of memory cells are read for the second read operation)
In regards to claims 7 and 14, Cariello further teaches
wherein the memory cells of the memory block are programmed according to a single bit per memory cell storage scheme. (¶28 teaches the memory cells can be SLC)
EXAMINER’S NOTE
Examiner has cited particular paragraphs, figures, and/or columns and line numbers in the references applied to the claims above for the convenience of the Applicants. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicants in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The applicant is reminded of what constitutes a proper reply to this office action is detailed in 37 CFR 1.111, and that the examiner has the discretion to treat any response that fails to meet ALL the requirements of that section as NON-RESPONSIVE without any additional extensions of time (see MPEP 714.03).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
`Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON W BLUST whose telephone number is (571)272-6302. The examiner can normally be reached 12-8:30 EST.
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/JASON W BLUST/ Primary Examiner, Art Unit 2132
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