Prosecution Insights
Last updated: October 02, 2026
Application No. 19/092,654

MANAGING DEFECTIVE BLOCKS DURING MULTI-PLANE PROGRAMMING OPERATIONS IN MEMORY DEVICES

Non-Final OA §103§112§DOUBLEPATENT
Filed
Mar 27, 2025
Priority
Aug 29, 2022 — continuation of 12/293,795
Examiner
RADKE, JAY W
Art Unit
Tech Center
Assignee
Micron Technology Inc.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
732 granted / 852 resolved
+25.9% vs TC avg
Moderate +8% lift
Without
With
+8.5%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
15 currently pending
Career history
870
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
41.5%
+1.5% vs TC avg
§102
23.6%
-16.4% vs TC avg
§112
26.0%
-14.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 852 resolved cases

Office Action

§103 §112 §DOUBLEPATENT
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on April 4, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5, 7-12, and 14-19 of U.S. Patent No. 12,293,795 (reference patent). Although the claims at issue are not identical, they are not patentably distinct from each other because of the following: Regarding claims 1-2: Claim 1 of the reference patent teaches the subject matter of these claims. Regarding claims 3-7: Claims 2-5 and 7 of the reference patent teaches, respectively, the subject matter of these claims. Regarding claims 8-9: Claim 8 of the reference patent teaches the subject matter of these claims. Regarding claims 3-7: Claims 9-12, and 14 of the reference patent teaches, respectively, the subject matter of these claims. Regarding claims 15-16: Claim 15 of the reference patent teaches the subject matter of these claims. Regarding claims 17-20: Claims 16-19 of the reference patent teaches, respectively, the subject matter of these claims. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Regarding claim 1: The only embodiment or embodiments supported in the specification are for an indirect and in part dependence of retiring the first block and the second block on determining that the first block fails the program verification check (FIG. 3, for example), wherein a plurality of other events or conditions need to be met, that may not be met, to cause the first block and second block to be retired. In other words, an embodiment, wherein the first block and the second block are retired immediately and solely in response to determining that the first block fails the program verification check, was NOT disclosed in the specification. Essential events other than just the determining that the first block fails the program verification check, such as a criterion being satisfied in 330 of FIG. 3 and a failure verification operation being performed on the second block in 340A of FIG. 3 that identifies the second block as a bad block, need to happen before retiring the first block and the second block. Hence, the claim is broader than the specification since its breadth includes at least one embodiment that was NOT disclosed or supported in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of the claimed invention. Claims 2-14 depend on claim 1. One possible way to overcome the rejection is to change “responsive to” to “responsive in part to”. Regarding claim 8: The only embodiment or embodiments supported in the specification are for an indirect and in part dependence of retiring the first block and the second block on determining that the first block fails the program verification check (FIG. 3, for example), wherein a plurality of other events or conditions need to be met, that may not be met, to cause the first block and second block to be retired. In other words, an embodiment, wherein the first block and the second block are retired immediately and solely in response to determining that the first block fails the program verification check, was NOT disclosed in the specification. Essential events other than just the determining that the first block fails the program verification check, such as a criterion being satisfied in 330 of FIG. 3 and a failure verification operation being performed on the second block in 340A of FIG. 3 that identifies the second block as a bad block, need to happen before retiring the first block and the second block. Hence, the claim is broader than the specification since its breadth includes at least one embodiment that was NOT disclosed or supported in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of the claimed invention. Claims 9-14 depend on claim 8. One possible way to overcome the rejection is to change “responsive to” to “responsive in part to”. Regarding claim 15: The only embodiment or embodiments supported in the specification are for an indirect and in part dependence of retiring the first block and the second block on determining that the first block fails the program verification check (FIG. 3, for example), wherein a plurality of other events or conditions need to be met, that may not be met, to cause the first block and second block to be retired. In other words, an embodiment, wherein the first block and the second block are retired immediately and solely in response to determining that the first block fails the program verification check, was NOT disclosed in the specification. Essential events other than just the determining that the first block fails the program verification check, such as a criterion being satisfied in 330 of FIG. 3 and a failure verification operation being performed on the second block in 340A of FIG. 3 that identifies the second block as a bad block, need to happen before retiring the first block and the second block. Hence, the claim is broader than the specification since its breadth includes at least one embodiment that was NOT disclosed or supported in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of the claimed invention. Claims 16-20 depend on claim 15. One possible way to overcome the rejection is to change “responsive to” to “responsive in part to”. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1, 8, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2022/0392556 A1) in view of Murai et al. (US 2023/0268013 A1). Regarding claim 1: Yang (FIG. 1, FIG. 2, FIG. 8A-B; [0062-0085]) teaches a system comprising: a memory device (memory device 100 in FIG. 2; [0062]); and a processing device (memory controller 122 in FIG. 2 or Host 140 in FIG. 2), operatively coupled with the memory device, to perform operations comprising: performing a set of write operations (a multi-plane programming operation; [0038]) on a first block in a first plane of the memory device and on a second block in a second plane of the memory device (plane 0 and plane 1 in FIG. 8B, for example). Yan does not specifically teach: performing a program verification check on the first block; and responsive to determining that the first block fails the program verification check, retiring the first block and the second block. Murai ([0031]) teaches, in prior art systems, executing a multi-plane programming operation, wherein failure of the programming process in one plane causes other planes to fail, and consequently retiring blocks in other planes, which may cause good blocks to be retired. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Murai into Yan in a manner such that a program verification check on a first block would be performed to determine whether the programming process was successful or a failure; and responsive to determining that the first block fails the program verification check, both the first block and the second block would be retired. The motivation to do so would have been to use a prior art technique, wherein a failure of the programming process in a first block in a first plane would cause a second block of a second plane to be retired even though it may be a good block. Regarding claim 8: Yang (FIG. 1, FIG. 2, FIG. 8A-B; [0062-0085]) teaches a method comprising: performing, by a processing device, a set of write operations on a first block in a first plane (a block in Plane 0 of FIG. 8B) of a memory device (memory device 100 in FIG. 2; [0062]) and on a second block in a second plane (a block in Plane 0 of FIG. 8B) of the memory device. Yan does not specifically teach: performing a program verification check on the first block; and responsive to determining that the first block fails the program verification check, retiring the first block and the second block. Murai ([0031]) teaches, in prior art systems, executing a multi-plane programming operation, wherein failure of the programming process in one plane causes other planes to fail, and consequently retiring blocks in other planes, which may cause good blocks to be retired. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Murai into Yan in a manner such that a program verification check on a first block would be performed to determine whether the programming process was successful or a failure; and responsive to determining that the first block fails the program verification check, both the first block and the second block would be retired. The motivation to do so would have been to use a prior art technique, wherein a failure of the programming process in a first block in a first plane would cause a second block of a second plane to be retired even though it may be a good block. Regarding claim 15: Yang (FIG. 1, FIG. 2, FIG. 8A-B; [0062-0085]) teaches a non-transitory computer-readable storage medium comprising instructions ([0048-0050]) that, when executed by a processing device, cause the processing device to perform operations comprising: performing a set of write operations on a first block in a first plane (a block in Plane 0 of FIG. 8B) of a memory device (memory device 100 in FIG. 2; [0062]) and on a second block in a second plane (a block in Plane 0 of FIG. 8B) of the memory device; Yang does not specifically teach: performing a program verification check on the first block; and responsive to determining that the first block fails the program verification check, retiring the first block and the second block. Murai ([0031]) teaches, in prior art systems, executing a multi-plane programming operation, wherein failure of the programming process in one plane causes other planes to fail, and consequently retiring blocks in other planes, which may cause good blocks to be retired. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Murai into Yan in a manner such that a program verification check on a first block would be performed to determine whether the programming process was successful or a failure; and responsive to determining that the first block fails the program verification check, both the first block and the second block would be retired. The motivation to do so would have been to use a prior art technique, wherein a failure of the programming process in a first block in a first plane would cause a second block of a second plane to be retired even though it may be a good block. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. JAY W. RADKE Primary Examiner Art Unit 2827 /JAY W. RADKE/Primary Examiner, Art Unit 2827
Read full office action

Prosecution Timeline

Mar 27, 2025
Application Filed
Sep 10, 2026
Non-Final Rejection mailed — §103, §112, §DOUBLEPATENT (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12748691
MEMORY DEVICE AND OPERATION THEREOF
2y 2m to grant Granted Sep 29, 2026
Patent 12744084
METHOD FOR READING A MULTI-LEVEL NON-VOLATILE MEMORY DEVICE, IN PARTICULAR A PHASE-CHANGE MEMORY DEVICE, AND MULTI-LEVEL NON-VOLATILE MEMORY DEVICE
2y 4m to grant Granted Sep 22, 2026
Patent 12744095
MEMORY DEVICE AND OPERATION METHOD THEREOF
2y 2m to grant Granted Sep 22, 2026
Patent 12738309
ADJUSTING REFRESH RATE DURING SELF-REFRESH STATE
1y 10m to grant Granted Sep 15, 2026
Patent 12725655
REDUNDANCY AND MAJORITY VOTING IN A KEY-VALUE DATA STORAGE SYSTEM USING CONTENT ADDRESSABLE MEMORY
1y 10m to grant Granted Sep 01, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
94%
With Interview (+8.5%)
2y 0m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 852 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month