DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claims 3-11, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2022/0137865), “Lee”, in view of Davis et al. (US 2003/0037185), “Davis”.
2. As per claim 1, Lee discloses at least one neural processor comprising a first neural processor [the accelerator 103 configured as a neural processing unit, paragraph 37]; a shared memory shared by the at least one neural processor [Memory Expander 110, figure 1]; and a global interconnection [the CXL interface coupled to the Accelerator 103 and the Memory Expander 110, figure 1] configured to transmit data between the at least one neural processor and the shared memory, wherein the first neural processor comprises: a first neural core configured to generate a first read request and have a first request ID [a read request and a first address, abstract]; a local interconnection configured to receive the first read request [the busses connecting the components, figure 1]; and a neural processor cache [a cache memory, paragraph 36].
Lee does not disclose expressly transmitting a second read request for the first read request receiving the second read request, receiving read data for the second read request, and transferring the read data.
Davis discloses transmitting a second read request for the first read request receiving the second read request [redirecting virtual addresses to physical addresses, abstract], receiving read data for the second read request, and transferring the read data [CPU receiving/transferring data from/to the physical memory resources, figure 1].
Lee and Davis are analogous art because they are from the same field of endeavor of storage device management.
Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to modify Lee by including the virtual addressing as expressly taught by Davis in figure 1.
The motivation for doing so would have been dynamic resource routing as expressly taught by Davis in the abstract.
3. As per claim 2, the cited prior arts disclose wherein the neural processor cache [a cache memory, paragraph 36, Lee] transfers a third read request for the second read request to the global interconnection [the CXL interface used for data transfer, figure 1, Lee], and receives the read data from the global interconnection.
4. As per claim 12, the cited prior arts disclose wherein the first neural processor further comprises a second neural core [Accelerator #2 1220, figure 15, Lee] configured to generate a first read request and have a second request ID [a second address, paragraph 47, Lee] that is different from the first request ID [a first address, abstract, Lee].
5. As per claim 15, the cited prior arts disclose wherein the neural processor cache comprises two or more lanes [multiple physical addresses, figure 1, Davis], each of which configured to receive the second read request independently and respectively receive the read data corresponding to the second read request [a second data read, paragraph 99, Lee].
6. As per claim 16, the cited prior arts disclose wherein the first neural processor further comprises an interleaving module configured to distribute the second read request to the two or more lanes [distributed to multiple physical addresses, figure 1, Davis].
7. As per claim 17, the cited prior arts disclose wherein a number of lanes [multiple physical addresses, figure 1, Davis] is different from a number of neural cores [Accelerator 103, figure 1, Lee].
Conclusion
A. Claims No Longer under Consideration
Claims 18-20 are withdrawn.
B. Subject Matter Considered Allowable
Claims 3-11, 13, and 14 are objected to.
The closest prior art of record, “Lee” discloses accelerator memory access in figure 1.
The primary reasons for allowance of claim 3 in the instant application is the combination with the inclusion in these claims that “wherein the neural processor cache comprises: an address decoder configured to allocate an allocation ID to the second read request, write the allocation ID of the second read request and the first request ID to a request ID link table, and generate a data read request according to the request ID link table; a data requester configured to generate and transfer a third read request for the data read request to the global interconnection, and receive the read data for the third read request; a data buffer configured to store the read data; and a data completer configured to transfer the read data to the first neural core”. The prior art of record neither anticipates nor renders obvious the above recited combination.
The primary reasons for allowance of claim 13 in the instant application is the combination with the inclusion in these claims that “wherein the neural processor cache receives the first read request of the first request ID and the first read request of the second request ID, and requests the read data at once”. The prior art of record neither anticipates nor renders obvious the above recited combination.
As allowable subject matter has been indicated, applicant's response must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 C.F.R. § 1.111(b) and § 707.07(a) of the MPEP.
C. Claims Rejected
Claims 1, 2, 12, and 15-17 are rejected.
D. Direction for Future Remarks
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAE UN YU whose telephone number is (571)272-1133. The examiner can normally be reached M-F 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAE U YU/Primary Examiner, Art Unit 2138
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