DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities: It seems a word of “system” is missing at the end of the statement. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. US12291219B2. Although the claims at issue are not identical, they are not patentably distinct from each other because; it would have been obvious to one of ordinary skill in the art;
To modify/remove some statements to make the claims broader,
To modify some statements with broader functionality, such as
“performing a first local test on a first processing portion”, instead of “performing a first system test on a first processing element”,
“local controller”; instead of “local test controller”,
“a second local test on a second processing portion”, instead of “a second system test on a second processing element”
could make the claims broader, but does not make patentable distinct from the parent patent claims.
A claim comparison of the parent patent and instant application clearly shows that there is no new or improved elements other than some of the patentably indistinct variations.
See below table for claim elements comparison:
Instant App. # : 19/093,406
(Pub. No.: US20250222941A1)
Parent App. # : 18/048,952
(Patent No.: US12291219B2)
Independent Claims
Independent Claims
1. A method comprising: performing a first local test on a first processing portion of an integrated processing system
1. A method comprising: performing a first system test on a first processing element of an integrated processing system based at least on accessing,
using a first local controller; and
using a first local test controller,
a first test node associated with the first processing element, the first local test controller being dedicated for the first test node and the first processing element; and
performing a second local test on a second processing portion of the integrated processing (Note: it seems a word of “system” is missing at the end of the sentence)
performing, independent of and at least partially during the first system test, a second system test on a second processing element of the integrated processing system
based at least on accessing,
using a second local controller
different from the first local controller.
using a second local test controller,
a second test node associated with the second processing element, the second local test controller being dedicated for the second test node and the second processing element.
9. A system comprising:
a first processing portion;
7. An integrated system comprising:
a first processing element cluster that includes one or more first processing elements;
a second processing element cluster that includes one or more second processing elements;
a first local controller assigned to the first processing portion and
to manage local tests of the first processing portion;
a first test node associated with the first processing element cluster;
a second test node associated with the second processing element cluster;
a first local test controller associated with the first test node, the first local test controller
to locally perform a first system test on the first processing element cluster using the first test node;
a data bus; and control circuitry to cause performance of one or more operations comprising: allowing data communication between the first processing portion and the first local controller during a first local test of the first processing portion; and blocking data communication between the first processing portion and the data bus during the first local test of the first processing portion.
Dependent claim 11 : “a data selector configured to select between a first selector mode and a second selector mode, the first selector mode including allowing communication of data between the first local test controller and the first processing element cluster, and the second selector mode including allowing communication of data between a data bus and the first processing element cluster.
a second local test controller associated with the second test node and separate from the first local test controller, the second local test controller to locally perform a second system test on the second processing element cluster using the second test node; and
a global test controller communicatively coupled to the first test node and the second test node to control a global system test that includes testing the first processing element cluster and the second processing element cluster.
16. One or more processors comprising:
one or more circuits to cause performance of a local test on a first processing portion of a processing system using a local controller assigned to the first processing portion
while a second processing portion of the processing system continues general operations.
14. A system comprising:
a first processing element cluster that includes one or more first processing elements; and a local test controller communicatively coupled to and assigned to the first processing element cluster, the local test controller to perform a local system test on the first processing element cluster
while a second processing element cluster of a same integrated system as the first processing element cluster, including one or more second processing elements, continues operation independent of the system test.
The instant claims recitations are obvious variation of the co-pending applications claims recitation in which both claims are represented by common drawings and are comingled in scope as mapped out above.
Regarding dependent claims 2-8, 10-15 & 17-20; these claims are substantial duplicates of parent patent claims 2-6, 8-13 & 15-19.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)1 and 102(a)2 as being anticipated by Portolan et al., Pub. No.: US 20120117436 A1.
Remarks : Portolan et al., US 20120117436 A1, teaches METHOD AND APPARATUS FOR DEFERRED SCHEDULING FOR JTAG SYSTEMS and provides a scheduling of testing in JTAG systems which is analogous with the claimed invention and claims.
Disclosure of the claims follows with inventive :
Regarding claim 1, Portolan et al. discloses a method comprising:
performing a first local test on a first processing portion of an integrated processing system using a first local controller ([0042] “a test instruction set architecture (TISA) is provided for use in performing system testing.” & [0179] “FIG. 5B depicts a mapping from C commands to TISA coding for use by a testing system performing testing of the system test environment 500 of FIG. 5A.” & [0305] “a TAP controller of the system under test”); and
performing a second local test on a second processing portion of the integrated processing using a second local controller different from the first local controller ([0041] “Various system testing capabilities are provided for use in performing testing of a system under test (SUT)”, & [0174] “The JTAG TAP 510 is controlled by a testing system (e.g., such as testing system 110 depicted and described with respect to FIG. 3).” & [0175] The system under test 520 includes a first board 521 (denoted as B1) and a second board 525 (denoted as B2).” & [0176] “The first scan chain 523 and second scan chain 527 are selectable by the IR 512 of JTAG TAP 510 (e.g., IR=0 selects first board B1, IR=1 selects second board B2).” & [0178] “TGT atomic test operations 316, which are translated, by TISA translator 340, into TISA atomic test operations 346.”).
Regarding claim 2, Portolan et al. discloses the method of claim 1, wherein one or more of: the first local test is performed while the second processing portion continues operation independent of the first local test; or the second local test is performed while the first processing portion continues operation independent of the second local test ([0251] “In order to perform such an optimization testing procedure, pattern generator 802, pattern receiver 804, and comparator 806 need to work in parallel, and each must be able to access the TAP independently of the others.”).
Regarding claim 3, Portolan et al. discloses the method of claim 1. wherein the performance of the first local test occurs asynchronously with the performance of the second local test ([0222] “for local testing, interface 609 may be implemented as one or more of a Universal Asynchronous Receiver-Transmitter (UART) interface, serial interface, and the like, as well as various combinations thereof. [0305] “operations over the TAP typically take a long time compared to the time required for a processor to perform a single operation.”).
Regarding claims 4 & 19, Portolan et al. discloses the method of claim 1 & the one or more processors of claim 16; wherein the first local test is performed in response to a determination that the first processing portion is idle ([0431] The exemplary TISA instruction set includes the following values for scan state: [0432] StartState, ScanState, EndState [0433] The scan state codes include: TestLogicReset (TLR), Run Test /Idle (RTI), PauseDR (PDR), PauselR (PIR), ScanDR (SDR), ScanlR (SIR). There is a 4-bit representation per state code, and 12 bits are used to describe the entire state transition sequence for a scan operation.).
Regarding claim 5, Portolan et al. discloses the method of claim 4, wherein the second local test is omitted from being performed during the first local test in response to a determination that at least a portion of the second processing portion is actively performing operations ([0045] “The TS 110 may perform any of the functions typically associated with testing a system under test, such as executing test procedures, providing input data to the system under test, receiving output data from the system under test, processing output data received from the system under test for determining system testing results, and like functions, as well as various combinations thereof.” & [0498] “If a section of the scan chain can be taken in and out the active scan path … The testing scheduler then has knowledge, from the system state, as to whether or not this segment(s) is active” & [0573] “the value of cell X is set such that only the cell X and a static section (denoted as static) are active within the JTAG scan chain 2411.” & [0576] In one embodiment, the associated scheduler is configured to detect a REQUEST to the "dynamic" node of the Circuit Model 2420 when the "dynamic" node of the Circuit Model 2420 is not active ” & [0579] “the state of the super-segment (i.e., the value of cell X) may determine which one or more dynamic segments are active” & [0474] “the scan clock TCK is active only during the scan operations (i.e., steps (iii), (vi), and (ix)), and is frozen in the remaining states.”).
Regarding claim 6, Portolan et al. discloses the method of claim 1, wherein the first local test and the second local test are performed during at least partially overlapping time frames ([0046] “…, the driver operates the vehicle and performs six tests. Three of the tests are performed during hands-off time periods and three of the tests are performed during hands-on time periods. ... For each of the hands-off time periods and hands-on time periods, the output of the hands-off detection algorithm is recorded (for example, transmitted to the testing computer 102 by the electronic controller 106 via the transceiver 116). These outputs represent a plurality of actual test outcomes.).
Regarding claim 7, Portolan et al. discloses the method of claim 1, wherein one or more of the first local test or the second local test is a runtime in-system test ([0059] “FIG. 2, … a test generation tool and a software compiler cooperating to generate test instructions for a system under test. & [0138] “The RUNTEST instruction accepts one or more of the following parameters (all of which are optional): [0139] (1) run_state: the state the interface must maintain during test execution; [0140] (2) run_count: the number of clock cycles the test must take; [0141] (3) run_clk: which clock run_count refers to (TCK: TAP clock, SCK: system clock); [0142] (4) min_time: minimum run time in seconds, expressed as a real number; [0143] (5) max_time: maximum run time in seconds, expressed as a real number”).
Regarding claims 8 & 18, Portolan et al. discloses the method of claim 1 & the one or more processors of claim 17 (wherein the one or more circuits are further to cause); further comprising performing a global test on the first processing portion and the second processing portion using a global controller ([0042] “The TISA combines computer science capabilities with system testing capabilities to provide improved system testing capabilities, including interactive testing capabilities, remote testing capabilities, and various other capabilities … the TISA is formed by combining the atomic operations of a software process with atomic testing operations of a test procedure. ... enables finer-grain control of embedded test execution, remote test execution, and various other improved system testing capabilities” & [0045] “testing a system under test, such as executing test procedures, providing input data to the system under test, receiving output data from the system under test, processing output data received from the system under test for determining system testing results, and like functions, as well as various combinations thereof.” & [0576] “the non-active "dynamic" leaf node is associated (thereby causing the "dynamic" node of the Circuit Model 2420 to become active). More generally, in one embodiment, the scheduler is configured to detect a REQUEST to a non-active leaf node … the non-active leaf node is associated) from "closed" to "open" such that the non-active leaf node becomes active.” & [0579] “the state of the super-segment (i.e., the value of cell X) may determine which one or more dynamic segments are active and the order in which they are to be traversed.”).
Regarding claim 9, Portolan et al. discloses a system comprising:
a first processing portion; a first local controller assigned to the first processing portion and to manage local tests of the first processing portion ([0042] “a test instruction set architecture (TISA) is provided for use in performing system testing.” & [0179] “FIG. 5B depicts a mapping from C commands to TISA coding for use by a testing system performing testing of the system test environment 500 of FIG. 5A.” & [0305] “a TAP controller of the system under test”);;
a data bus; and control circuitry to cause performance of one or more operations ([0225] “HC 601 and TS 610 may include various other components, such as additional processors, additional memories, internal communications buses, input/output modules, additional support circuits (e.g., power supplies), and the like, as well as various combinations thereof.” & [0308] “test processor architecture 1300 may include various other support circuits, such as buses, I/O circuits, and the like, as well as various combinations thereof.) comprising:
allowing data communication between the first processing portion and the first local controller during a first local test of the first processing portion([0306] The cooperation between primary processor 1310 and secondary processor 1320 to perform testing of at least a portion of a system under test is facilitated by communication path 1330. The communication path 1330 may be implemented using any suitable means of communication between primary processor 1310 and secondary processor 1320, which may depend on the type of multi-processor architecture with which the test processor architecture 1300 is implemented. For example, communication path 1330 may include one or more of a main processor interface bus, an auxiliary processor interface, a communication interface (e.g., such as a serializer-deserializer (SERDES) interface or other suitable communication interface), and the like, as well as various combinations thereof.); and
blocking data communication between the first processing portion and the data bus during the first local test of the first processing portion ([0056] “The ISA enables the processor to execute simple instructions, such as reading/writing values from/to memory, perform logical or arithmetical operations on registers, handle interruption, and the like.” & [0324] “The communications may be supported using one or both of the main processor interface bus 1441 and the auxiliary processor interface 1452. The communications between CPU 1410 and TCPU 1420 may include communications associated with instruction exception notification, interrupt access, DMA arbitration, and the like, as well as various combinations thereof. The communications between CPU 1410 and TCPU 1420 and other components of the test co-processor architecture 1400 may include communications associated with reading from memory, writing to memory, and/or any other tasks which may be performed in support of testing the system under test.”).
Regarding claim 10, Portolan et al. discloses the system of claim 9, wherein the operations further comprise allowing data communication between a second processing portion of the system and the data bus during the first local test of the first processing portion ([0221] “The interface 609 may support local communications and/or remote communications between HC 601 and TS 610. Thus, HC 601 may control interactive testing of SUT 620 via TS 610 locally and/or remotely.” & [0324] The CPU 1410 and TCPU 1420 perform testing of the system under test using communication between CPU 1410 and TCPU 1420 and communication between CPU 1410 and/or TCPU 1420 and other components of test co-processor architecture 1400”).
Regarding claim 11, Portolan et al. discloses the system of claim 9, further comprising: a second processing portion; and a second local controller assigned to the second processing portion, the second local controller to manage local tests of the second processing portion, wherein the operations further comprise allowing data communication between the second processing portion and the second local controller during a second local test of the second processing portion ([0176] “FIG. 5A, … second board 525 is accessible via a second scan chain 527. The first scan chain 523 and second scan chain 527 are selectable by the IR 512 of JTAG TAP 510 (e.g., IR=0 selects first board B1, IR=1 selects second board B2).” & [0177] In a test program, … exploiting the second scan chain 527.” & [0259] “a second set of instructions is generated. The second set of instructions includes test instructions associated with the system under test.” & [0263] - [0266] At step 1006, a second set of instructions is generated. The second set of instructions includes test instructions generated by compiling at least one description file associated with the system under test.” & [0267] “the first and second sets of instructions are combined to form a combined set of instructions. In the combined set of instructions, the instructions of the first set of instructions are adapted for use in controlling execution of the test instructions of the second set of instructions.).
Regarding claim 12, Portolan et al. discloses the system of claim 11, wherein the operations further comprise one or more of:
blocking data communication between the second processing portion and the data bus during the second local test of the second processing portion ([0056] “The ISA enables the processor to execute simple instructions, such as reading/writing values from/to memory, perform logical or arithmetical operations on registers, handle interruption, and the like.” & [0324] “The communications between CPU 1410 and TCPU 1420 may include communications associated with instruction exception notification, interrupt access”);
allowing data communication between the first processing portion and the data bus during the second local test of the second processing portion; or allowing data communication between the second processing portion and the data bus during the first local test of the first processing portion ([0306] The cooperation between primary processor 1310 and secondary processor 1320 to perform testing of at least a portion of a system under test is facilitated by communication path 1330. The communication path 1330 may be implemented using any suitable means of communication between primary processor 1310 and secondary processor 1320, which may depend on the type of multi-processor architecture with which the test processor architecture 1300 is implemented. For example, communication path 1330 may include one or more of a main processor interface bus, an auxiliary processor interface, a communication interface (e.g., such as a serializer-deserializer (SERDES) interface or other suitable communication interface), and the like, as well as various combinations thereof.).
Regarding claim 13, Portolan et al. discloses the system of claim 11, wherein the operations further comprise allowing data communication between the data bus and both of the first processing portion and the second processing portion during a global test that includes the first processing portion and the second processing portion ([0306] The cooperation between primary processor 1310 and secondary processor 1320 to perform testing of at least a portion of a system under test is facilitated by communication path 1330. The communication path 1330 may be implemented using any suitable means of communication between primary processor 1310 and secondary processor 1320, which may depend on the type of multi-processor architecture with which the test processor architecture 1300 is implemented. For example, communication path 1330 may include one or more of a main processor interface bus, an auxiliary processor interface, a communication interface (e.g., such as a serializer-deserializer (SERDES) interface or other suitable communication interface), and the like, as well as various combinations thereof.).
Regarding claim 14, Portolan et al. discloses the system of claim 13, wherein the global test is managed by a global controller that is separate from the first local controller and the second local controller ([0223] “for remote testing, interface 609 may be implemented using any suitable communications capabilities, such as Transmission Control Protocol (TCP)/Internet Protocol (IP) or any other suitable communications protocols. This enables remote testing in which the HC 601 and TS 610 may be separated by large geographical distances, and HC 601 will still be able to control TS 610 for purposes of performing testing of SUT 620.” & [0224] In the TISA-based testing environment 600, the HC 601 is able to control, step-by-step, test execution on SUT 620, by controlling operation of TS 610 via a standard connection (e.g., UART, TCP/IP, and the like), thereby enabling interactive testing and debugging capabilities.” & [0225] “HC 601 and TS 610 may include various other components, such as additional processors, additional memories, internal communications buses, input/output modules, additional support circuits (e.g., power supplies), and the like, as well as various combinations thereof.).
Regarding claim 15, Portolan et al. discloses the system of claim 9, wherein the system includes a system-on-a-chip (SoC) ([0339] “the local test memory 1560 may be relatively small since it handles processing of scan chain segments of the scan chain of the system under test, rather than the entire scan chain (as may be required in an on-chip memory).) comprising one or more of: one or more graphics processing units (GPUs); one or more central processing units (CPUs); or one or more hardware accelerators ([0205] “at a fine level, queries from the SC to the TGT may involve registers or even bits. For example, dedicated Scan Segment primitives could significantly accelerate instrument access and TAP reconfiguration, boost code reuse, and provide various other advantages.” & [0526] “The user application elements 1941 may be application threads or any other hardware and/or software based elements configured for use in sending access requests and receiving and processing access responses.” & [0547]-[0551] “various elements of scheduler execution architecture may be implemented using hardware and/or software. For example, scheduler 1930 and user application 1940 each may be implemented in hardware or as a software-based module stored in one or more memories and configured for execution by one or more processors (e.g., TISA processor 1920 and/or any other suitable processor(s), which may depend on the locations of TISA processor 1930, scheduler 1930, and user application 1940).
Regarding claims 16, Portolan et al. discloses one or more processors comprising: one or more circuits to cause performance of a local test on a first processing portion of a processing system using a local controller assigned to the first processing portion while a second processing portion of the processing system continues general operations ([0312] The device 2000 may include CPLD firmware, such as, for example, Actel Igloo Nano AGL250V2-VQG100.sub.--0. Such CPLD firmware may govern linear flash ("LF") control signals for read/write operations, may govern FIFO control signals for write and read operations in a manner of a FIFO dual-ported implementation, and may employ level shifted address and data buses for LF, FIFO, and the OMAP, according to embodiments of the present invention. The device 2000 may include an operating system, such as, for example, OE 2.6.x Open Embedded Linux. The device 2000 may employ the C# Common Language Runtime (2.6.2),).
Regarding claim 17, Portolan et al. discloses the one or more processors of claim 16, wherein the one or more circuits are further to cause performance of a different local test on the second processing portion using a different local controller assigned to the second processing portion while the first processing portion continues general operations ([0311] “a SOM coprocessor subsystem 2040 ... SOM 2040 may also include a storage device 2044, such as, for example, a removable micro SD storage/memory slot. A micro SD card may be used in such a slot as random access storage as well as a source of the boot strap code to initialize the co-processor subsystem 2040. SOM 2040 may also include a power management integrated circuit ("IC") 2048, ... SOM 2040 may also include a processor 2046 such as, for example, a TI Open Multimedia Applications Platform ("OMAP") 3503 processor with 256 MB of random access memory ("RAM") and 256 MB of non-volatile RAM ("NVRAM") in a package-on-package ("POP") package.” & [0399] The second byte stream branch goes into the processor side of the Zango card. The processor side of the Zango card functions to process the byte stream performing the logical operations illustrated in FIG. 31.”).
Regarding claim 20, Portolan et al. discloses the one or more processors of claim 16, wherein the one or more circuits are further to cause performance of at least one of:
allowing data communication between the first processing portion and the local controller during the local test of the first processing portion ([0306] The cooperation between primary processor 1310 and secondary processor 1320 to perform testing of at least a portion of a system under test is facilitated by communication path 1330. The communication path 1330 may be implemented using any suitable means of communication between primary processor 1310 and secondary processor 1320, which may depend on the type of multi-processor architecture with which the test processor architecture 1300 is implemented. For example, communication path 1330 may include one or more of a main processor interface bus, an auxiliary processor interface, a communication interface (e.g., such as a serializer-deserializer (SERDES) interface or other suitable communication interface), and the like, as well as various combinations thereof.);
blocking data communication between the first processing portion and a data bus of the processing system during the local test of the first processing portion; or allowing data communication between the second processing portion and the data bus during the local test of the first processing portion ([0056] “The ISA enables the processor to execute simple instructions, such as reading/writing values from/to memory, perform logical or arithmetical operations on registers, handle interruption, and the like.” & [0324] “The communications may be supported using one or both of the main processor interface bus 1441 and the auxiliary processor interface 1452. The communications between CPU 1410 and TCPU 1420 may include communications associated with instruction exception notification, interrupt access”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See Notice of References cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jalal C CODUROGLU whose telephone number is (408)918-7527. The examiner can normally be reached Monday -Friday 8-6 PT.
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/Jalal C CODUROGLU/Examiner, Art Unit 3665
/DONALD J WALLACE/Primary Examiner, Art Unit 3665
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