DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 07/23/2026 has been considered by Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 6-8, and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 2024/0257735 A1) in view of In et al (US 2020/0105199 A1).
Claim 1, Park (Fig. 1-7E) discloses a display device (Fig. 1; Paragraph [0032]; wherein discloses a display apparatus) comprising:
a light-emitting element (EL; Fig. 5);
a first transistor (DT; Fig. 5) connected between a driving voltage line (EVDD; Fig. 5) and the light-emitting element (EL; Fig. 5);
a capacitor (Cst2; Fig. 5) connected between a gate electrode (DTG; Fig. 5) and a source electrode (DTS; Fig. 5) of the first transistor (DT; Fig. 5);
a second transistor (T3; Fig. 5);
a third transistor (T1; Fig. 5) connected between a reference voltage line (Vinit; Fig. 5) and the gate electrode (DTG; Fig. 5) of the first transistor (DT; Fig. 5), and
a fourth transistor (T5; Fig. 5) connected between the driving voltage line (EVDD: Fig. 5) and a drain electrode (DTD; Fig. 5) of the first transistor (DT; Fig. 5),
wherein the capacitor (Cst2; Fig. 5) and the second transistor (T3; Fig. 5) are connected in series (Fig. 5; wherein figure shows elements T3 and Cst2 connected in series) between the gate electrode (DTG; Fig. 5) of the first transistor (DT; Fig. 5) and the source electrode (DTS; Fig. 5) of the first transistor (DT; Fig. 5),
wherein, during a threshold voltage detection period (Ps; Fig. 6; Paragraph [0070-0071]; wherein discloses a sensing period Ps in which “the threshold voltage Vth of the driving transistor DT may be quickly sensed in the sensing period Ps”’; Fig. 7B), an emission signal (EM1; Fig. 6) is configured to turn on (“ON” during Ps; Fig. 6) the fourth transistor (T5; Fig. 5 and 7B) and a gate signal (SC3; Fig. 6) is configured to turn off (“OFF” during Ps) the second transistor (T3; Fig. 5 and 7B).
Park does not expressly disclose a second transistor connected between the capacitor and the source electrode of the first transistor.
In (Fig. 1-20) discloses a second transistor (TEM1; Fig. 8) connected between the capacitor (CST; Fig. 8) and the source electrode (Paragraph [0083]) of the first transistor (TDR; Fig. 8).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Park’s display device by applying a pixel circuit arrangement, as taught by In, so to use a display device with a pixel circuit arrangement for providing a pixel of a display panel in which a threshold voltage variation or deviation between pixels and a threshold voltage variation or deviation between display panels are compensated using different voltages (Paragraph [0006]).
Claim 2, Park (Fig. 1-7E) discloses further comprising:
a fifth transistor (T4; Fig. 5) connected between a data line (DL; Fig. 5) and the gate electrode (DTG; Fig. 5) of the first transistor (DT; Fig. 5).
Claim 4, Park (Fig. 1-7E) discloses further comprising:
a sixth transistor (T2; Fig. 5) connected between an initialization voltage line (Vref; Fig. 5) and an anode electrode of the light-emitting element (EL; Fig. 5; wherein figure shows electrode of transistor T2 connected to anode of EL).
Claim 6, Park (Fig. 1-7E) discloses further comprising:
a seventh transistor (T6; Fig. 5) connected between the source electrode (DTS; Fig. 5) of the first transistor (DT; Fig. 5) and the anode electrode of the light-emitting element (EL; Fig. 5; wherein figure shows electrode of transistor T6 connected to anode of EL).
Claim 7, Park (Fig. 1-7E) discloses further comprising:
a first gate line (SC4/GL4; Fig. 5) connected to a gate electrode of the fifth transistor (T4; Fig. 5);
a second gate line (SC1/GL1; Fig. 5) connected to a gate electrode of the third transistor (T1; Fig. 5);
a third gate line (SC2/GL2; Fig. 5) connected to a gate electrode of the sixth transistor (T2; Fig. 5);
an emission line (EM1/GL5; Fig. 5) connected to a gate electrode of the fourth transistor (T5; Fig. 5).
In (Fig. 1-20) discloses a fourth gate line (SE; Fig. 8) connected to a gate electrode of the seventh transistor (TEM2; Fig. 8) and a gate electrode of the second transistor (TEM1; Fig. 8).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Park’s display device by applying a pixel circuit arrangement, as taught by In, so to use a display device with a pixel circuit arrangement for providing a pixel of a display panel in which a threshold voltage variation or deviation between pixels and a threshold voltage variation or deviation between display panels are compensated using different voltages (Paragraph [0006]).
Claim 8, Park (Fig. 1-7E) discloses wherein the data line (DL; Fig. 5) transmits a data voltage (Vdata; Fig. 5; Vdata; Fig. 6),
the first gate line (SC4/GL4; Fig. 5) transmits a first gate signal (SC4; Fig. 6), fig.
the second gate line (SC1/GL1; Fig. 5) transmits a second gate signal (SC1; Fig. 6),
the third gate line (SC2/GL2; Fig. 5) transmits a third gate signal (SC2; Fig. 6),
the fourth gate line (SC3/GL3; Fig. 5) transmits a fourth gate signal (SC3; Fig. 6), and
the emission line (EM1/GL5; Fig. 5) transmits an emission signal (EM1; Fig. 6).
Claim 20, Park (Fig. 1-7E) discloses wherein each of the first to seventh transistors (T1-T6 and DT; Fig. 5) comprises an oxide-based active layer (Paragraph [0036]; wherein discloses “ A semiconductor layer of at least some of the transistors may include oxide”).
Fig. 1
Claim 21, Park (Fig. 1-7E) discloses an electronic device (Fig. 1; Paragraph [0032]; wherein discloses a display apparatus) comprising:
a light-emitting element (EL; Fig. 5);
a first transistor (DT; Fig. 5) connected between a driving voltage line (EVDD; Fig. 5) and the light-emitting element (EL; Fig. 5);
a capacitor (Cst2; Fig. 5) connected between a gate electrode (DTG; Fig. 5) and a source electrode (DTS; Fig. 5) of the first transistor (DT; Fig. 5);
a second transistor (T3; Fig. 5);
a third transistor (T1; Fig. 5) connected between a reference voltage line (Vinit; Fig. 5) and the gate electrode (DTG; Fig. 5) of the first transistor (DT; Fig. 5), and
a fourth transistor (T5; Fig. 5) connected between the driving voltage line (EVDD: Fig. 5) and a drain electrode (DTD; Fig. 5) of the first transistor (DT; Fig. 5),
wherein the capacitor (Cst2; Fig. 5) and the second transistor (T3; Fig. 5) are connected in series (Fig. 5; wherein figure shows elements T3 and Cst2 connected in series) between the gate electrode (DTG; Fig. 5) of the first transistor (DT; Fig. 5) and the source electrode (DTS; Fig. 5) of the first transistor (DT; Fig. 5),
wherein, during a threshold voltage detection period (Ps; Fig. 6; Paragraph [0070-0071]; wherein discloses a sensing period Ps in which “the threshold voltage Vth of the driving transistor DT may be quickly sensed in the sensing period Ps”’; Fig. 7B), an emission signal (EM1; Fig. 6) is configured to turn on (“ON” during Ps; Fig. 6) the fourth transistor (T5; Fig. 5 and 7B) and a gate signal (SC3; Fig. 6) is configured to turn off (“OFF” during Ps) the second transistor (T3; Fig. 5 and 7B).
Park does not expressly disclose a second transistor connected between the capacitor and the source electrode of the first transistor.
In (Fig. 1-20) discloses a second transistor (TEM1; Fig. 8) connected between the capacitor (CST; Fig. 8) and the source electrode (Paragraph [0083]) of the first transistor (TDR; Fig. 8).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Park’s display device by applying a pixel circuit arrangement, as taught by In, so to use a display device with a pixel circuit arrangement for providing a pixel of a display panel in which a threshold voltage variation or deviation between pixels and a threshold voltage variation or deviation between display panels are compensated using different voltages (Paragraph [0006]).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 2024/0257735 A1) in view of In et al (US 2020/0105199 A1) as applied to claim 8 above, and further in view of Wu et al (CN 117437886 A).
Claim 9, Park (Fig. 1-7E) discloses wherein in a first initialization period (Pi; Fig. 6; Paragraph [0101]), each of the third gate signal (SC2; Fig. 6) and the fourth gate signal (SC3; Fig. 6) has an active level (“ON” for SC2 and SC3 during Pi; Fig. 6), and each of the first gate signal (SC4; Fig. 6) and the emission signal (EM1; Fig. 6) has an inactive level (“OFF” for EM1 and SC4 during Pi; Fig. 6).
Park in view of In does not expressly disclose wherein in a first initialization period the second gate signal has an inactive level.
Wu (Fig. 1-17) discloses wherein in a first initialization period (t01; Fig. 15) the second gate signal (GB1; Fig. 10 and 15) has an inactive level (GB1; Fig. 15; wherein figure shows GB1 at a low level during period t01).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Park in view of In’s display device by applying a driving method, as taught by Wu, so to use a display device with a driving method for providing can avoid the voltage drop on the driving power line and the characteristic drift of the driving transistor to influence the driving signal transmitted to the luminous element, and ensure the driving circuit to reliably drive the luminous element to emit light, so that the display effect is good (see page 5 of translation).
Claim 10, Park (Fig. 1-7E) discloses wherein in the threshold voltage detection period (Ps; Fig. 6) after the first initialization period (Pi; Fig. 6),
each of the second gate signal (SC1; Fig. 6) and the emission signal (EM1; Fig. 6) has the active level (“ON”; Fig. 6; wherein figure show both EM1 and SC1 being an ON level during Ps period), and
each of the first gate signal (SC4; Fig. 6), the third gate signal (SC2; Fig. 6) and the fourth gate signal (SC3; Fig. 6) has the inactive level (“OFF”; Fig. 6; wherein figure shows all the signals SC2, SC3, and SC4 being an OFF level during PS period).
Claims 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 2024/0257735 A1) in view of In et al (US 2020/0105199 A1) and Wu et al (CN 117437886 A) as applied to claim 10 above, and further in view of Zhu et al (US 2017/0270867 A1).
Claim 11, Park (Fig. 1-7E) discloses wherein in a data write period (Pw; Fig. 6) after the threshold voltage detection period (Ps; Fig. 6),
the first gate signal has (SC4; Fig. 6) the active level (“ON”; Fig. 6; wherein figure shows SC4 with an ON level during Pw),
each of the second gate signal (SC1; Fig. 6) and the third gate signal (SC2; Fig. 6) has the inactive level (“OFF”; Fig. 6; wherein figure shows both SC1 and SC2 with an OFF level during Pw), and
the data voltage (Vdata; Fig. 6) is applied to the data line (DL; Fig. 5).
Park in view of In and Wu does not expressly disclose each of the second gate signal, the third gate signal, the fourth gate signal and the emission signal has the inactive level.
Zhu (Fig. 1A-6) discloses each of the second gate signal (S1; Fig. 1B and 1C; wherein during P3), the third gate signal (S2; Fig. 1B and 1C; wherein during P3), the fourth gate signal (E1; Fig. 4B; wherein figure shows transistor T3 receiving E1 signal) and the emission signal (E1; Fig. 4B; wherein figure shows transistor T5 receiving E1 signal) has the inactive level (P3; Fig. 1C; wherein during P3 the signals S1, S2, and E1 are all a low level).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Park in view of In and Wu’s display device by applying a driving method, as taught by Zhu, so to use a display device with a driving method for providing the brightness evenness of the organic light-emitting display panel may be improved (Paragraph [0125]).
Claim 12, Park (Fig. 1-7E) discloses wherein in a second initialization period (OBS; Fig. 6) after the data write period (Pw; Fig. 6),
each of the third gate signal (SC2; Fig. 6) and the fourth gate signal (SC3; Fig. 6) has the active level (“ON”; Fig. 6; wherein figure shows both SC2 and SC3 with ON level during OBS), and each of the first gate signal (SC4; Fig. 6), the second gate signal (SC1; Fig. 6) and the emission signal (EM1; Fig. 6) has the inactive level (“OFF”; Fig. 6; wherein each signal SC1, SC4, and EM1 have an OFF level during OBS).
Claim 13, Park (Fig. 1-7E) discloses wherein in an emission period (Pe; Fig. 6) otherafter the second initialization period (OBS; Fig. 6),
each of the fourth gate signal (SC3; Fig. 6) and the emission signal (EM1; Fig. 6) has the active level (“ON”; Fig. 6; wherein figure shows both SC3 and EM1 having an ON level during Pe), and
each of the first gate signal (SC4; Fig. 6), the second gate signal (SC1; Fig. 6) and the third gate signal (SC2; fig. 6) has the inactive level (“OFF”; Fig. 6; wherein figure shows the signals SC1, SC2, and SC4 having an OFF level during Pe).
Claim 14, Park (Fig. 1-7E) discloses wherein each of the first to seventh transistors (T1-T6 and DT; Fig. 5) is an n-type transistor (Fig. 5; wherein figure shows n-type transistors).
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 2024/0257735 A1) in view of In et al (US 2020/0105199 A1), Wu et al (CN 117437886 A), and Zhu et al (US 2017/0270867 A1) as applied to claim 13 above, and further in view of Yang et al (US 2017/0147121 A1).
Claim 15, Park in view of In, Wu, and Zhu discloses the display device of claim 13.
Park in view of In, Wu, and Zhu does not expressly disclose wherein a type of the second transistor and a type of at least one of the first transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are different.
Yang (Fig. 1-10) discloses wherein a type of the second transistor (T4; Fig. 6e; wherein figure shows a P-type transistor) and a type of at least one of the first transistor, the third transistor (T2; Fig. 6e), the fourth transistor (T5; Fig. 6e), the fifth transistor (T1; Fig. 6e), the sixth transistor (T3; Fig. 6e), and the seventh transistor are different (Fig. 6e; wherein figure shows at least the transistor T4 of a P-type being different from at least one of T2, T5, T5, and T3 of a N-type).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Park in view of In, Wu, and Zhu’s display device by applying a pixel circuit arrangement, as taught by Yang, so to use a display device with a pixel circuit arrangement for providing so that the operating state of each module in the sub-pixel circuit is the same as that in the third stage (i.e., the light-emitting display stage), which ensures normal display, therefore, an in-cell touch display panel based on OLED panel is achieved (Paragraph [0107]).
Claim 16, Yang (Fig. 1-10) discloses wherein the type of the second transistor (T4; Fig. 6e; wherein figure shows a P-type transistor) and the type of the fifth transistor (T1; Fig. 6e; wherein figure shows a N-type transistor) are different (Fig. 6e).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Park in view of In, Wu, and Zhu’s display device by applying a pixel circuit arrangement, as taught by Yang, so to use a display device with a pixel circuit arrangement for providing so that the operating state of each module in the sub-pixel circuit is the same as that in the third stage (i.e., the light-emitting display stage), which ensures normal display, therefore, an in-cell touch display panel based on OLED panel is achieved (Paragraph [0107]).
Claim 17, Yang (Fig. 1-10) discloses wherein each of the first transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor is an n-type transistor (Fig. 6e; wherein figure shows all the transistors other than the second transistor (T4) are N-type transistors; wherein Yang clearly teaches in figures 6a-6e that the types of the transistors can be changed from all P-type, mostly P-type with one second transistor with N-type, all N-type, and mostly N-type with one second transistor with P-type, therefore the embodiments being claimed by Applicant are well known substitutions), and the second transistor is a p-type transistor (T4; Fig. 6e; wherein figure shows a P-type transistor).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Park in view of In, Wu, and Zhu’s display device by applying a pixel circuit arrangement, as taught by Yang, so to use a display device with a pixel circuit arrangement for providing so that the operating state of each module in the sub-pixel circuit is the same as that in the third stage (i.e., the light-emitting display stage), which ensures normal display, therefore, an in-cell touch display panel based on OLED panel is achieved (Paragraph [0107]).
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 2024/0257735 A1) in view of In et al (US 2020/0105199 A1) as applied to claim 6 above, and further in view of Kim (US 2012/0026146 A1).
Claim 18, Park (Fig. 1-7E) discloses further comprising:
a second gate line (SC1/GL1; Fig. 5) connected to a gate electrode of the third transistor (T1; Fig. 5);
a third gate line (SC2/GL2; Fig. 5) connected to a gate electrode of the sixth transistor (T2; Fig. 5);
an emission line (EM1/GL5; Fig. 5) connected to a gate electrode of the fourth transistor (T5; Fig. 5); and
a fourth gate line (EM2/GL6; Fig. 5) connected to a gate electrode of the seventh transistor (T6; Fig. 5).
Park in view of In does not expressly disclose a first gate line connected to a gate electrode of the fifth transistor and the second transistor.
Kim (Fig. 1-10) discloses a first gate line (S1n; Fig. 9) connected to a gate electrode of the fifth transistor (M2; Fig. 9) and the second transistor (Mc1; Fig. 9).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Park in view of In’s display device by applying a pixel circuit arrangement, as taught by Kim, so to use a display device with a pixel circuit arrangement for providing a pixel that can compensate deterioration of an organic light emitting diode, regardless of voltage drop of a second power supply ELVSS, and an organic light emitting display device using the pixel (Paragraph [0014]).
Claim 19, Kim (Fig. 1-10) discloses wherein the gate electrode of the second transistor (Mc1; Fig. 9) and the gate electrode of the fifth transistor (M2; Fig. 9) are connected to the first gate line (S1n; Fig. 9).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Park in view of In’s display device by applying a pixel circuit arrangement, as taught by Kim, so to use a display device with a pixel circuit arrangement for providing a pixel that can compensate deterioration of an organic light emitting diode, regardless of voltage drop of a second power supply ELVSS, and an organic light emitting display device using the pixel (Paragraph [0014]).
Response to Arguments
Applicant's arguments with respect to claims 1-2, 4, and 6-21 have been considered but are moot in view of the new ground(s) of rejection.
In view of arguments, the references of Park et al (US 2024/0257735 A1), In et al (US 2020/0105199 A1), Wu et al (CN 117437886 A), Zhu et al (US 2017/0270867 A1), Yang et al (US 2017/0147121 A1), and Kim (US 2012/0026146 A1) have been used for new ground rejection.
Claims 1 and 21 are rejected in view of newly discovered reference(s) to Park et al (US 2024/0257735 A1) and In et al (US 2020/0105199 A1).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM J SNYDER whose telephone number is (571)270-3460. The examiner can normally be reached Monday-Friday 8am-4:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh D Nguyen can be reached at (571)272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Adam J Snyder/ Primary Examiner, Art Unit 2623 09/22/2026
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