Prosecution Insights
Last updated: October 02, 2026
Application No. 19/094,087

PROTECTION CIRCUIT AND EMBEDDED MULTI-CHIP SYSTEM

Non-Final OA §102§103
Filed
Mar 28, 2025
Priority
Jan 16, 2025 — TW 114101772
Examiner
PATEL, DHARTI HARIDAS
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Industrial Technology Research Institute
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
1106 granted / 1266 resolved
+19.4% vs TC avg
Moderate +8% lift
Without
With
+7.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
23 currently pending
Career history
1278
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
42.8%
+2.8% vs TC avg
§102
44.1%
+4.1% vs TC avg
§112
2.4%
-37.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1266 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tamegai Publication No. US 2009/0097181. Regarding claim 1, Tamegai discloses a protection circuit, comprising: a first transistor having a first terminal, a second terminal and a control terminal [Fig. 1, transistor 10 having drain, source, and a gate], and configured to receive an input signal through the first terminal and output an output signal through the second terminal in a conducting state; and a first comparator [Fig. 1, 18a], wherein an input terminal of the first comparator is coupled to the first terminal of the first transistor [Fig. 1, (-) terminal of 18a is coupled to the drain terminal of 10], another input terminal of the first comparator is configured to receive a first reference signal [Fig. 1, (+) terminal of 18a is coupled to 18b], an output terminal of the first comparator is coupled to the control terminal of the first transistor [Fig. 1, output terminal of 18a is coupled to the gate of 10], and the first comparator is configured to output a first comparison signal according to a comparison result between the first reference signal and the input signal [par. 0034]. Regarding claim 2, Tamegai further comprises a first voltage-dividing sub-circuit [Fig. 1, comprising R11, R12], connected to the first terminal of the first transistor and configured to perform voltage division on the input signal, wherein the first comparator outputs the first comparison signal according to the comparison result between the first reference signal and the input signal after the voltage division [par. 0034]. Regarding claim 3, Tamegai discloses that the first voltage-dividing sub-circuit comprises a plurality of voltage-dividing elements [Fig. 1, resistors R11, R12] connected to each other, and the first comparator is connected to the plurality of voltage-dividing elements [par. 0034]. Claims 1-3, 11-13, and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hirai Publication No. US 2025/0158608. Regarding claim 1, Hirai discloses a protection circuit, comprising: a first transistor [Fig. 1, 43] having a first terminal, a second terminal and a control terminal [Fig. 1, transistor 43 having drain, source, and a gate], and configured to receive an input signal through the first terminal and output an output signal through the second terminal in a conducting state; and a first comparator [Fig. 1, first voltage detection circuit 1 comprises a first comparator 17], wherein an input terminal of the first comparator is coupled to the first terminal of the first transistor, another input terminal of the first comparator is configured to receive a first reference signal, an output terminal of the first comparator is coupled to the control terminal of the first transistor [Fig. 1, output pf 1 is coupled to the gate of 43], and the first comparator is configured to output a first comparison signal according to a comparison result between the first reference signal and the input signal [par. 0096, 0102, 0103]. Regarding claim 2, Hirai further comprises a first voltage-dividing sub-circuit [Fig. 1, 18], connected to the first terminal of the first transistor and configured to perform voltage division on the input signal, wherein the first comparator outputs the first comparison signal according to the comparison result between the first reference signal and the input signal after the voltage division [par. 0096, 0102, 0103]. Regarding claim 3, Hirai discloses that the first voltage-dividing sub-circuit comprises a plurality of voltage-dividing elements [Fig. 1, 18] connected to each other, and the first comparator is connected to the plurality of voltage-dividing elements [par. 0096]. Regarding claim 11, Hirai discloses an embedded multi-chip system, comprising: a protection circuit [Fig. 1, 101], comprising: a first transistor [Fig. 1, 43] having a first terminal, a second terminal and a control terminal [Fig. 1, transistor 43 having drain, source, and a gate], and configured to receive an input signal through the first terminal and output an output signal through the second terminal in a conducting state; and a first comparator [Fig. 1, first voltage detection circuit 1 comprises a first comparator 17], wherein an input terminal of the first comparator is coupled to the first terminal of the first transistor, another input terminal of the first comparator is configured to receive a first reference signal, an output terminal of the first comparator is coupled to the control terminal of the first transistor [Fig. 1, output pf 1 is coupled to the gate of 43], and the first comparator is configured to output a first comparison signal according to a comparison result between the first reference signal and the input signal [par. 0096, 0102, 0103]. a low dropout regulator [Fig. 1, LDO 60] connected to a battery [Fig. 1, BAT], and configured to generate and provide the input signal to the protection circuit; and a switch control circuit [Fig. 1, Electronic circuit 70] connected to the protection circuit, and configured to control at least one switch element according to the output signal [par. 0056]. Regarding claim 12, Hirai further comprises a first voltage-dividing sub-circuit [Fig. 1, 18], connected to the first terminal of the first transistor and configured to perform voltage division on the input signal, wherein the first comparator outputs the first comparison signal according to the comparison result between the first reference signal and the input signal after the voltage division [par. 0096, 0102, 0103]. Regarding claim 13, Hirai discloses that the first voltage-dividing sub-circuit comprises a plurality of voltage-dividing elements [Fig. 1, 18] connected to each other, and the first comparator is connected to the plurality of voltage-dividing elements [par. 0096]. Regarding claim 15, Hirai discloses that the protection circuit further comprises an inverter [Fig. 6, the first voltage detection circuit 1 comprises an inverter 53] connected to the output terminal of the first comparator [Fig. 1, 17] and the control terminal of the first transistor, and the inverter is configured to control the first transistor to enter the conducting state or a non-conducting state according to the first comparison signal [par. 0102, 0103]. Regarding claim 16, Hirai discloses that the protection circuit further comprises a second comparator [Fig. 7, second voltage detection circuit 2 comprises a comparator 27] and a logic element [Fig. 1, 45], the output terminal of the first comparator and an output terminal of the second comparator are connected to two input terminals of the logic element [Fig. 1, the outputs of 1 and 2 are connected to two input terminals of the NAND gate 45], respectively, the logic element is connected to the control terminal of the first transistor, and the logic element is configured to control the first transistor to enter the conducting state or a non-conducting state according to a comparison result between the first comparison signal from the first comparator and a second comparison signal from the second comparator [par. 0070]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hirai Publication No. US 2025/0158608, in view of Kiryu et al. Patent No. US 4,833,342. Regarding claims 4 and 14, Hirai discloses a voltage dividing circuit comprising a plurality of resistors. However, Hirai does not disclose that the plurality of voltage-dividing elements are a plurality of voltage-dividing transistors, and a gate and a drain of each of the plurality of voltage-dividing transistors are electrically connected to each other. Kiryu discloses a reference potential generating circuit, comprising a plurality of voltage-dividing elements are a plurality of voltage dividing transistors [Fig. 1, Q1-Q8], and a gate and a drain of each of the plurality of voltage-dividing transistors are electrically connected to each other [as shown in Fig. 1]. Hirai and Kiryu are analogous voltage dividing circuits that can be used in protection circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Kiryu’s voltage divider made up of transistors, into Hirai, for the benefit of providing a much lower output resistance without wasting large amounts of idle power. Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Tamegai Publication No. US 2009/0097181, in view of Miller Patent No. US 4,725,765. Regarding claim 5, Tamegai does not further comprise an inverter connected to the output terminal of the first comparator and the control terminal of the first transistor, and the inverter is configured to control the first transistor to enter the conducting state or a non-conducting state according to the first comparison signal. Miller discloses a protection circuit, comprising: a first transistor [Fig. 1, 34]; a first comparator [Fig. 1, comparator 16], a voltage dividing circuit [Fig. 1, comprising resistors 10, 12, 14], and further comprises an inverter [Fig. 1, 21] configured to control the first transistor to enter the conducting state or a non-conducting state according to the first comparison signal [Fig. 1, the output of the comparator 16 is coupled to the input of the inverter 21, and the output of the inverter 21 controls the operation of the transistor 34]. Tamegai and Miller are analogous voltage detection and protection circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Miller’s inverter, into Tamegai, for the benefit of Inverting the logical state of the signal that controls the transistor. Regarding claim 6, Miller further comprises a second comparator [Fig. 1, comparator 18] and a logic element [Fig. 1, NAND gate 24], wherein the output terminal of the first comparator and an output terminal of the second comparator are connected to two input terminals of the logic element, respectively, the logic element is connected to the control terminal of the first transistor, and the logic element is configured to control the first transistor to enter the conducting state or a non-conducting state according to a comparison result between the first comparison signal from the first comparator and a second comparison signal from the second comparator [col. 3 lines 55-68]. Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Tamegai Publication No. US 2009/0097181, in view of Miller Patent No. US 4,725,765, and further in view of Labbus et al. Patent No. US 4,935,836. Regarding claims 7 and 17, Tamegai and Miller do not disclose that an input terminal of the second comparator is connected to a temperature sensor or a process parameter sensor, to output the second comparison signal according to a temperature signal or a process parameter signal. Labbus discloses a protection circuit, comprising a first comparator [Fig. 1, 15], a second comparator [Fig. 1, 13], a first switch [Fig. 1, 12], wherein the input terminal of the second comparator is connected to a temperature sensor or a process parameter sensor [Fig. 1, current sensor 11], to output the second comparison signal according to a temperature signal or a process parameter signal. All three teachings are analogous protection circuits. It would have been obvious to one of ordinary skill in the art at the time of the filing of the claimed invention, to incorporate a current sensor, into Tamegai modified by Miller, for the benefit of controlling the switch based on current and voltage sensors. Allowable Subject Matter Claims 8-10 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance of claims 8, 18: The prior art does not further comprise a second voltage-dividing sub-circuit connected to the second terminal of the first transistor, and configured to perform voltage division on the output signal; and a third comparator, wherein an input terminal of the third comparator is connected to the second voltage-dividing sub-circuit, another input terminal of the third comparator is configured to receive a second reference signal, and the third comparator is configured to output an activation signal according to a comparison result between the second reference signal and the output signal after the voltage division. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DHARTI PATEL whose telephone number is (571)272-8659. The examiner can normally be reached M - F 9 AM - 5 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. DHARTI PATEL Primary Examiner Art Unit 2836 /DHARTI H PATEL/ Primary Examiner, Art Unit 2838
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Prosecution Timeline

Mar 28, 2025
Application Filed
Sep 17, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
95%
With Interview (+7.7%)
2y 3m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1266 resolved cases by this examiner. Grant probability derived from career allowance rate.

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