DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this office action and presented for examination.
Specification
The disclosure is objected to because of the following informalities. Appropriate correction is required.
In [0004], line 3, “can operation on” should be grammatically reworded.
In [0004], line 4, “general-purposed” may have been intended to be “general-purpose”.
In [0014], line 5, “the other lane are disable” should be grammatically reworded.
Paragraph [0021], line 3, discloses “destination registers 113”; however, reference character 113 of FIG. 1 is merely directed to a destination register (singular).
In [0021], lines 3-4, “a predicate elements” should be grammatically reworded.
Paragraph [0022], line 4, discloses “source registers 114”; however, reference character 114 of FIG. 1 is merely directed to a source register (singular).
In [0022], line 6, “clear” may have been intended to be “cleared”.
Paragraph [0023], line 4, discloses “destination registers 113”; however, reference character 113 of FIG. 1 is merely directed to a destination register (singular).
In [0024], line 4, “all of the elements may inactive o\r all of the elements may be active” should be grammatically reworded.
Paragraph [0025], line 4, discloses “only four lanes are depicted in the embodiment of FIG. 1”; however, FIG. 1 appears to show three lanes.
In [0027], line 3, “match name” should be “match the name” for grammatical clarity.
In [0028], line 3, “retain” should be “to retain” for grammatical clarity.
In [0035], line 10, “bemapped” should be “be mapped”.
In [0056], line 10, “cores 625 and 640” should be “cores 635 and 640”.
Drawings
The drawings are objected to because:
All drawings must be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. However, the drawings in the file wrapper do not meet this requirement — see, for example, the array of white dots that causes the lines, text, numbers, and graphics to appear fuzzy and blurry. This may be caused by dithering being applied when a conversion from greyscale to black has taken place; if so, Examiner recommends ensuring that any drawings to be filed do not contain any grey elements.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 14-20 are objected to because of the following informalities. Appropriate correction is required.
In claim 14, line 4, an “and” should be inserted at the end of the line to precede the last recited element of the recited system.
Claims 15-20 are objected to for failing to alleviate the objection of claim 14 above.
In claim 15, lines 2-4, “configured … set” should be “configured … to set” for grammatical clarity.
In claim 16, lines 2-4, “configured … retain” should be “configured … to retain” for grammatical clarity.
Claims 17-19 are objected to for failing to alleviate the objection of claim 16 above.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “destination register” in line 9. However, it is indefinite as to whether this destination register is the same as, or different from, “a destination register” as recited in claim 1, line 5.
Claim 1 recites the limitation “the destination register” in line 16. However, it is indefinite as to whether the antecedent basis for this limitation is “destination register” in claim 1, line 5, or “destination register” in claim 1, line 9. Note that this limitation is also recited in claim 2, line 3; claim 2, line 6; claim 3, line 3; claim 3, lines 4-5; claim 4, line 1; claim 4, line 3; claim 5, line 1; claim 6, line 1; claim 6, line 3; claim 6, line 4; and claim 6, line 5.
Claim 1 recites the limitation “output vector” in line 17. However, it is indefinite as to whether this output vector is the same as, or different from, “output vector” as recited in claim 1, line 5.
Claims 2-6 are rejected for failing to alleviate the rejections of claim 1 above.
Claim 2 recites the limitation “the output vector” in line 2. However, it is indefinite as to whether the antecedent basis for this limitation is “output vector” in claim 1, line 5, or “output vector” in claim 1, line 17. Note that this limitation is also recited in claim 2, line 4, and claim 2, line 6.
Claim 2 recites the limitation “the inactive elements of the output vector” in lines 1-2. However, there is insufficient antecedent basis for this limitation in the claims. Note that, for one previously recited “output vector”, “included in” was recited rather than “of”. Note that this limitation is also recited in claim 2, line 4.
Claim 2 recites the limitation “a determination that the name of the destination register does not match the respective names of the one or more source registers” in lines 2-4. However, in the scenario in which, for example, the name of the destination register matches the name of a first source register of the one or more source registers but not the name of a second source register of the one or more source registers, it is indefinite as to whether this scenario corresponds to a positive determination or a negative determination.
Claim 3 recites the limitation “the output vector” in line 2. However, it is indefinite as to whether the antecedent basis for this limitation is “output vector” in claim 1, line 5, or “output vector” in claim 1, line 17. Note that this limitation is also recited in claim 3, line 5; claim 4, lines 2-3; and claim 6, lines 4-5.
Claim 3 recites the limitation “the inactive elements of the output vector” in lines 1-2. However, there is insufficient antecedent basis for this limitation in the claims. Note that, for one previously recited “output vector”, “included in” was recited rather than “of”. Note that this limitation is also recited in claim 3, line 5; and claim 4, lines 2-3.
Claim 3 recites the limitation “the values from the destination register that correspond to the inactive elements of the output vector” in lines 4-5. However, there is insufficient antecedent basis for this limitation in the claims. Also note that the further limitation “the values from the destination register” (sans “that correspond to the inactive elements of the output vector”) is recited in claim 4, line 1; claim 6, line 1; and claim 6, line 3, and that the further limitation “the values saved from the destination register” is recited in claim 6, line 4; for these further limitations, Examiner recommends likewise adding “that correspond to the inactive elements of the output vector” for antecedent basis clarity.
Claims 4-6 are rejected for failing to alleviate the rejections of claim 3 above.
Claim 6 recites the limitation “active elements of the output vector” in lines 4-5. However, it is indefinite as to whether these active elements of the output vector are the same as, or different from, “active elements of the output vector” as recited in claim 1, line 16.
Claim 7 recites the limitation “performing, by the processor circuit, a comparison of respective names of source registers associated with the one or more operands” in lines 7-8. However, it is indefinite as to whether the recitation of “names of source registers” is implicitly limiting “one or more operands” to be multiple operands.
Claim 7 recites the limitation “writing, by the processor circuit using, active elements of the output vector to the destination register” in lines 13-14. However, it is indefinite as to whether active elements of the output vector are written, or whether active elements of the output vector are used to facilitate writing.
Claims 8-13 are rejected for failing to alleviate the rejections of claim 7 above.
Claim 8 recites the limitation “the inactive elements of the output vector” in lines 1-2. However, there is insufficient antecedent basis for this limitation in the claims. Note that, in claim 7, line 11, “included in” was recited rather than “of”. Note that this limitation is also recited in claim 8, lines 3-4.
Claim 8 recites the limitation “determining that the name of the destination register does not match the respective names of the one or more source registers” in lines 2-3. However, in the scenario in which, for example, the name of the destination register matches the name of a first source register of the one or more source registers but not the name of a second source register of the one or more source registers, it is indefinite as to whether this scenario corresponds to a positive determination or a negative determination.
Claim 8 recites the limitation “the respective names of the one or more source registers” in line 3. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 8 recites the limitation “the one or more source registers” in line 3. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 9 recites the limitation “the inactive elements of the output vector” in lines 1-2. However, there is insufficient antecedent basis for this limitation in the claims. Note that, in claim 7, line 11, “included in” was recited rather than “of”. Note that this limitation is also recited in claim 9, lines 4-5; and claim 10, line 2.
Claim 9 recites the limitation “the values from the destination register that correspond to the inactive elements of the output vector” in lines 4-5. However, there is insufficient antecedent basis for this limitation in the claims. Also note that the further limitation “the values from the destination register” (sans “that correspond to the inactive elements of the output vector”) is recited in claim 10, line 1; claim 12, line 1; and claim 12, line 2, and that the further limitation “the values saved from the destination register” is recited in claim 12, line 3; for these further limitations, Examiner recommends likewise adding “that correspond to the inactive elements of the output vector” for antecedent basis clarity.
Claim 9 recites the limitation “the one or more source registers” in line 3. However, there is insufficient antecedent basis for this limitation in the claims.
Claims 10-12 are rejected for failing to alleviate the rejections of claim 9 above.
Claim 12 recites the limitation “active elements of the output vector” in lines 3-4. However, it is indefinite as to whether these active elements of the output vector are the same as, or different from, “active elements of the output vector” as recited in claim 7, line 13.
Claim 14 recites the limitation “perform, the one or more operands and the predicate vector, the operation to generate an output vector” in lines 7-8. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to whether the one or more operands and the predicate vector, or the operation, are/is being performed.
Claim 14 recites the limitation “perform a comparison of respective names of source registers associated with the one or more operands” in lines 9-10. However, it is indefinite as to whether the recitation of “names of source registers” is implicitly limiting “one or more operands” to be multiple operands.
Claim 14 recites “at least one vector instruction that specifies an operation, one or more operands, and a predicate vector that includes a plurality of predicate elements; a processor circuit configured to: fetch the at least one vector instruction from the memory circuit” in lines 2-6. However, it is indefinite as to whether a same operation is specified by each of the at least one vector instruction, or whether a potentially different corresponding operation is specified for each of the at least one vector instruction. Additionally, in the latter case, it is unclear as to which potentially different corresponding operation provides antecedent basis for “the operation” recited in claim 14, line 7, and claim 20, line 2. Similarly, it is indefinite as to whether a same one or more operands is specified by each of the at least one vector instruction, or whether a potentially different corresponding one or more operands is specified for each of the at least one vector instruction. Additionally, in the latter case, it is unclear as to which potentially different corresponding one or more operands provides antecedent basis for “the one or more operands” recited in claim 14, line 7; and claim 14, line 10. Similarly, it is indefinite as to whether a same predicate vector that includes a plurality of predicate elements is specified by each of the at least one vector instruction, or whether a potentially different corresponding predicate vector that includes a plurality of predicate elements is specified for each of the at least one vector instruction. Additionally, in the latter case, it is unclear as to which potentially different corresponding predicate vector provides antecedent basis for “the predicate vector” recited in claim 14, line 7; claim 14, line 12; claim 14, line 15; and claim 18, line 3.
Claims 15-20 are rejected for failing to alleviate the rejections of claim 14 above.
Claim 15 recites the limitation “the inactive elements of the output vector” in lines 1-2. However, there is insufficient antecedent basis for this limitation in the claims. Note that, in claim 14, lines 11-12, “included in” was recited rather than “of”. Note that this limitation is also recited in claim 15, line 4.
Claim 15 recites the limitation “a determination that the name of the destination register does not match the respective names of the one or more source registers” in lines 2-4. However, in the scenario in which, for example, the name of the destination register matches the name of a first source register of the one or more source registers but not the name of a second source register of the one or more source registers, it is indefinite as to whether this scenario corresponds to a positive determination or a negative determination.
Claim 15 recites the limitation “the respective names of the one or more source registers” in lines 3-4. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 15 recites the limitation “the one or more source registers” in lines 3-4. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 16 recites the limitation “the inactive elements of the output vector” in line 1-2. However, there is insufficient antecedent basis for this limitation in the claims. Note that, in claim 14, lines 11-12, “included in” was recited rather than “of”. Note that this limitation is also recited in claim 16, line 5; and claim 17, lines 2-3.
Claim 16 recites the limitation “the values from the destination register that correspond to the inactive elements of the output vector” in lines 4-5. However, there is insufficient antecedent basis for this limitation in the claims. Also note that the further limitation “the values from the destination register” (sans “that correspond to the inactive elements of the output vector”) is recited in claim 17, line 1; claim 19, line 1; and claim 19, line 3, and that the further limitation “the values saved from the destination register” is recited in claim 19, line 4; for these further limitations, Examiner recommends likewise adding “that correspond to the inactive elements of the output vector” for antecedent basis clarity.
Claim 16 recites the limitation “the one or more source registers” in line 4. However, there is insufficient antecedent basis for this limitation in the claims.
Claims 17-19 are rejected for failing to alleviate the rejections of claim 16 above.
Claim 19 recites the limitation “active elements of the output vector” in lines 4-5. However, it is indefinite as to whether these active elements of the output vector are the same as, or different from, “active elements of the output vector” as recited in claim 14, line 14.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-6 and 14-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the claim(s) can be interpreted as software per se and thus can be made without an actual hardware apparatus. While the claim(s) do recite circuitry, paragraph [0067] discloses “a storage medium that specifies the circuitry”; paragraph [0076] discloses “a circuit design specified by design information 815”; paragraph [0077] discloses “design information describes a circuit”; and paragraph [0102] discloses “HDL description is the manner that is used to transform the structure of a circuit, unit, or component to the next level of implementational detail”, for example. As such, Examiner recommends inserting the limitation “hardware” in an appropriate part of the claim and all relevant places in further dependent claims (e.g. replacing the limitation “execution circuit” with the limitation “hardware execution circuit”, and replacing the limitation “processor circuit” with the limitation “hardware processor circuit”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Valentine et al. (US 20130305020 A1) disclose “[w]hile the zeroing operation is illustrated only relative to an operation where the destination is different from the sources, zeroing also works where the second source and destination are the same” (see paragraph [0337]), which is relevant to the claimed source register name, destination register name, and setting inactive elements of the output vector to logical-0 values.
Beckmann et al. (US 20220206945 A1) discloses “a destination element is not updated with the result of the operation if the corresponding writemask bit is not set; instead, the destination element value must be preserved (merging-masking) or it must be zeroed out (zeroing-masking) … the masking can be used for zeroing instead of merging, so that the masked-out elements are updated with 0 instead of preserving the old value. The zeroing behavior is provided to remove the implicit dependency on the old value when it is not needed” (see paragraph [0153]), which is relevant to the claimed predicate vector, writing logical-0 values, masking, and retaining values, and the dependency subject matter of paragraph [0017].
Walters et al. (US 20200117457 A1) discloses “For a predicated instruction, different options are available for controlling what value should be specified in an inactive portion of the destination register which is not being updated based on the processing result resulting from applying the corresponding processing operation to one or more operands. For example, for a zeroing predicated instruction, the inactive portions to the destination register are set to zero. … It is also possible to provide a merging predicated instruction” (see paragraphs [0013]-[0014]), which is relevant to the claimed predicate vector, writing logical-0 values, and retaining values.
Corbal et al. (US 20140052968 A1) disclose “A formal format for the VSMADD instruction may be VSMADD R1; k; z; R2; R3; R4/M where k corresponds to the mask vector and z corresponds toa bit select to establish whether zeroing-masking or merging-masking apply. Zeroing-masking writes zeroes to the destination if the mask bit is zero, while merging-masking leaves the destination unchanged” (see paragraph [0030]), which is relevant to the claimed predicate vector, writing logical-0 values, retaining values, source register name, and destination register name.
Ould-Ahmed-Vall et al. (US 20140059322 A1) disclose “masking is used to decide whether a destination element in a vector receives the value of an operation (in this case, the broadcasted value from the source) or receives some other value. There are two types of masking employed by different embodiments of the invention: (1) zeroing masking: in this case every destination element with a corresponding mask bit of 0 will receive a value of zero; and (2) merging masking: in this case every destination element with a mask bit of 0 retains its old value. In one embodiment, for each instruction that allows masking there is one bit that decides which type of masking it uses, in other words all destination elements for that instructions that have a mask bit of 0 will either retain their old values or all receive 0” (see paragraph [0066]), which is relevant to the claimed predicate vector, writing logical-0 values, retaining values, and masking.
Rupley, II et al. (US 20050081017 A1) disclose “[e]fficiency of the renaming mechanism in an out-of-order processor my drive processor performance. That is, the renaming mechanism and its associated physical register file may represent critical resources for an out-of-order processor architecture. Implementation of predication on such processors poses interesting issues” (see paragraph [0009]), which is relevant to instant paragraph [0017].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH E VICARY whose telephone number is (571)270-1314. The examiner can normally be reached Monday to Friday, 9:00 AM to 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at (571)270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KEITH E VICARY/Primary Examiner, Art Unit 2183
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