Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending.
Claim Objections
Claim 5 is objected to because of the following informalities: typographical error.
“the each of” in line 2 would better be “each of”. Appropriate correction is required.
Claim 9 is objected to because of the following informalities: typographical error. “the each of” in line 2 would better be “each of”. “a eleventh” in line 33 would better be “an eleventh”. Appropriate correction is required.
Claim 10 is objected to because of the following informalities: typographical error. “a eleventh” in line 33 would better be “an eleventh”. Appropriate correction is required.
Claim 15 is objected to because of the following informalities: typographical error. “the each of” in line 2 would better be “each of”. Appropriate correction is required.
Claim 18 is objected to because of the following informalities: typographical error. “the each of” in line 2 would better be “each of”. “a eleventh” in line 33 would better be “an eleventh”. Appropriate correction is required.
Claim 19 is objected to because of the following informalities: typographical error. “a eleventh” in line 33 would better be “an eleventh”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-7, 11-13, 16-17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Han et al. (China Patent Application CN108154831A, hereinafter “Han”).
Regarding Claim 1, Han teaches a gate driver (par 0004 Fig 1 gate driving circuit 10), comprising:
a first output stage through a N-th output stage (paras 0004,0058 Fig 1 each [of a first through an nth] shift register unit [output] is connected to a corresponding gate line); and
a sensing stage (par 0065 Fig 2 detection circuit 20 of the shift register unit can be set in a certain stage of the gate drive circuit, such as the first stage shift register unit 10), wherein:
each of the first output stage through the N-th output stage is configured to output a gate signal in response to a voltage of a control node (par 0055 Fig 2 third transistor T3 [of each stage] can be used to respond to the voltage signal of the pull-up node PU to transmit the clock signal to the signal output terminal OUT), and
the sensing stage:
comprises a hold transistor configured to turn on in response to the voltage of the control node (par 0055 Fig 2 hold transistor T3 [of the sensing stage] configured to turn on in response to the voltage signal of the pull-up node PU), and
is configured to sense a threshold voltage of the hold transistor of the sensing stage (par 0066 Fig 2 sensing stage/detection circuit 20 sample the voltage signal of the sampling node S when the signal output terminal OUT of the shift register unit 10 is connected to the sampling node S, so that the sampling module can obtain the threshold voltage Vth of the output transistor of the shift register unit 10, namely the third transistor T3, based on the voltage signal).
Regarding Claim 2, Han teaches the gate driver of claim 1, wherein the sensing stage further comprises:
a sensing transistor connected to an electrode of the hold transistor of the sensing stage and configured to turn on in response to the voltage of the control node (par 0062 Fig 2 first control element [par 0071 sensing transistor] MS1 can be turned on in response to the first control signal so that the signal output terminal OUT of the shift register unit is connected to the sampling node S).
Regarding Claim 3, Han teaches the gate driver of claim 2, wherein
the sensing transistor of the sensing stage is turned on when the hold transistor of the sensing stage is turned on (par 0079 Fig 2 sensing transistor MS1 is turned on and the third transistor T3, i.e. the output transistor, is also turned on under the action of the pull-up node PU).
Regarding Claim 6, Han teaches the gate driver of claim 1, wherein
the sensing stage is configured to sense the threshold voltage of the hold transistor of the sensing stage when a display device is turned on (par 0065 Fig 2 detection circuit 20 detection time can be set in the interval between two adjacent frame scans, a time when clearly the display is turned on) or turned off.
Regarding Claim 7, Han teaches the gate driver of claim 1, wherein
the sensing stage is configured to sense the threshold voltage of the hold transistor of the sensing stage when a display device is driven (par 0065 Fig 2 detection circuit 20 detection time can be set in the interval between two adjacent frame scans; par 0073,0074 the sensing comprises at least driving display device portions MS1 and SW1 to be turn on, and thus the sensing stage is configured to sense the threshold voltage of the hold transistor of the sensing stage when [at least a portion of] a display device is driven).
Claim 11 presents the limitations of Claim 1 in a different claim category, and therefore Claim 11 is rejected with a rationale similar to Claim 6, mutatis mutandis.
Claim 12 presents the limitations of Claim 2 in a different claim category, and therefore Claim 12 is rejected with a rationale similar to Claim 2, mutatis mutandis.
Claim 13 presents the limitations of Claim 3 in a different claim category, and therefore Claim 13 is rejected with a rationale similar to Claim 3, mutatis mutandis.
Claim 16 presents the limitations of Claim 6 in a different claim category, and therefore Claim 16 is rejected with a rationale similar to Claim 6, mutatis mutandis.
Claim 17 presents the limitations of Claim 7 in a different claim category, and therefore Claim 17 is rejected with a rationale similar to Claim 7, mutatis mutandis.
Regarding Claim 20, Han teaches an electronic device (par 0091 display device), comprising:
a display panel comprising pixels (par 0091 comprises a display panel [comprising pixels with gate terminals of switching transistors to be driven]);
a gate driver configured to provide gate signals to the pixels (par 0084 Fig 2,3 gate driving circuit 10 to provide gate driving signals for the scan lines [of pixels with gate terminals of switching transistors to be driven] of the display panel);
a driving controller configured to control the gate driver (par 0088 Fig 8 control module 40 comprises a calculation unit and a voltage regulation unit; the calculation unit may be used to determine whether the difference between the threshold voltage Vth of the output transistor and the reference threshold voltage exceeds a preset value, and send a voltage regulation control signal when the difference exceeds the preset value; the voltage regulation unit may be used with the voltage regulation control signal to adjust the drive voltage of the shift register/gate driver unit); and
a processor configured to control the driving controller (paras 0091,0092 display device with a display panel may be a computer [a processor which may control the driving controller]), wherein
the gate driver comprises:
a first output stage through a N-th output stage (paras 0004,0058 Fig 1 each [of a first through an nth] shift register unit [output] is connected to a corresponding gate line); and
a sensing stage (par 0065 Fig 2 detection circuit 20 of the shift register unit can be set in a certain stage of the gate drive circuit, such as the first stage shift register unit 10), wherein:
each of the first output stage through the N-th output stage is configured to output a gate signal in response to a voltage of a control node (par 0055 Fig 2 third transistor T3 [of each stage] can be used to respond to the voltage signal of the pull-up node PU to transmit the clock signal to the signal output terminal OUT), and
the sensing stage:
comprises a hold transistor, which is turned on in response to the voltage of the control node (par 0055 Fig 2 hold transistor T3 [of the sensing stage] configured to turn on in response to the voltage signal of the pull-up node PU), and
is configured to sense a threshold voltage of the hold transistor of the sensing stage (par 0066 Fig 2 sensing stage/detection circuit 20 sample the voltage signal of the sampling node S when the signal output terminal OUT of the shift register unit 10 is connected to the sampling node S, so that the sampling module can obtain the threshold voltage Vth of the output transistor of the shift register unit 10, namely the third transistor T3, based on the voltage signal).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4, 5, 8, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (China Patent Application CN108154831A, hereinafter “Han”) in view of Matsuda (Japan Patent Application JP2006174294A).
Regarding Claim 4, Han teaches the gate driver of claim 1, wherein
a compensation voltage is applied to a large, the control module 40 automatically adjusts the drive signal of the shift register unit, thereby effectively extending the service life of the shift register unit).
However, Han appears not to expressly teach a compensation voltage is applied to a back gate electrode of the hold transistor.
Matsuda teaches a compensation voltage is applied to a back gate electrode of the hold transistor (par 0012 Fig 2 a transistor that outputs a voltage input from the drain as an output signal from the source in response to a voltage applied to its back gate).
Han and Matsuda are analogous art as they each pertain to gate driving circuits. It would have been obvious to a person of ordinary skill in the art to modify the gate driving circuit of Han with the inclusion of the compensation voltage being applied to a back gate electrode of the hold transistor of Matsuda. The motivation would have been in order to provide that the driver circuit of the present invention compensates for threshold fluctuations by applying a threshold voltage shift to the back gate (Matsuda par 0012).
Regarding Claim 5, Han as modified teaches the gate driver of claim 4, wherein:
the each of the first output stage through the N-th output stage comprises a hold transistor configured to turn on in response to the voltage of the control node (par 0055 Fig 2 hold transistor T3 [of each stage] can be used to respond to the voltage signal of the pull-up node PU to transmit the clock signal to the signal output terminal OUT), and
when the compensation voltage is applied to the control module 40 automatically adjusts the drive signal of[each] shift register unit).
However, Han appears not to expressly teach the compensation voltage is applied to the back gate electrode of the hold transistor.
Matsuda teaches a compensation voltage is applied to a back gate electrode of the hold transistor (par 0012 Fig 2 a transistor that outputs a voltage input from the drain as an output signal from the source in response to a voltage applied to its back gate).
Han and Matsuda are analogous art as they each pertain to gate driving circuits. It would have been obvious to a person of ordinary skill in the art to modify the gate driving circuit of Han with the inclusion of the compensation voltage being applied to a back gate electrode of the hold transistor of Matsuda. The motivation would have been in order to provide that the driver circuit of the present invention compensates for threshold fluctuations by applying a threshold voltage shift to the back gate (Matsuda par 0012).
Regarding Claim 8, Han teaches the gate driver of claim 1. However, Han appears not to expressly teach wherein
the hold transistor of the sensing stage is an N-channel metal-oxide-semiconductor (NMOS) transistor.
Matsuda teaches wherein
the hold transistor of the sensing stage is an N-channel metal-oxide-semiconductor (NMOS) transistor (par 0035 Fig 2 the output transistor M1, and the transistors M2 and M3 (and M1a and M1b, which will be described later) are all n-channel FETs).
Han and Matsuda are analogous art as they each pertain to gate driving circuits. It would have been obvious to a person of ordinary skill in the art to modify the gate driving circuit of Han with the inclusion of the N-channel FETs of Matsuda. The motivation would have been in order to provide that the driver circuit of the present invention compensates for threshold fluctuations by applying a threshold voltage shift to the output FET’s back gate (Matsuda par 0012, 0038).
Claim 14 presents the limitations of Claim 4 in a different claim category, and therefore Claim 14 is rejected with a rationale similar to Claim 4, mutatis mutandis.
Claim 15 presents the limitations of Claim 5 in a different claim category, and therefore Claim 15 is rejected with a rationale similar to Claim 5, mutatis mutandis.
Allowable Subject Matter
Claims 9-10 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if rewritten to overcome any objections thereto.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 9,18:
While closest prior art Hong (20230105266 A1) teaches a portion of the limitations of Claim 9, namely "the gate driver of claim 1, wherein the each of the first output stage through the N-th output stage comprises:
a first transistor comprising a gate electrode configured to receive a first carry clock signal, a first electrode configured to receive an input signal, and a second electrode connected to a first control node (par 0055 Fig 2 transistor T1/T1a receive a first carry clock signal C(n-2), first electrode configured to receive an input signal C(n-2), a second electrode connected to a first control node;
a second transistor comprising a gate electrode configured to receive a global control signal, a first electrode configured to receive a low gate voltage, and a second electrode connected to the first control node (par 0061 Fig 2 transistor T3nB/T3nC receive a global control signal VST, first electrode configured to receive a low gate voltage GVSS2, a second electrode connected to a first control node Q);
a third transistor comprising a gate electrode connected to the first control node, a first electrode configured to receive a high gate voltage, and a second electrode connected to a middle node of the first transistor and a middle node of the second transistor (par 0056 Fig 2 transistor T3Q gate electrode connected to the first control node Q, first electrode connected to GVDD, second electrode connected to a middle node of the first transistor and a middle node of the second transistor);
an eighth transistor comprising a gate electrode connected to the first control node, a first electrode configured to receive a gate clock signal, and a second electrode configured to generate a gate signal (par 0056 Fig 2 transistor T6 gate electrode connected to the first control node Q, first electrode configured to receive a gate clock signal SCCLK(n), ) a second electrode configured to generate a gate signal SCOUT(n));
a ninth transistor comprising a gate electrode connected to the second control node, a first electrode configured to receive the low gate voltage, a second electrode configured to generate the gate signal, and a back gate electrode configured to receive a first compensation voltage (par 0056 Fig 2 transistor T7 gate electrode connected to the second control node Qb, first electrode configured to receive a low gate voltage GVSS0, a second electrode configured to generate the gate signal SCOUT(n))”;
the prior art of record fails to teach or fairly suggest the particular limitations of Claim 9, namely “a fourth transistor comprising a gate electrode configured to receive a second carry clock signal, a first electrode connected to the first control node, and a second electrode;
a fifth transistor comprising a gate electrode connected to a second control node, a first electrode connected to the second electrode of the fourth transistor, and a second electrode configured to generate a carry signal;
a sixth transistor comprising a gate electrode connected to the first control node, a first electrode configured to receive the second carry clock signal, and a second electrode configured to generate the carry signal;
a seventh transistor comprising a gate electrode connected to the second control node, a first electrode configured to receive a second low gate voltage, a second electrode configured to generate the carry signal, and a back gate electrode configured to receive a second compensation voltage;
a tenth transistor comprising a gate electrode configured to receive the high gate voltage, a first electrode configured to receive the high gate voltage, and a second electrode;
a eleventh transistor comprising a gate electrode connected to the second electrode of the tenth transistor, a first electrode configured to receive the high gate voltage, and a second electrode connected to the second control node;
a twelfth transistor comprising a gate electrode connected to the first control node, a first electrode configured to receive the second low gate voltage, and a second electrode connected to the second control node;
a thirteenth transistor comprising a gate electrode connected to the first control node, a first electrode configured to receive the low gate voltage, and a second electrode connected to the second electrode of the tenth transistor and the gate electrode of the eleventh transistor;
a first capacitor comprising a first electrode connected to the first control node, and a second electrode connected to the second electrode of the fifth transistor, the second electrode of the sixth transistor, and the second electrode of the seventh transistor; and
a second capacitor comprising a first electrode connected to the second control node, and a second electrode connected to the second electrode of the tenth transistor, the gate electrode of the eleventh transistor, and the second electrode of the thirteenth transistor" in combination with all other limitations of the claim and of claims on which the claim depends.
Claim 10,19:
While closest prior art Hong (20230105266 A1) teaches a portion of the limitations of Claim 10, the prior art of record fails to teach or fairly suggest the particular limitations of Claim 10, namely "the gate driver of claim 1, wherein the sensing stage comprises:
a first transistor comprising a gate electrode configured to receive a first carry clock signal, a first electrode configured to receive an N-th gate signal, and a second electrode connected to a first control node (par 0055 Fig 2 transistor T1/T1a receive a first carry clock signal C(n-2), first electrode configured to receive an N-th gate signal C(n-2), a second electrode connected to a first control node;
a second transistor comprising a gate electrode configured to receive a global control signal, a first electrode configured to receive a low gate voltage, and a second electrode connected to the first control node (par 0061 Fig 2 transistor T3nB/T3nC receive a global control signal VST, first electrode configured to receive a low gate voltage GVSS2, a second electrode connected to a first control node Q);
a third transistor comprising a gate electrode connected to the first control node, a first electrode configured to receive a high gate voltage, and a second electrode connected to a middle node of the first transistor and a middle node of the second transistor (par 0056 Fig 2 transistor T3Q gate electrode connected to the first control node Q, first electrode connected to GVDD, second electrode connected to a middle node of the first transistor and a middle node of the second transistor);
an eighth transistor comprising a gate electrode connected to the first control node, a first electrode configured to receive a gate clock signal, and a second electrode (par 0056 Fig 2 transistor T6 gate electrode connected to the first control node Q, first electrode configured to receive a gate clock signal SCCLK(n), ) a second electrode configured to generate a gate signal SCOUT(n));”,
the prior art of record fails to teach or fairly suggest the particular limitations of Claim 9, namely “a fourth transistor comprising a gate electrode configured to receive a second carry clock signal, a first electrode connected to the first control node, and a second electrode;
a fifth transistor comprising a gate electrode connected to a second control node, a first electrode connected to the second electrode of the fourth transistor, and a second electrode;
a sixth transistor comprising a gate electrode connected to the first control node, a first electrode configured to receive the second carry clock signal, and a second electrode connected to the second electrode of the fifth transistor;
a seventh transistor comprising a gate electrode connected to the second control node, a first electrode configured to receive a second low gate voltage, a second electrode connected to the second electrode of the fifth transistor and the second electrode of the sixth transistor, and a back gate electrode configured to receive a second compensation voltage;
a ninth transistor comprising a gate electrode connected to the second control node, a first electrode configured to receive the low gate voltage, a second electrode connected to the second electrode of the eighth transistor, and a back gate electrode configured to receive a first compensation voltage;
a tenth transistor comprising a gate electrode configured to receive the high gate voltage, a first electrode configured to receive the high gate voltage, and a second electrode;
a eleventh transistor comprising a gate electrode connected to the second electrode of the tenth transistor, a first electrode configured to receive the high gate voltage, and a second electrode connected to the second control node;
a twelfth transistor comprising a gate electrode connected to the first control node, a first electrode configured to receive the second low gate voltage, and a second electrode connected to the second control node;
a thirteenth transistor comprising a gate electrode connected to the first control node, a first electrode configured to receive the low gate voltage, and a second electrode connected to the second electrode of the tenth transistor and the gate electrode of the eleventh transistor;
a first capacitor comprising a first electrode connected to the first control node and a second electrode connected to the second electrode of the fifth transistor, the second electrode of the sixth transistor, and the second electrode of the seventh transistor;
a second capacitor comprising a first electrode connected to the second control node and a second electrode connected to the second electrode of the tenth transistor, the gate electrode of the eleventh transistor, and the second electrode of the thirteenth transistor;
a first sensing transistor comprising a gate electrode configured to receive a voltage of the second control node, a first electrode connected to the second electrode of the eighth transistor and the second electrode of the ninth transistor, and a second electrode configured to generate a first sensing current; and
a second sensing transistor comprising a gate electrode configured to receive the voltage of the second control node, a first electrode connected to the second electrode of the fifth transistor, the second electrode of the sixth transistor, and the second electrode of the seventh transistor, and a second electrode configured to generate a second sensing current" in combination with all other limitations of the claim and of claims on which the claim depend.
Conclusion
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/MARK EDWARDS/Primary Examiner, Art Unit 2624