Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1 and 10
b. Pending: 1-15
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) is submitted on 3/31/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (CN 115346568).
Regarding independent claim 1, Li discloses a memory device (Figs. 1-18) including a plurality of memory cells (Fig. 4 shows memory array), comprising:
a memory cell array in which a plurality of unit memories are arranged in an array, each of the unit memory including a first non-volatile memory cell and a second non-volatile memory cell, which store data in a complementary manner (Fig. 4 and pg:7-8 describes each column of the array 100 has a bit line BL and a reverse bit line (inverting bit line) BLB. In these examples, the memory array 100 has a Y column, so that the bit line is designated as bit line BL [0] to BL [Y-1] and BLB [0] to BLB [Y-1]. Each of the plurality of memory cells 200 is connected to one of the bit lines BL and BLB in its column);
a detection unit (Fig. 6 shows sense amplifier and read circuit) that detects the data stored in the first and second non-volatile memory cells for each unit memory (pg:9 describes sense amplifier SA 300 includes a cross coupling latch 304 (a pair of cross-connected inverters) between the bit line BL and the reverse bit line BLB); and
an operation unit (Fig. 4 shows CIM circuit 52 ) that sets weight data based on output of the detection unit and performs a multiplication operation on input data and the weight data (CIM circuit 52 includes a multiplication circuit 130 and an adder circuit 140. The input terminal is configured to receive the CIM input signal IN, and the multiplication circuit 130 is configured to multiply the selected weight signal stored in the memory array 100 by the input signal IN to generate a plurality of partial product P. The multiplication circuit 130 includes multiplication circuits 130-1, 130-2 ... 130-n).
Regarding claim 3, Li discloses all the elements of claim 1 as above and further the detection unit includes latches that amplify the data stored in the first non-volatile memory cell and the second non-volatile memory cell and output a first amplified value and a second amplified value, respectively (pg:9 describes sense amplifier SA 300 includes a cross coupling latch 304 (a pair of cross-connected inverters) between the bit line BL and the reverse bit line BLB).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (CN 115346568) in view of Li (US 20200301668), herein referred as Li_second.
Regarding claim 2, Li discloses all the elements of claim 1 as above and through Li_second further the unit memory includes: a first switching element which is switched by a word line signal and of which the other end is connected to a first source line; a second switching element which is switched by the word line signal and of which the other end is connected to a second source line; a first resistive memory cell of which one end is connected to a first bit line LBL and the other end is connected to one end of the first switching element; and a second resistive memory cell of which one end is connected to a second bit line and the other end is connected to one end of the second switching element, and the second source line is applied with an inverted signal of the signal applied to the first source line, the second bit line is applied with an inverted signal of the signal applied to the first bit line, and the first resistive memory cell and the second resistive memory cell store data in a complementary manner (Fig. 2A-1 shows above connection).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Li_second to Li in order to provide with memory bit cell circuit configured to store a weight data and a complement weight data complementary to the weight data as taught by Li_second ([0010]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (CN 115346568) in view of Sumbul et al. (US 11061646).
Regarding claim 8, Li discloses all the elements of claim 1 as above and through Sumbul further the operation unit selects, as the weight data, the value detected by the detection unit based on the data stored in the first non-volatile memory cell, and the operation unit includes a NAND arithmetic circuit that receives the input data and the weight data as input (Fig. 7 and (45)-(48) describes multiply operation in a Bit-line Processor (BLP) using one analog and one digital operand).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Sumbul to Li in order to provide with Compute-in memory techniques. Compute-in memory (CIM) (which can also be referred to as in-memory processing) involves performing compute operations within a memory array. Thus, compute operations are performed directly on the data read from the memory cells instead of transferring the data to a digital processor for processing. By avoiding transferring some data to the digital processor, the bandwidth limitations associated with transferring data back and forth between the processor and memory in a conventional computer system are reduced as taught by Sumbul ((18)).
Claims 10-12 and 14 recite similar limitations of claims 1-3 and 8 but drafted in method format. Henceforth they are rejected similarly as above.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (CN 115346568) in view of Guidash et al. (CN 105981370).
Regarding claim 13, Li discloses all the elements of claim 12 as above and through Guidash further the output of the transfer gate charges a capacitor connected to the output end of the transfer gate through capacitive coupling (Claim 9).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Guidash to Li in order to provide with low and high signal read path using different conversion gain, so it reduces the low signal noise under the condition without compromising dynamic range as taught by Guidash (Specific implementation methods).
Regarding claim 15, Li discloses all the elements of claim 14 as above and further output of the NAND gate is input to an adder tree (Fig. 4 and pg:7 describes that CIM circuit 52 includes a multiplication circuit 130 and an adder circuit 140).
Allowable Subject Matter
Claims 4-7 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 9/30/2026
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