DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Information Disclosure Statement
Per MPEP 609.02(I) and (II)(A)(2), the examiner of a continuing application will consider information which has been considered by the Office in the parent application. Therefore, information considered in parent applications 17/703,479 (Pat. No. 11,829,321) and 18/376,494 (Pat. No. 12,287,756) has been considered during examination of the instant application. However, if applicant wants said considered information to be printed on any patent resulting from the instant application, applicant must ensure that said information appears on either an IDS or an 892 in the instant application.
Drawings
Figures 7A-E and 11B are objected to for failing to comply with 37 CFR 1.84(i), which requires that words appear in a horizontal, left-to-right fashion when the page is either upright or turned so that the top becomes the right side. Note, from 37 CFR 1.84(f), that the top of the sheet is regarded as one of the shorter sides. For Fig. 11B, the text “C+D” needs to be rotated 180 degrees. For Figs. 7A-E, the text “Space (j dimension)” needs to be rotated 180 degrees.
Figures 1-3 and 6-13 are objected for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(l), which requires the drawings be in black, and that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. When zooming into the images, pixelation of the lines, numbers, and/or characters can be seen, which is a sign that these drawings were drawn in a color other than black or were expanded past their native resolution size.
Figures 1 and 3-5 are further objected to for failing to comply with 37 CFR 1.84(m), which indicates that the use of shading is encouraged if it aids in understanding the invention and if it does not reduce legibility. However, the shading used does not aid in understanding the invention and/or affect the legibility of the drawings. For example, in Fig. 1, the shading used in 110 does not aid in understanding the invention and does not have a practical use. Applicant is advised to remove these shadings.
The drawings are further objected to for failing to comply with 37 CFR 1.84(p)(3), which requires that numbers, letters, and reference characters must measure at least .32 cm. (1/8 inch) in height. Examiner believes many of the numbers, letters, and reference characters in the drawings do not meet this requirement, although Examiner has not measured every number, letter, and reference character.
Figures 1, 3, 6A-C, and 8-13 are further objected to for failing to comply with 37 CFR 1.84(p)(3), which requires that numbers, letters, and reference characters are not to be placed upon hatched or shaded surfaces.
The drawings are further objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: 200.
Figures 4-5 are objected for failing to comply with 37 CFR 1.84(q), which requires for reference characters without lead lines to be underlined to make it clear that a lead line has not been left out by mistake. Reference characters missing lead lines or need to be underlined are:
Fig. 4: 400, 401, 405, 410, 415, 420, 425, 430.
Fig. 5: 401, 513, 514, 516, 517, 518, 519, 521, 523, 524, 526, 560.
The drawings are further objected to because of the following informalities:
Fig. 5: Delete the shading under 500, 505, 512, and 530, as the shading could be mis-interpreted as an underline. An underline can only be used for reference characters with no lead line (37 CFR 1.84(q)).
Figs. 7B, 7D, and 7E: Each of the figures include text such as “in blue” or “in green or blue”, but the figures shown do not include color, only black and white. Applicant is advised to address this issue.
Fig. 8: The plurality of S’s at the bottom-half of the figure are crossed out with strike marks. Examiner does not see the significance of crossing out the letters and the specification does not provide details as to why the letters are crossed out. Confirmation of the use of strike marks is requested.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The disclosure is objected to because of the following informalities:
Applicant should insert the patent number of Patent Application No. 18/376,494 in paragraph [0001] since it has been granted.
[0011]: line 5, delete “arithmetic logic units” and the parenthesis surrounding “ALUs” since the abbreviation was previously established in [0003].
[0020]: line 5, delete “arithmetic logic units” and the parenthesis surrounding “ALUs” since the abbreviation was previously established in [0025].
[0040]: second-to-last line, add a space between “-“ and “1” to be consistent with the formatting of the equation.
[0056]: line 1, “power source 1030” is an error and should be changed to “power source 430”.
[0079-0080]: The paragraphs indicate “blue array cycle”, “green array cycle”, “blue (second) instruction”, and “green (first) instruction”. However, the drawings do not include any color. Applicant is advised to amend the elements noted to match the shading of the figures.
[0083]: line 3, add a space between the comma and “rotate”.
[0083]: line 3: Examiner believes “concat” is a spelling error and should be corrected to “concatenate”
Appropriate correction is required.
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112 below.
Claim Objections
Claims 4, 7, and 13 are objected to because of the following informalities:
Claim 4, line 1: Change the phrase “at least one of the first or second ALUs” to “at least the first ALU or the second ALU” to improve clarity/consistency.
Claim 7, line 1: Replace “arithmetic logic unit” to ALU to maintain consistency of using the abbreviation previously established.
Claim 13, line 3: An “and” is missing after the semicolon and should be added.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“sequencer configured to control instructions sent to the one or more processors and the plurality of cells” in claim 16 invoke 112(f). However, Examiner could not find the corresponding structure in the specification or drawings. Examiner finds the support to perform the recited function (see [0040]), but could not find any corresponding structure for the element. For the sake of examination, Examiner will interpret the element to be any circuit that performs the recited function. Examiner recommends that Applicant amends the element to recite “circuit” after “sequencer” to avoid having the limitation be interpreted under 112(f) (see MPEP 2181(I)(A)).
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
Claim 16 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 16, as described in the 112(b) rejection below, the disclosure does not provide adequate structure to perform the claimed function of controlling instructions sent to the one or more processors and the plurality of cells. The application does not demonstrate that the applicant has made an invention that achieves the claimed functions because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-11, 16, and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "output from the one or more ALUs" in line 2. There is insufficient antecedent basis for this limitation in the claim. There was no prior instance of “one or more ALUs” within the claim or the claim it depends on. Only two ALUs (the first ALU and the second ALU) in each cell were established in claim 8. For the sake of examination, Examiner will interpret this claim to be “[t]he systolic array of claim 8, wherein each cell further comprises a register file configured to receive, as input, output from the first ALU or the second ALU”. This interpretation also addresses the antecedent basis issue “the register file in each cell” in claim 11, line 1.
Claim 11 is rejected for inheriting the rejection of claim 10.
Claim 11 recites the limitation "an output of the register file in each cell" in line 1. There is insufficient antecedent basis for this limitation in the claim. There was no prior instance of “register file in each cell” within the claim or the claim it depends on. Only a “register file” was established in claim 10, but the “register file” was not established being in each of the cells. For the sake of examination, Examiner will interpret that each of the cells comprise a register file.
Claim 11 recites “the crossbar switch in the same cell” in line 2. There is insufficient antecedent basis for this limitation in the claim. There was no prior instance of “a crossbar switch in the same cell” within the claim or the claim it depends on. Only a “crossbar switch” was established in claim 8, but the “crossbar switch” was not established being in each of the cells. For the sake of examination, Examiner will interpret that each of the cells comprise a crossbar switch.
Claim 18 recites the limitation "an output of the register file in each cell" in line 2. There is insufficient antecedent basis for this limitation in the claim. There was no prior instance of “a register file in each cell” within the claim or the claim it depends on. Only a “register file” was established in claim 18, but the “register file” was not established being in each of the cells. For the sake of examination, Examiner will interpret that each of the cells comprise a register file.
Claim 18 recites “the crossbar switch in the same cell” in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. There was no prior instance of “a crossbar switch in the same cell” within the claim or the claim it depends on. Only a “crossbar switch” was established in claim 13, but the “crossbar switch” was not established being in each of the cells. For the sake of examination, Examiner will interpret that each of the cells comprise a crossbar switch.
Regarding claim 16, the claim limitation “sequencer” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification is devoid of adequate structure to perform the claimed function. In particular, the specification states that the claimed function of controlling instructions sent to the one or more processors and the plurality of cells is done by a “sequencer.” The use of the term “sequencer” is not adequate structure for performing the claimed functions mentioned previously because it does not describe a particular structure for performing the function. The specification does not provide sufficient details such that one of ordinary skill in the art would understand which structure would perform the claimed function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1, 1, 1, 3, 1, 5, and 6 of U.S. Patent No. 11,829,321 (Hereinafter, Patent ‘321).
Regarding claim 1, Patent ‘321 teaches a systolic cell, comprising:
a first arithmetic logic unit (ALU) coupled to a first output of a crossbar switch (see claim 1); and
a second ALU coupled to a second output of the crossbar switch (see claim 1);
wherein the systolic cell is configured to provide signals from the first ALU and the second ALU as inputs to the crossbar switch (Claim 1: The output bits (i.e., signals) of the first ALU and the second ALU are inputs to the register file. The register file then provides an output signal based on the input signals of the ALUs as an input to the crossbar switch. Therefore, the first ALU and the second ALU provides signals as inputs to the crossbar switch through the register file. Note that Patent ‘321 only has support for the register file receiving the outputs of the ALUs and the disclosure does not indicate that the register file receives inputs from anything other than the outputs of the ALUs (see Figs. 1-2, Col. 3, lines 18-32, and Col. 4, lines 36-47). Therefore, the output of the register file must comprise of the bits/signals of the ALUs (see MPEP 804(II)(B)(1), paragraphs 2-3 and 5)).
Regarding claim 2, Patent ‘321 teaches the systolic cell of claim 1, further comprising a register file configured to receive, as inputs, output from the first ALU and the second ALU (see claim 1).
Regarding claim 3, Patent ‘321 teaches the systolic cell of claim 2, wherein an output of the register file is provided to an input of the crossbar switch (see claim 1).
Regarding claim 4, Patent ‘321 teaches the systolic cell of claim 1, wherein at least one of the first or second ALUs comprises a multiplier (see claim 3).
Regarding claim 5, Patent ‘321 teaches the systolic cell of claim 1, further comprising the crossbar switch (see claim 1).
Regarding claim 6, Patent ‘321 teaches the systolic cell of claim 5, wherein the crossbar switch is an NxN crossbar switch, and is configured to:
receive a first set of inputs from a register file, and a second set of inputs from adjacent cells, and provide a first set of outputs to the first ALU and a second set of outputs to the second ALU (Claim 5: The crossbar switch is a 4x4 crossbar switch (i.e., a NxN crossbar switch) that receives inputs from the register file and inputs from adjacent cells. The crossbar switch then provides outputs to the first ALU and second ALU).
Regarding claim 7, Patent ‘321 teaches the systolic cell of claim 1, further comprising a third arithmetic logic unit coupled between the crossbar switch and a register file (see claim 6).
Claims 8-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 7, 7, 7, 7, 12, 13, 14, 15, 16, 17,13, 19, and 19 of U.S. Patent ‘321 in view of Bedau (US 20210406009 A1)
Regarding claim 8, Patent ‘321 teaches a systolic array, comprising:
a plurality of cells arranged such that a first output of a first cell is provided as input to a second adjacent cell, and a second output of the first cell is provided as input to a third adjacent cell (see claim 7), wherein each cell comprises:
a first arithmetic logic unit (ALU) coupled to a first output of a crossbar switch; and
a second ALU coupled to a second output of the crossbar switch (Claim 7: A plurality of ALUs encompasses two ALUs, where each ALU is coupled to the outputs of the crossbar switch);
wherein the cell is configured to provide signals from the first ALU and the second ALU as inputs to the crossbar switch (Claim 7: The output bits (i.e., signals) of the first ALU and the second ALU are inputs to the register file. The register file then provides an output signal based on the input signals of the ALUs as an input to the crossbar switch. Therefore, the first ALU and the second ALU provides signals as inputs to the crossbar switch through the register file. Note that Patent ‘321 only has support for the register file receiving the outputs of the ALUs and the disclosure does not indicate that the register file receives inputs from anything other than the outputs of the ALUs (see Figs. 1-2, Col. 3, lines 18-32, and Col. 4, lines 36-47). Therefore, the output of the register file must comprise of the bits/signals of the ALUs (see MPEP 804(II)(B)(1), paragraphs 2-3 and 5)).
Patent ‘321 does not teach that the systolic array is programmed to execute loop-blocks, each loop-block being a sequence of instructions that is executed one time each in all of the cells of the systolic array.
Note that an instruction intended to be processed by a systolic array would comprise of at least one operand. The at least one operand would be processed by the systolic array with the corresponding operation to be performed indicated by the instruction and then propagate through the systolic array. Therefore, each systolic cell would only process the instruction once.
Bedau teaches to execute a sequence of instructions (i.e., a loop-block) using a systolic array ([0033]: A sequence of microcode instructions is executed by a processing devices such as a systolic array).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Patent ‘321 with the teachings of Bedau to have used a systolic array to execute a sequence of instructions. One of ordinary skill may prefer using a systolic array to perform a sequence of instructions over using a standard processor execution unit when the sequence of instructions may comprise of vector/matrix operands to be used in matrix operations, in which the systolic array exceeds in performance over the latter.
Regarding claim 9, Patent ‘321, in view of Bedau, teaches the systolic array of claim 8, further comprising the crossbar switch (Patent ‘321, see claim 7).
Regarding claim 10, Patent ‘321, in view of Bedau, teaches the systolic array of claim 8, further comprising a register file configured to receive, as input, output from the one or more ALUs (Patent ‘321, see claim 7).
Regarding claim 11, Patent ‘321 teaches the systolic array of claim 10, wherein an output of the register file in each cell is provided to an input of the crossbar switch in the same cell (Patent ‘321, see claim 7).
Regarding claim 12, Patent ‘321, in view of Bedau, teaches the systolic array of claim 8, wherein the systolic array is configured to receive two source vectors and produce at least one result vector per cycle (Patent ‘321, see claim 12).
Regarding claim 13, Patent ‘321 teaches the computing system, comprising:
one or more memories (see claim 13);
one or more processors in communication with the one or more memories (see claim 13);
a systolic array comprising a plurality of cells in communication with the one or more processors, the plurality of cells arranged such that a first output of a first cell is provided as input to a second adjacent cell, and a second output of the first cell is provided as input to a third adjacent cell (see claim 14), wherein each cell comprises:
a first arithmetic logic unit (ALU) coupled to a first output of a crossbar switch; and
a second ALU coupled to a second output of the crossbar switch (Claim 13: A plurality of ALUs encompasses two ALUs, where each ALU is coupled to the outputs of the crossbar switch);
wherein the cell is configured to provide signals from the first ALU and the second ALU as inputs to the crossbar switch (Claim 13: The output bits (i.e., signals) of the first ALU and the second ALU are inputs to the register file. The register file then provides an output signal based on the input signals of the ALUs as an input to the crossbar switch. Therefore, the first ALU and the second ALU provides signals as inputs to the crossbar switch through the register file. Note that Patent ‘321 only has support for the register file receiving the outputs of the ALUs and the disclosure does not indicate that the register file receives inputs from anything other than the outputs of the ALUs (see Figs. 1-2, Col. 3, lines 18-32, and Col. 4, lines 36-47). Therefore, the output of the register file must comprise of the bits/signals of the ALUs (see MPEP 804(II)(B)(1), paragraphs 2-3 and 5)).
Patent ‘321 does not teach that the systolic array is programmed to execute loop-blocks, each loop-block being a sequence of instructions that is executed one time each in all of the cells of the systolic array.
Note that an instruction intended to be processed by a systolic array would comprise of at least one operand. The at least one operand would be processed by the systolic array with the corresponding operation to be performed indicated by the instruction and then propagate through the systolic array. Therefore, each systolic cell would only process the instruction once.
Bedau teaches to execute a sequence of instructions (i.e., a loop-block) using a systolic array ([0033]: A sequence of microcode instructions is executed by a processing devices such as a systolic array).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Patent ‘321 with the teachings of Bedau to have used a systolic array to execute a sequence of instructions. One of ordinary skill may prefer using a systolic array to perform a sequence of instructions over using a standard processor execution unit when the sequence of instructions may comprise of vector/matrix operands to be used in matrix operations, in which the systolic array exceeds in performance over the latter.
Regarding claim 14, Patent ‘321, in view of Bedau, teaches the computing system of claim 13, wherein the one or more processors comprise at least one of a scalar core or a vector processing unit (Patent ‘321, see claim 14).
Regarding claim 15, Patent ‘321, in view of Bedau, teaches the computing system of claim 13, wherein the one or more memories include a vector data cache (Patent ‘321, see claim 15).
Regarding claim 16, Patent ‘321, in view of Bedau, teaches the computing system of claim 13, further comprising a sequencer configured to control instructions sent to the one or more processors and the plurality of cells (Patent ‘321, see claim 16).
Regarding claim 17, Patent ‘321, in view of Bedau, teaches the computing system of claim 13, wherein the systolic array is configured to receive a set of source vectors and produce at least one result vector per cycle (Patent ‘321, see claim 17).
Regarding claim 18, Patent ‘321, in view of Bedau, teaches the computing system of claim 13, wherein the systolic array further includes a register file, and wherein an output of the register file in each cell is provided to an input of the crossbar switch in the same cell (Patent ‘321, see claim 13).
Regarding claim 19, Patent ‘321, in view of Bedau, teaches the computing system of claim 13, further comprising the crossbar switch in each cell, wherein the crossbar switch in each cell is configured to receive as input, output from one or more adjacent cells (Patent ‘321, see claim 19).
Regarding claim 20, Patent ‘321, in view of Bedau, teaches the computing system of claim 19, wherein the crossbar switch is an NxN crossbar switch (Patent ‘321, claim 19: The crossbar switch receives an output from the register file and receives an output from one or more adjacent cells, making up two inputs. A plurality of ALUs encompasses 2 ALUs. The crossbar switch sends an output to the first ALU and second ALU, making up two outputs. Therefore, the crossbar switch is a 2x2 (two inputs and two outputs) crossbar switch), and is configured to:
receive a first set of inputs from a register file (Patent ‘321, claim 19: The crossbar switch receives an output from the register file. The output from the crossbar switch as the first set of inputs), and a second set of inputs from adjacent cells (Patent ‘321, claim 19: The crossbar switch receives an output from the adjacent cell. The output as the second set of inputs), and
provide a first set of outputs to the first ALU and a second set of outputs to the second ALU (Patent ‘321, claim 19: The crossbar switch of the current cell sends outputs to a first ALU and a second ALU. The first output to the first ALU is the first set of outputs. The second output to the second ALU is the second set of outputs).
Claims 1-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 1, 1, 4, 1, 3, and 1 of U.S. Patent No. 12,287,756 (Hereinafter, Patent ‘756).
Regarding claim 1, Patent ‘756 teaches a systolic cell (Claim 1: The processor cell as the systolic cell), comprising:
a first arithmetic logic unit (ALU) coupled to a first output of a crossbar switch (Claim 1: The first floating point logic unit is a type of ALU); and
a second ALU coupled to a second output of the crossbar switch (Claim 1: The second floating point logic unit is a type of ALU);
wherein the systolic cell is configured to provide signals from the first ALU and the second ALU as inputs to the crossbar switch (Claim 1: The outputs of the FPLUs are inputs to the register file. Then, the output of the register file is the input of the crossbar switch. Therefore, the output of the FPLUs are eventually inputs to the crossbar switch. Note that Patent ‘756 only has support for the register file receiving the outputs of the FPLUs and the output of the register file is only used as an input to the crossbar switch. The disclosure does not indicate that the register file receives inputs from anything other than the outputs of the FPLUs (see Figs. 1-2, Col. 3, lines 25-40, and Col. 4, lines 45-56) or that the output of the register file is an input to anything other than the crossbar switch (see Figs. 1-2, Col. 3, lines 25-40). Therefore, the output of the register file must comprise of the bits/signals of the FPLUs and provide those bits/signals through the register file as input to the crossbar switch (see MPEP 804(II)(B)(1), paragraphs 2-3 and 5)).
Regarding claim 2, Patent ‘756 teaches the systolic cell of claim 1, further comprising a register file configured to receive, as inputs, output from the first ALU and the second ALU (see claim 1).
Regarding claim 3, Patent ‘756 teaches the systolic cell of claim 2, wherein an output of the register file is provided to an input of the crossbar switch (see claim 1).
Regarding claim 4, Patent ‘756 teaches the systolic cell of claim 1, wherein at least one of the first or second ALUs comprises a multiplier (see claim 4).
Regarding claim 5, Patent ‘756 teaches the systolic cell of claim 1, further comprising the crossbar switch (see claim 1).
Regarding claim 6, Patent ‘756 teaches the systolic cell of claim 5, wherein the crossbar switch is an NxN crossbar switch (Claim 3: The crossbar switch receives one or more outputs from the register file (which encompasses one input) and receives an output from one or more additional processing cells (which encompasses one output from one additional processing cell), making up two inputs. The crossbar switch sends an output to the first FPLU and second FPLU, making up two outputs. Therefore, the crossbar switch is a 2x2 (two inputs and two outputs) crossbar switch), and is configured to:
receive a first set of inputs from a register file (Claim 3: The crossbar switch receives one or more outputs from the register file. The one or more outputs from the crossbar switch as the first set of inputs), and a second set of inputs from adjacent cells (Claim 3: The crossbar switch receives an output from the one or more additional processing cells. Since the crossbar switch receives an output from the additional processing cell, the additional processing cell must be adjacent to the current processing cell), and
provide a first set of outputs to the first ALU and a second set of outputs to the second ALU (Claim 3: The crossbar switch of the processing cell sends outputs to the first FPLU and second FPLU. The first output to the first FPLU is the first set of outputs. The second output to the second FPLU is the second set of outputs).
Regarding claim 7, Patent ‘756 teaches the systolic cell of claim 1 (see claim 1).
Patent ‘756 does not teach that the systolic cell comprises of a third arithmetic logic unit coupled between the crossbar switch and a register file.
However, it would have been obvious to one of ordinary skill in the art to have modified the teachings of Patent ‘756 to add a third ALU located between the register file and the ALU. By adding more ALUs in a system, more data can be processed or more complex operations can be performed, which one of ordinary skill may appreciate. Furthermore, duplication of parts, i.e., adding a third ALU, is considered to be a routine expedient, not a patentable distinction (MPEP 2144.04(VI)(B)).
Claims 8-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 7, 7, 7, 7, 13, 14, 15, 16, 17, 18, 14, 20, and 20 of U.S. Patent ‘756 in view of Bedau (US 20210406009 A1).
Regarding claim 8, Patent ‘756 teaches a systolic array (Claim 7: The processor array as the systolic array), comprising:
a plurality of cells arranged such that a first output of a first cell is provided as input to a second adjacent cell, and a second output of the first cell is provided as input to a third adjacent cell (Claim 7: Processor cell being the type of cell used. Given that the outputs of a first cell are inputs to a second cell and third cell, the second cell and third cell must be adjacent to the first cell to receive its output), wherein each cell comprises:
a first arithmetic logic unit (ALU) coupled to a first output of a crossbar switch; and
a second ALU coupled to a second output of the crossbar switch (Claim 7: The floating point logic unit is a type of ALU. The plurality of FPLUs indicate at least two or more FPLUs);
wherein the cell is configured to provide signals from the first ALU and the second ALU as inputs to the crossbar switch (Claim 7: The outputs of the plurality of FPLUs are inputs to the register file. Then, the output of the register file is the input of the crossbar switch. Therefore, the output of the plurality of FPLUs are eventually inputs to the crossbar switch. Note that Patent ‘756 only has support for the register file receiving the outputs of the FPLUs and the output of the register file is only used as an input to the crossbar switch. The disclosure does not indicate that the register file receives inputs from anything other than the outputs of the FPLUs (see Figs. 1-2, Col. 3, lines 25-40, and Col. 4, lines 45-56) or that the output of the register file is an input to anything other than the crossbar switch (see Figs. 1-2, Col. 3, lines 25-40). Therefore, the output of the register file must comprise of the bits/signals of the FPLUs and provide those bits/signals through the register file as input to the crossbar switch (see MPEP 804(II)(B)(1), paragraphs 2-3 and 5)).
Patent ‘756 does not teach that the systolic array is programmed to execute loop-blocks, each loop-block being a sequence of instructions that is executed one time each in all of the cells of the systolic array.
Note that an instruction intended to be processed by a systolic array would comprise of at least one operand. The at least one operand would be processed by the systolic array with the corresponding operation to be performed indicated by the instruction and then propagate through the systolic array. Therefore, each systolic cell would only process the instruction once.
Bedau teaches to execute a sequence of instructions (i.e., a loop-block) using a systolic array ([0033]: A sequence of microcode instructions is executed by a processing devices such as a systolic array).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Patent ‘756 with the teachings of Bedau to have used a systolic array to execute a sequence of instructions. One of ordinary skill may prefer using a systolic array to perform a sequence of instructions over using a standard processor execution unit when the sequence of instructions may comprise of vector/matrix operands to be used in matrix operations, in which the systolic array exceeds in performance over the latter.
Regarding claim 9, Patent ‘756, in view of Bedau, teaches the systolic array of claim 8, further comprising the crossbar switch (Patent ‘756, see claim 7).
Regarding claim 10, Patent ‘756, in view of Bedau, teaches the systolic array of claim 8, further comprising a register file configured to receive, as input, output from the one or more ALUs (Patent ‘756, see claim 7).
Regarding claim 11, Patent ‘756, in view of Bedau, teaches the systolic array of claim 10, wherein an output of the register file in each cell is provided to an input of the crossbar switch in the same cell (Patent ‘756, see claim 7).
Regarding claim 12, Patent ‘756, in view of Bedau, teaches the systolic array of claim 8, wherein the systolic array is configured to receive two source vectors and produce at least one result vector per cycle (Patent ‘756, see claim 13).
Regarding claim 13, Patent ‘756 teaches a computing system (see claim 14), comprising:
one or more memories (see claim 14);
one or more processors in communication with the one or more memories (see claim 14);
a systolic array comprising a plurality of cells in communication with the one or more processors (Claim 14: The plurality of cells make up the systolic array), the plurality of cells arranged such that a first output of a first cell is provided as input to a second adjacent cell, and a second output of the first cell is provided as input to a third adjacent cell (Claim 14: Given that the outputs of a first cell are inputs to a second cell and third cell, the second cell and third cell must be adjacent to the first cell to receive its output), wherein each cell comprises:
a first arithmetic logic unit (ALU) coupled to a first output of a crossbar switch; and
a second ALU coupled to a second output of the crossbar switch; wherein the cell is configured to provide signals from the first ALU and the second ALU as inputs to the crossbar switch (Claim 14: The floating point logic unit is a type of ALU. The plurality of FPLUs indicate at least two or more FPLUs. Note that Patent ‘756 only has support for the register file receiving the outputs of the FPLUs and the output of the register file is only used as an input to the crossbar switch. The disclosure does not indicate that the register file receives inputs from anything other than the outputs of the FPLUs (see Figs. 1-2, Col. 3, lines 25-40, and Col. 4, lines 45-56) or that the output of the register file is an input to anything other than the crossbar switch (see Figs. 1-2, Col. 3, lines 25-40). Therefore, the output of the register file must comprise of the bits/signals of the FPLUs and provide those bits/signals through the register file as input to the crossbar switch (see MPEP 804(II)(B)(1), paragraphs 2-3 and 5)).
Patent ‘756 does not teach that the systolic array is programmed to execute loop-blocks, each loop-block being a sequence of instructions that is executed one time each in all of the cells of the systolic array.
Note that an instruction intended to be processed by a systolic array would comprise of at least one operand. The at least one operand would be processed by the systolic array with the corresponding operation to be performed indicated by the instruction and then propagate through the systolic array. Therefore, each systolic cell would only process the instruction once.
Bedau teaches to execute a sequence of instructions (i.e., a loop-block) using a systolic array ([0033]: A sequence of microcode instructions is executed by a processing devices such as a systolic array).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Patent ‘756 with the teachings of Bedau to have used a systolic array to execute a sequence of instructions. One of ordinary skill may prefer using a systolic array to perform a sequence of instructions over using a standard processor execution unit when the sequence of instructions may comprise of vector/matrix operands to be used in matrix operations, in which the systolic array exceeds in performance over the latter.
Regarding claim 14, Patent ‘756, in view of Bedau, teaches the computing system of claim 13, wherein the one or more processors comprise at least one of a scalar core or a vector processing unit (Patent ‘756, see claim 15).
Regarding claim 15, Patent ‘756, in view of Bedau, teaches the computing system of claim 13, wherein the one or more memories include a vector data cache (Patent ‘756, see claim 16).
Regarding claim 16, Patent ‘756, in view of Bedau, teaches the computing system of claim 13, further comprising a sequencer configured to control instructions sent to the one or more processors and the plurality of cells (Patent ‘756, see claim 17).
Regarding claim 17, Patent ‘756, in view of Bedau, teaches the computing system of claim 13, wherein the systolic array is configured to receive a set of source vectors and produce at least one result vector per cycle (Patent ‘756, see claim 18).
Regarding claim 18, Patent ‘756, in view of Bedau, teaches the computing system of claim 13, wherein the systolic array further includes a register file, and wherein an output of the register file in each cell is provided to an input of the crossbar switch in the same cell (Patent ‘756, see claim 14).
Regarding claim 19, Patent ‘756, in view of Bedau, teaches the computing system of claim 13, further comprising the crossbar switch in each cell, wherein the crossbar switch in each cell is configured to receive as input, output from one or more adjacent cells (Patent ‘756, Claim 20: Given that one of the inputs of a first cell receives an output of a fourth cell, the fourth cell must be adjacent to the first cell so that the first cell receives the output).
Regarding claim 20, Patent ‘756, in view of Bedau, teaches the computing system of claim 19, wherein the crossbar switch is an NxN crossbar switch (Patent ‘756, claim 20: The crossbar switch receives one or more outputs from the register file (which encompasses one input) and receives an output from a fourth cell, making up two inputs. A plurality of FPLUs encompasses 2 FPLUs. The crossbar switch sends an output to the first FPLU and second FPLU, making up two outputs. Therefore, the crossbar switch is a 2x2 (two inputs and two outputs) crossbar switch), and is configured to:
receive a first set of inputs from a register file (Patent ‘756, claim 20: The crossbar switch receives one or more outputs from the register file. The one or more outputs from the crossbar switch as the first set of inputs), and a second set of inputs from adjacent cells (Patent ‘756, claim 20: The crossbar switch receives an output from the fourth cell. Since the crossbar switch receives an output from the fourth cell, the fourth cell must be adjacent to the current cell), and
provide a first set of outputs to the first ALU and a second set of outputs to the second ALU (Patent ‘756, claim 20: The crossbar switch of the current cell sends outputs to the first FPLU and second FPLU. The first output to the first FPLU is the first set of outputs. The second output to the second FPLU is the second set of outputs).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Luzhou et al. (“Domain-Specific Language and Compiler for Stencil Computation on FPGA-based Systolic Computational-Memory Array”) in view of Ahmed (US 20210406010 A1, see IDS filed March 31, 2025).
Regarding claim 1, Luzhou teaches a systolic cell (Page 4, Fig. 3: the processing element is part of a systolic array. Therefore, it’s a systolic cell), comprising:
an ALU coupled to a first output of a crossbar switch (Page 4, Figs. 3-4: An output of the switch (which must be some type of crossbar switch to direct data between units/PEs) is an input of the Comp unit. The comp unit is a floating-point multiply accumulate unit, which is a type of ALU);
wherein the systolic cell is configured to provide signals from the comp unit as input to the crossbar switch (Page 4, Fig. 3: The output of the comp unit is used as the input of the switch).
Luzhou does not teach that the systolic cell comprises of a second ALU coupled to a second output of the crossbar switch, wherein the systolic cell is configured to provide signals from the first ALU and the second ALU as inputs to the crossbar switch.
Ahmed teaches a processing element of a systolic array comprising of a first ALU coupled to an output of MUXs and a second ALU coupled to an output of MUXs (Fig. 4, [0061-0062]: ALU 42 as the first ALU. MAC 44, which is a specialized arithmetic logic unit, as the second ALU. The input to the units are based on the first and second MUX 451-452), and provides the results of both ALUs to be sent to a third MUX to provide a final result (Fig. 4: MUX 453)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Luzhou with the teachings of Ahmed to have multiple ALUs be used within the systolic cell and have one of the results routed back to the switch of the cell. One of ordinary skill would recognize that by having multiple ALUs, one can be specialized to support specific operations (like the MAC unit) while the other performs general arithmetic operations, which would reduce latency compared to having both a MAC and ALU in one unit. Furthermore, more types of operations can be performed as a result.
Regarding claim 2, Luzhou, in view of Ahmed, teaches the systolic cell of claim 1, further comprising a local memory configured to receive, as inputs, output from the from the first ALU and the second ALU (Luzhou, Page 4, Fig. 3: In the current combination, the output of the MUX between the ALU and the MAC can be seen as the mix of inputs between the two units to the local memory. Therefore, the ALU and the MAC provides outputs as inputs to the local memory).
Luzhou, in view of Ahmed, does not teach that the local memory is a register file.
Ahmed also teaches a register file that receives the output of the ALUs (Fig. 4: Register file 42). Note that a register file serves the same purpose as a local memory in the sense that both memories allow data to be stored and fetched for processing. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have substituted the local memory of Luzhou with the register file of Ahmed (See KSR Int'l Co. V. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007)).
Regarding claim 3, Luzhou, in view of Ahmed, teaches the systolic cell of claim 1, wherein an output of the register file is provided to an input of the crossbar switch (Luzhou, Page 4, Fig. 3; Ahmed, Fig. 4: In the current combination, the output of the register file would be input for the crossbar switch).
Regarding claim 4, Luzhou, in view of Ahmed, teach the systolic cell of claim 1, wherein at least one of the first or second ALUs comprises a multiplier (Luzhou, Page 4, Figs. 3-4; Ahmed, Fig. 4, [0061-0062]: In the current combination, the first ALU is a MAC unit, which would comprise a multiplier as part of the MAC).
Regarding claim 5, Luzhou, in view of Ahmed, teaches the systolic cell of claim 1, further comprising the crossbar switch (Luzhou, Page 4, Fig. 3: See claim 1 mapping. In the current combination, the cell comprises of a crossbar switch).
Regarding claim 6, Luzhou, in view of Ahmed, teaches the systolic cell of claim 5, wherein the crossbar switch is an NxN crossbar switch (Luzhou, Page 4, Fig. 3: The crossbar switch is a 4 external input and 4 external output crossbar switch (which does not include the internal input and output signals) to communicate between other adjacent cells. Therefore, the crossbar switch is a 4x4 crossbar switch (i.e., NxN crossbar switch)), and is configured to:
receive a first set of inputs from a local memory (Luzhou, Page 4, Fig. 3: The local memory sends a set of inputs to the crossbar switch), and a second set of inputs from adjacent cells (Luzhou, Page 4, Fig. 3: The crossbar switch also receives a set of inputs from adjacent cells), and
provide a first set of outputs to the first ALU and a second set of outputs to the second ALU (Luzhou, Page 4, Fig. 3; Ahmed, Fig. 4: In the current combination, The first signal and the second signal to the ALUs are the first set and second set of outputs. The first signal is input to both ALUs, which would include the generic MAC. The second signal is input to both ALUs, which would include the ALU. Therefore, the crossbar switch provides a first set of outputs to the first ALU and a second set of outputs to the second ALU).
Luzhou, in view of Ahmed, does not teach that the local memory is a register file.
Ahmed also teaches a register file that receives an output from ALUs (Fig. 4: Register file 42). Note that a register file serves the same purpose as a local memory in the sense that both memories allow data to be stored and fetched for processing. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have substituted the local memory of Luzhou with the register file of Ahmed (See KSR Int'l Co. V. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007)).
Regarding claim 7, Luzhou, in view of Ahmed, teaches the systolic cell of claim 1.
Luzhou, in view of Ahmed, does not teach a register file in the processing element.
Ahmed also teaches a register file that receives an output from ALUs (Fig. 4: Register file 42). Note that a register file serves the same purpose as a local memory in the sense that both memories allow data to be stored and fetched for processing. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have substituted the local memory of Luzhou with the register file of Ahmed (See KSR Int'l Co. V. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007)).
Luzhou, in view of Ahmed, still does not teach to have a third arithmetic logic unit coupled between the crossbar switch and register file.
However, it would have been obvious to one of ordinary skill in the art to have modified the teachings of Luzhou, in view of Ahmed, to add a third ALU located between the register file and the ALU. By adding more ALUs in a system, more data can be processed or more complex operations can be performed, which one of ordinary skill may appreciate. Furthermore, duplication of parts, i.e., adding a third ALU, is considered to be a routine expedient, not a patentable distinction (MPEP 2144.04(VI)(B)).
Claims 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Luzhou et al. (“Domain-Specific Language and Compiler for Stencil Computation on FPGA-based Systolic Computational-Memory Array”) in view of Ahmed (US 20210406010 A1, see IDS filed March 31, 2025), and Bedau (US 20210406009 A1).
Regarding claim 8, the claim is mostly rejected for the same reasons as claim 1. Luzhou, in view of Ahmed, teaches a systolic array (Luzhou, Page 4, Fig. 3: Systolic computational-memory array), comprising:
A plurality of cells arranged such that a first output of a first cell is provided as input to a second adjacent cell, and a second output of the first cell is provided as input to a third adjacent cell (Luzhou, Page 4, Fig. 3: In the current combination, the systolic array comprises of multiple processing elements having a crossbar switch that has multiple outputs. For one processing element (i.e., a first cell) one of the outputs (i.e., a first output of the first cell) is sent as an input to a right-adjacent processing element. Another one of the outputs (i.e., a second output of the first cell) is sent as an input to a bottom-adjacent processing element. The right-adjacent processing element as the second adjacent cell and the bottom-adjacent processing element as the third adjacent cell).
Luzhou, in view of Ahmed, does not explicitly teach that the systolic array is programmed to execute loop-blocks, each loop-block being a sequence of instructions that is executed one time each in all of the cells of the systolic array.
Note that an instruction intended to be processed by a systolic array would comprise of at least one operand. The at least one operand would be processed by the systolic array with the corresponding operation to be performed indicated by the instruction and then propagate through the systolic array. Therefore, each systolic cell would only process the instruction once.
Bedau teaches to execute a sequence of instructions (i.e., a loop-block) using a systolic array ([0033]: A sequence of microcode instructions is executed by a processing devices such as a systolic array).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Luzhou, in view of Ahmed, with the teachings of Bedau to have used a systolic array to execute a sequence of instructions. One of ordinary skill may prefer using a systolic array to perform a sequence of instructions over using a standard processor execution unit when the sequence of instructions may comprise of vector/matrix operands to be used in matrix operations, in which the systolic array exceeds in performance over the latter.
Regarding claim 9, Luzhou, in view of Ahmed and Bedau, teaches the systolic array of claim 8, further comprising the crossbar switch (Luzhou, Page 4, Fig. 3: In the current combination, each processing element comprises of a crossbar switch).
Regarding claim 10, Luzhou, in view of Ahmed and Bedau, teaches the systolic array of claim 8, further comprising a local memory configured to receive, as inputs, output from the from the one or more ALUs (Luzhou, Page 4, Fig. 3: In the current combination, the output of the MUX between the ALU and the MAC can be seen as the mix of inputs between the two units to the local memory. Therefore, the ALU and the MAC provides outputs as inputs to the local memory).
Luzhou, in view of Ahmed and Bedau, does not teach that the local memory is a register file.
Ahmed also teaches a register file that receives an output from ALUs (Fig. 4: Register file 42). Note that a register file serves the same purpose as a local memory in the sense that both memories allow data to be stored and fetched for processing. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have substituted the local memory of Luzhou with the register file of Ahmed (See KSR Int'l Co. V. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007)).
Regarding claim 11, Luzhou, in view of Ahmed and Bedau, teaches the systolic array of claim 10, wherein an output of the register file in each cell is provided to an input of the crossbar switch in the same cell (Luzhou, Page 4, Fig. 3; Ahmed, Fig. 4: In the current combination, for each processing element of the systolic array, the output of the register file would be input for the crossbar switch).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Luzhou et al. (“Domain-Specific Language and Compiler for Stencil Computation on FPGA-based Systolic Computational-Memory Array”) in view of Ahmed (US 20210406010 A1, see IDS filed March 31, 2025), Bedau (US 20210406009 A1), and O et al. (US 20220350861 A1).
Regarding claim 12, Luzhou, in view of Ahmed and Bedau, teaches the systolic array of claim 8.
Luzhou, in view of Ahmed and Bedau, does not explicitly teach that the systolic array is configured to receive two source vectors and produce at least one result vector per cycle.
O teaches a systolic array that is configured to receive two source vectors and produce at least one result vector per cycle (Figs. 4 and 5A-D: A systolic array receives a vector of inputs per cycle. For example, Fig. 4 has two input matrices where each input matrix comprises of vector T1-T7. For each cycle, Vectors T1 of both matrices enter the system and produces a first result vector (see Fig. 5, where the result vector only comprises of r111). Then, the data continues to propagate where each cycle produces one or more output vectors until the data finally outputs out at the last row of processing elements).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Luzhou, in view of Ahmed and Bedau, with the teachings of O to have the systolic array receives two source vectors and produce at least one source vector per cycle. By inputting two vector operands instead of one into the systolic array and having the systolic array produce an output vector per cycle, more operations are available to be performed, such as sparse matrix multiplication and accumulation, which may be needed by one of ordinary skill.
Claims 13-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Luzhou et al. (“Domain-Specific Language and Compiler for Stencil Computation on FPGA-based Systolic Computational-Memory Array”) in view of Ahmed (US 20210406010 A1, see IDS filed March 31, 2025), Bedau (US 20210406009 A1), and Surti et al. (US 20220129521 A1).
Regarding claim 13, the claim is mostly rejected for the same reasons as claim 8.
Luzhou, in view of Ahmed and Bedau, does not teach that the computing system comprises of:
one or more memories;
one or more processors in communication with the one or more memories; and
the systolic array in communication with the one or more processors.
Surti teaches one or more memories (Fig. 27: Cache 2727, Registers 2725, L3 Data Cache 2730, and Shared Local Memory 2732 as the memories);
one or more processors in communication with the one or more memories (Fig. 27: GPGPU processor as the one or more processors. The GPGPU comprises of Cache 2727, Registers 2725, L3 Data Cache 2730, and Shared Local Memory 2732. Therefore, the GPGPU is in communication with the memories); and
a systolic array in communication with the one or more processors (Figs. 27-28: Tensor accelerator 2723 comprises of a systolic array 2808).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Luzhou, in view of Ahmed and Bedau, with the teachings of Surti to have implemented a systolic array on a processing system comprising of processors and memories. A systolic array has the benefit of executing certain operations such as dot product operations, in which a systolic array throughputs these operations at a higher rate over compute blocks (Surti, see [0365]). Therefore, it may be beneficial for a computing system to comprise of a systolic array.
Regarding claim 14, Luzhou, in view of Ahmed, Bedau, and Surti, teaches the computing system of claim 13, wherein the one or more processors comprise at least one of a scalar core or a vector processing unit (Surti, Figs. 27-28: The GPGPU comprises a tensor accelerator 2723, which executes matrix operations. Therefore, the tensor accelerator is a vector processing unit).
Regarding claim 15, Luzhou, in view of Ahmed, Bedau, and Surti teaches the computing system of claim 13, wherein the one or more memories include a vector data cache (Surti, Fig. 27, [0358]: L3 Data Cache 2730 includes shared local memory, which can cache data accessed by the tensor accelerator 2723. As a result, L3 data cache would store matrix (vectors) operands used by the tensor accelerator. The L3 data cache as the vector data cache).
Regarding claim 16, Luzhou, in view of Ahmed, Bedau, and Surti, teaches the computing system of claim 13, further comprising a sequencer configured to control instructions sent to the one or more processors and the plurality of cells (Luzhou, Figs. 3-4; Surti, Figs. 27-28: In the current combination, a sequencer is used to indicate micro-operations to be performed by each processing element. The instructions would have to be received by the GPGPU’s instruction fetch and decode unit to process the instruction before sending it down to the systolic array).
Regarding claim 18, Luzhou, in view of Ahmed, Bedau, and Surti, teaches the computing system of claim 13, wherein the systolic array further includes a local memory, and wherein an output of the local memory in each cell is provided to an input of the crossbar switch in the same cell (Luzhou, Page 4, Fig. 3: In the current combination, each processing element comprises of a local memory, in which the output of the local memory is an input to the crossbar switch).
Luzhou, in view of Ahmed, Bedau, and Surti, does not teach that the local memory is a register file.
Ahmed also teaches a register file that receives an output from ALUs (Fig. 4: Register file 42). Note that a register file serves the same purpose as a local memory in the sense that both memories allow data to be stored and fetched for processing. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have substituted the local memory of Luzhou with the register file of Ahmed (See KSR Int'l Co. V. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007)).
Regarding claim 19, Luzhou, in view of Ahmed, Bedau, and Surti, teaches the computing system of claim 13, further comprising the crossbar switch in each cell (), wherein the crossbar switch in each cell is configured to receive as input, output from one or more adjacent cells (Luzhou, Fig. 3: Each processing element comprises of a switch, wherein each switch may receive input from a north-adjacent processing element, a west-adjacent processing element, a south-adjacent processing element, or an east-adjacent processing element).
Regarding claim 20, Luzhou, in view of Ahmed, Bedau, and Surti, teaches the computing system of claim 19, wherein the crossbar switch is an NxN crossbar switch (Luzhou, Page 4, Fig. 3: The crossbar switch is a 4 external input and 4 external output crossbar switch (which does not include the internal input and output signals) to communicate between other adjacent cells. Therefore, the crossbar switch is a 4x4 crossbar switch (i.e., NxN crossbar switch)), and is configured to:
receive a first set of inputs from a local memory (Luzhou, Page 4, Fig. 3: The local memory sends a set of inputs to the crossbar switch), and a second set of inputs from adjacent cells (Luzhou, Page 4, Fig. 3: The crossbar switch also receives a set of inputs from adjacent cells), and
provide a first set of outputs to the first ALU and a second set of outputs to the second ALU (Luzhou, Page 4, Fig. 3; Ahmed, Fig. 4: In the current combination, The first signal and the second signal to the ALUs are the first set and second set of outputs. The first signal is input to both ALUs, which would include the generic MAC. The second signal is input to both ALUs, which would include the ALU. Therefore, the crossbar switch provides a first set of outputs to the first ALU and a second set of outputs to the second ALU).
Luzhou, in view of Ahmed, Bedau, and Surti, does not teach that the local memory is a register file.
Ahmed also teaches a register file that receives an output from ALUs (Fig. 4: Register file 42). Note that a register file serves the same purpose as a local memory in the sense that both memories allow data to be stored and fetched for processing. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have substituted the local memory of Luzhou with the register file of Ahmed (See KSR Int'l Co. V. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007)).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Luzhou et al. (“Domain-Specific Language and Compiler for Stencil Computation on FPGA-based Systolic Computational-Memory Array”) in view of Ahmed (US 20210406010 A1, see IDS filed March 31, 2025), Bedau (US 20210406009 A1), Surti et al. (US 20220129521 A1), and O et al. (US 20220350861 A1).
Regarding claim 17, Luzhou, in view of Ahmed, Bedau, and Surti, teaches the computing system of claim 13.
Luzhou, in view of Ahmed, Bedau, and Surti, does not explicitly teach that the systolic array is configured to receive two source vectors and produce at least one result vector per cycle.
O teaches a systolic array that is configured to receive two source vectors and produce at least one result vector per cycle (Figs. 4 and 5A-D: A systolic array receives a vector of inputs per cycle. For example, Fig. 4 has two input matrices where each input matrix comprises of vector T1-T7. For each cycle, Vectors T1 of both matrices enter the system and produces a first result vector (see Fig. 5, where the result vector only comprises of r111). Then, the data continues to propagate where each cycle produces one or more output vectors until the data finally outputs out at the last row of processing elements).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Luzhou, in view of Ahmed, Bedau, and Surti, with the teachings of O to have the systolic array receives two source vectors and produce at least one source vector per cycle. By inputting two vector operands instead of one into the systolic array and having the systolic array produce an output vector per cycle, more operations are available to be performed, such as sparse matrix multiplication and accumulation, which may be needed by one of ordinary skill.
Claim 1 is alternatively rejected under 35 U.S.C. 103 as being unpatentable over Seki (US 20080028015 A1) in view of Olsen (US 20130311532 A1, see IDS filed March 31, 2025).
Regarding claim 1, Seki teaches a systolic cell (Figs. 1 and 5, [0089]: Processing element is used in a systolic array. Therefore. it’s a systolic cell), comprising:
an arithmetic logic unit (ALU) coupled to a first output of a crossbar switch (Fig. 5 and [0089-0092]: CORDIC calculation circuit 103 is an FPU, which is a type of ALU. The CORDIC processor receives inputs from outputs of a crossbar 102);
wherein the systolic cell is configured to provide signals from the ALU as inputs to the crossbar switch (Fig. 5 and [0089-0092]: The output of the CORDIC calculation circuit 103 is an input to a register file, where the output of the register file (comprising the calculated data from the calculation circuit) is an input of the crossbar. Therefore, the output of the calculation circuit is an input to the crossbar).
Seki does not teach that the processing element comprises of a second ALU coupled to a second output of the crossbar switch, wherein the processing element is configured to provide signals from the first ALU and the second ALU as inputs to the crossbar switch.
Note that the CORDIC calculation unit receives necessary input from the register file through the crossbar (see [0090]).
Olsen teaches a functional unit where a register file with dual input and output access to inputs and outputs of a first ALU and a second ALU (Fig. 1D: ALU 100a and ALU 100b receiving output from register file 102 and outputs from the ALUs act as inputs to the register file)
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Seki with the teachings of Olsen to have multiple ALUs be used within the systolic cell and have one of the results routed back to the switch of the cell. One of ordinary skill would recognize that by having multiple ALUs, more data can be processed, which increases the throughput of processing of data.
Claim 8 is alternatively rejected under 35 U.S.C. 103 as being unpatentable over Seki (US 20080028015 A1) in view of Olsen (US 20130311532 A1, see IDS filed March 31, 2025), and Bedau (US 20210406009 A1).
Regarding claim 8, the claim is mostly rejected for the same reasons as claim 1. Seki, in view of Olsen, teaches a systolic array (Seki, Fig. 1 and [0078]: A systolic array is shown in the figure), comprising:
A plurality of cells arranged such that a first output of a first cell is provided as input to a second adjacent cell, and a second output of the first cell is provided as input to a third adjacent cell (Seki, Figs. 1 and 5: In the current combination, the systolic array comprises of multiple processing elements having a crossbar that has multiple outputs to different processing elements. For one processing element (i.e., a first cell) one of the outputs (i.e., a first output of the first cell) is sent as an input to a top-adjacent processing element. Another one of the outputs (i.e., a second output of the first cell) is sent as an input to a bottom-adjacent processing element. The top-adjacent processing element as the second adjacent cell and the bottom-adjacent processing element as the third adjacent cell).
Seki, in view of Olsen, does not explicitly teach that the systolic array is programmed to execute loop-blocks, each loop-block being a sequence of instructions that is executed one time each in all of the cells of the systolic array.
Note that an instruction intended to be processed by a systolic array would comprise of at least one operand. The at least one operand would be processed by the systolic array with the corresponding operation to be performed indicated by the instruction and then propagate through the systolic array. Therefore, each systolic cell would only process the instruction once.
Bedau teaches to execute a sequence of instructions (i.e., a loop-block) using a systolic array ([0033]: A sequence of microcode instructions is executed by a processing devices such as a systolic array).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Seki, in view of Olsen, with the teachings of Bedau to have used a systolic array to execute a sequence of instructions. One of ordinary skill may prefer using a systolic array to perform a sequence of instructions over using a standard processor execution unit when the sequence of instructions may comprise of vector/matrix operands to be used in matrix operations, in which the systolic array exceeds in performance over the latter.
Claim 13 is alternatively rejected under 35 U.S.C. 103 as being unpatentable over Seki (US 20080028015 A1) in view of Olsen (US 20130311532 A1, see IDS filed March 31, 2025), Bedau (US 20210406009 A1), and Surti et al. (US 20220129521 A1).
Regarding claim 13, the claim is mostly rejected for the same reasons as claim 8. Seki, in view of Olsen and Bedau, also teaches a computing system comprising one or more memories (Seki, Fig. 1: Memory located at the top and bottom of the systolic array).
Seki, in view of Olsen and Bedau, does not teach that the computing system comprises of:
one or more processors in communication with the one or more memories; and
the systolic array in communication with the one or more processors.
Surti teaches one or more processors in communication with one or more memories (Fig. 27: GPGPU processor as the one or more processors. The GPGPU comprises of Cache 2727, Registers 2725, L3 Data Cache 2730, and Shared Local Memory 2732. Therefore, the GPGPU is in communication with the memories); and
a systolic array in communication with the one or more processors (Figs. 27-28: Tensor accelerator 2723 comprises of a systolic array 2808).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Seki, in view of Olsen and Bedau, with the teachings of Surti to have implemented a systolic array on a processing system comprising of processors and memories. A systolic array has the benefit of executing certain operations such as dot product operations, in which a systolic array throughputs these operations at a higher rate over compute blocks (Surti, see [0365]). Therefore, it may be beneficial for a computing system to comprise of a systolic array.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 5410723 A: Schmidt et al. teaches an array processor comprising of processing elements, where each processing element comprises of a register block (i.e., a register file), an ALU, and a MAC unit.
US 20220137927 A1: Yu et al. teaches a processing unit comprising of multiple ALUs, in which the data is transferred within the processing unit using a crossbar switch matrix.
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/E.A./Examiner, Art Unit 2183
/David J. Huisman/Primary Examiner, Art Unit 2183
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