Prosecution Insights
Last updated: October 02, 2026
Application No. 19/095,849

METHOD OF EVALUATING DISPLAY DRIVING ELEMENTS, AND DISPLAY PANEL

Final Rejection §103
Filed
Mar 31, 2025
Priority
Jul 15, 2024 — RE 10-2024-0093267
Examiner
LIN, CHUN-NAN
Art Unit
2629
Tech Center
2600 — Communications
Assignee
Samsung Display Co., Ltd.
OA Round
2 (Final)
87%
Grant Probability
Favorable
3-4
OA Rounds
5m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
585 granted / 670 resolved
+25.3% vs TC avg
Strong +16% interview lift
Without
With
+15.7%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
23 currently pending
Career history
696
Total Applications
across all art units

Statute-Specific Performance

§101
4.2%
-35.8% vs TC avg
§103
55.5%
+15.5% vs TC avg
§102
5.3%
-34.7% vs TC avg
§112
28.9%
-11.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 670 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 8, 9, 12, 13, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Koyama et al. (U.S. Patent Publication 20100163874 A1) in view of Choi et al. (U.S. Patent Publication 20220069053 A1) in view of Ko et al. (U.S. Patent Publication 20170061840 A1). Regarding claim 8, Koyama discloses “A display panel comprising: a display area (Fig 1) in which a plurality of pixel driving circuits (Fig 1, 103 [0071] [0072]) is disposed; and wherein the test element group comprises: a driving transistor (Fig. 10. Thin film transistor 353, [0085] [0088]) having terminals respectively connected to pads; (Fig. 10 801, 802, [0150] [0152]) and a first transistor (Fig. 10. Thin film transistor 355 [0154] [0155]) connected to a first end of the driving transistor and having a gate terminal (Fig. 11A, 902 Gate Terminal [0157] [0163]) Koyama does not disclose “a non-display area in which a test element group having a same structure as a structure of the pixel driving circuits is disposed, connected to an additional pad which is distinct from the pads connected to the respective terminals of the driving transistor”. Choi discloses “a non-display area in which a test element group having a same structure as a structure of the pixel driving circuits is disposed, ([0072] The test circuit portion 59 supplies a switching control signal and a test data signal, supplied from a test apparatus via a test pad portion disposed at the first non-display area IA1 or fourth non-display area IA4, to the data lines. For example, the test data signal may be a data signal for a pixel lighting test, but embodiments of the present disclosure are not limited thereto. [0073] [0209]) It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate test circuit on non-display area by Choi into device of Koyama. The suggestion/motivation would have been to provide test data signal. (Choi: [0072]) Koyama and Choi do not disclose “connected to an additional pad which is distinct from the pads connected to the respective terminals of the driving transistor”. Ko discloses “connected to an additional pad which is distinct from the pads connected to the respective terminals of the driving transistor”. (Figs. 4 - 8, [0008] [0039] – [0043] Claim does not define “connected to” is “physically connected” or “electrically connected”.) It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate pad by Ko into device of Koyama and Choi. The suggestion/motivation would have been to provide additional pad connection. (Ko: [0039]) Regarding claim 9, Koyama, Choi and Ko disclose wherein the first transistor is controlled to be turned off, (Koyama Fig 1, [0072] [0155] [0157]) and characteristics of the driving transistor are measured through pads connected to the respective terminals of the driving transistor. (Koyama Fig 1, [0071] [0072]) Regarding claim 10, Koyama, Choi and Ko disclose wherein the first transistor is controlled to be turn off by an off voltage applied through the pad connected to the gate terminal of the first transistor. (Koyama [0154] [0155] [0157]) Regarding claim 12, Koyama, Choi and Ko disclose wherein the first end of the driving transistor comprises a source terminal of the driving transistor, and the source terminal of the driving transistor is connected to a source terminal of the first transistor. (Koyama [0155] - [0158]) Regarding claim 13, Koyama, Choi and Ko disclose wherein the test element groups further comprises a second transistor, and a source terminal of the first transistor is connected to a source terminal of the driving transistor, and a source terminal of the second transistor is connected to a gate terminal of the driving transistor. (Koyama [0160] - [0163]) Regarding claim 14, Koyama, Choi and Ko disclose wherein the first transistor is turned on by a sensing signal to transmit a signal to initialize a light-emitting device, and the second transistor is turned on by a scan signal to transmit a data signal. (Koyama [0160] - [0163]) Additionally, claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Koyama et al. (U.S. Patent Publication 20100163874 A1) in view of Choi et al. (U.S. Patent Publication 20220069053 A1) in view of Jung et al. (U.S. Patent Publication 20210110745 A1). Regarding claim 8, Koyama discloses “A display panel comprising: a display area (Fig 1) in which a plurality of pixel driving circuits (Fig 1, 103 [0071] [0072]) is disposed; and wherein the test element group comprises: a driving transistor (Fig. 10. Thin film transistor 353, [0085] [0088]) having terminals respectively connected to pads; (Fig. 10 801, 802, [0150] [0152]) and a first transistor (Fig. 10. Thin film transistor 355 [0154] [0155]) connected to a first end of the driving transistor and having a gate terminal (Fig. 11A, 902 Gate Terminal [0157] [0163]) Koyama does not disclose “a non-display area in which a test element group having a same structure as a structure of the pixel driving circuits is disposed, connected to an additional pad which is distinct from the pads connected to the respective terminals of the driving transistor”. Choi discloses “a non-display area in which a test element group having a same structure as a structure of the pixel driving circuits is disposed, ([0072] The test circuit portion 59 supplies a switching control signal and a test data signal, supplied from a test apparatus via a test pad portion disposed at the first non-display area IA1 or fourth non-display area IA4, to the data lines. For example, the test data signal may be a data signal for a pixel lighting test, but embodiments of the present disclosure are not limited thereto. [0073] [0209]) It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate test circuit on non-display area by Choi into device of Koyama. The suggestion/motivation would have been to provide test data signal. (Choi: [0072]) Koyama and Choi do not disclose “connected to an additional pad which is distinct from the pads connected to the respective terminals of the driving transistor”. Jung discloses “connected to an additional pad which is distinct from the pads connected to the respective terminals of the driving transistor”. (Figs 3 - 5, [0078] [0013] – [0018] Claim does not define “connected to” means “physically directly connected” or “electrically connected”.) It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate pad by Jung into device of Koyama and Choi. The suggestion/motivation would have been to provide additional pad connection. (Jung: [0078]) Allowable Subject Matter Claims 11, 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant’s arguments with respect to claim(s) 8-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN-NAN LIN whose telephone number is (571)272-5646. The examiner can normally be reached Monday - Thursday 7:30am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin C Lee can be reached at 571-2722963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHUN-NAN LIN/Primary Examiner, Art Unit 2629
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Prosecution Timeline

Mar 31, 2025
Application Filed
May 08, 2026
Non-Final Rejection mailed — §103
Aug 07, 2026
Response Filed
Aug 26, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
87%
Grant Probability
99%
With Interview (+15.7%)
1y 11m (~5m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 670 resolved cases by this examiner. Grant probability derived from career allowance rate.

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