Prosecution Insights
Last updated: August 15, 2026
Application No. 19/096,039

Input Voltage Control for a DC/AC Power Converter

Non-Final OA §103
Filed
Mar 31, 2025
Priority
Oct 17, 2018 — provisional 62/746,698 +17 more
Examiner
LY, XUAN
Art Unit
2836
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Solaredge Technologies Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
1y 2m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
460 granted / 540 resolved
+17.2% vs TC avg
Moderate +6% lift
Without
With
+6.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
25 currently pending
Career history
564
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
69.8%
+29.8% vs TC avg
§102
22.7%
-17.3% vs TC avg
§112
5.0%
-35.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 540 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 04/24/2025 the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1, 3, and 6-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kidera et al. (US 2015/0288296) in view of Xiong (US 9,203,321). Regarding claim 1, Kidera teaches A system (see figures 1-4: shows the power supply system includes a power conversion device connected to a DC power supply 1) comprising: a power source (fig. 1@ DC power supply 1) comprising a pair of source terminals (see figure 1), the source terminals (see figure 1: inputs from DC power source 11 to DC-DC converter 12) comprising a first source terminal and a second source terminal (see figure 1); and an inverter (fig. 1@ inverter 5) comprising: a DC/AC module (5) comprising a pair of DC/AC module terminals, the DC/AC module terminals comprising a first DC/AC module terminal and a second DC/AC module terminal (see figure 1), wherein the first DC/AC module (5) terminal is connected to the first source terminal (1), and the DC/AC module (5) is configured to convert a DC voltage across the DC/AC module (5) terminals to an AC voltage (see Figs. 1-5: inverter 5 is configured to converter DC power of 1 into AC and output three phase AC), a housing (see figure 5) configured to house the DC/AC module (5); and voltage control circuitry (fig. 1@ controller 7) connected to the second source terminal (see figures 1-4), the first DC/AC module (5) terminal, and the second DC/AC module (5) terminal, wherein the voltage control circuitry (7) is configured to convert a source voltage across the source terminals to a higher voltage across the DC/AC module terminals (see par. [0039], [0046] and [0050], voltage detector 4 so as to regulate the power storage amounts of the first midpoint capacitor 31 and the second midpoint capacitor 32). However, Kidera does not explicitly teach the voltage control circuitry is configured to convert a source voltage across the source terminals to a higher voltage across the DC/AC module terminals inside the housing of the inverter. Xiong teaches the voltage control circuitry (fig. 4@ controller 106) is configured to convert a source voltage across the source terminals to a higher voltage across the DC/AC module (fig. 4@ inverter 108) terminals inside the housing (fig. 4@ housing 502) of the inverter (see figure 4). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kidera with the teachings of Xiong by having the voltage control circuitry is configured to convert a source voltage across the source terminals to a higher voltage across the DC/AC module terminals inside the housing of the inverter in order to improve inverter efficiency, enables the use of lower-voltage, safer DC sources, and guarantees stable grid-tied operations. Regarding claim 3, the combination teaches the system further comprising: a DC/DC module (fig. 3@ DC-DC converter) electrically connected to the power source (11); wherein the DC/DC module comprises a heating element (fig. 3@ resistances 21 and 23) thermally coupled to a surface of the power source (see figure 3; Kidera). Regarding claim 6, the combination teaches wherein the voltage control circuitry is configured to convert the source voltage according to a fixed ratio (see par. [0048-0049], the controller 7 thus fixes a duty ratio, at approximately 50%; Kidera). Regarding claim 7, the combination teaches wherein the fixed ratio is a one-to-one ratio, and the voltage control circuitry is configured to set the higher voltage across the DC/AC module terminals to double the source voltage of the power source (see par. [0048-0049], When the power storage amount of the midpoint capacitor 3 decreases, and the midpoint potential thus decreases, the controller 7 repeatedly switches the fifth switching element 22 on the high side between the ON state and the OFF state. Thus, the electricity is stored in the midpoint capacitor 3 so as to increase the midpoint potential of the midpoint stabilizer 2; Kidera). Regarding claim 8, the combination teaches wherein the voltage control circuitry (7) is configured to convert the source voltage to the higher voltage according to an efficiency of the DC/AC module (see par. [0048-0049]; Kidera). Regarding claim 9, the combination teaches wherein the voltage control circuitry (7) is configured to convert a lesser DC output voltage of the power source to a greater DC input voltage of the DC/AC module (see par. [0048-0049], When the power storage amount of the midpoint capacitor 3 decreases, and the midpoint potential thus decreases, the controller 7 repeatedly switches the fifth switching element 22 on the high side between the ON state and the OFF state. Thus, the electricity is stored in the midpoint capacitor 3 so as to increase the midpoint potential of the midpoint stabilizer 2; Kidera). Regarding claim 10, the combination teaches further comprising a first capacitor (capacitor 31) connected between the first DC/AC module terminal and the second source terminal, and a second capacitor (capacitor 32) connected between the second source terminal and the second DC/AC module terminal (see figures 1-3; Kidera). Regarding claim 11, the combination teaches wherein the voltage control circuitry (7) is configured to control a voltage at the second source terminal (see par. [0048-00450]; Kidera). Regarding claim 12, the combination teaches wherein the inverter comprises a neutral terminal (see par. [0021], neutral line as an O phase (neutral phase); Kidera), and the voltage control circuitry is configured to control the voltage at the second source terminal according to a voltage of the neutral terminal (see par. [0007-0009], wherein the controller controls the midpoint stabilizer in a manner such that the midpoint potential in the neutral line is a midpoint of a voltage waveform between the first voltage line and the second voltage line, and the controller controls the inverter so as to output a voltage waveform of a desired frequency from between the first voltage line and the second voltage line; Kidera). Regarding claim 13, the combination teaches wherein the voltage control circuitry is configured to control the voltage at the second source terminal to be equal to the voltage of the neutral terminal (see par. [0006-0009]; Kidera). Regarding claim 14, the combination teaches wherein the voltage control circuitry is configured to maintain a positive voltage with respect to a ground potential at the first source terminal of the power source (see figures 1-4 and par. [0003], the O phase is subjected to ground connection to a pole transformer; Kidera). Regarding claim 15, the combination teaches wherein the voltage control circuitry (7) is configured to maintain a positive voltage with respect to the ground potential at the second source terminal of the power source (see par. [0062-0067]; Kidera). Regarding claim 16, the combination teaches wherein the voltage control circuitry (7) is configured to maintain a zero voltage with respect to the ground potential at the second source terminal of the power source (see par. [0008], [0043], and [0062-0067]; Kidera). Regarding claim 17, the combination teaches wherein the voltage control circuitry (7) is configured to maintain a negative voltage with respect to a ground potential at the first source terminal of the power source (see par. [0008], [0043], and [0062-0067]; Kidera). Regarding claim 18, the combination teaches wherein the voltage control circuitry (7) is configured to maintain a negative voltage with respect to the ground potential at the second source terminal of the power source (see par. [0008], [0043], and [0062-0067]; Kidera). Regarding claim 19, the combination teaches wherein the voltage control circuitry (7) is configured to maintain a zero voltage with respect to the ground potential at the second source terminal of the power source (see par. [0008], [0043], and [0062-0067]; Kidera). Allowable Subject Matter Claims 2, 4-5, and 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to XUAN LY whose telephone number is (571)272-9885. The examiner can normally be reached M-F 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rexford Barnie can be reached at 571-272-7492. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /XUAN LY/Examiner, Art Unit 2836 /REXFORD N BARNIE/Supervisory Patent Examiner, Art Unit 2836
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Prosecution Timeline

Mar 31, 2025
Application Filed
Jul 15, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
92%
With Interview (+6.5%)
2y 7m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 540 resolved cases by this examiner. Grant probability derived from career allowance rate.

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