DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 3, 7, 10, 13, 14, 16, 18, and 19 have been amended.
Claims 1-20 have been examined.
The specification objections in the previous Office Action have been addressed and are withdrawn.
The § 112 rejections in the previous Office Action have been addressed and are withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 5, 10-12, 16, 17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Publication No. 2019/0310845 by Ramani et al. (hereinafter referred to as “Ramani”).
Regarding claims 1, 10, and 16, taking claim 1 as representative, Ramani discloses:
a method for memory dependency prediction, the method comprising: maintaining, by processing circuitry, a set of store instructions dispatched for execution, each store instruction having a type and one or more attributes (Ramani discloses, at Figure 5 and related description, a method for predicting memory dependency. See, e.g., ¶ [0056]. The method writes dispatched stores, which are understood to each have a type, and attributes to a MEMFILE. See, e.g., ¶ [0061] et seq.); and
in response to identifying a load instruction having a first type and a first set of one or more attributes that correspond to a store instruction in the set of store instructions dispatched for execution, indicating, by the processing circuitry, a memory dependency between the load instruction and the store instruction (Ramani discloses, at Figure 5 and related description, comparing loads, which are understood to each have a type, against stores to detect, e.g., an address match, and in response to detecting a match, indicating a memory dependency.).
Regarding claims 2, 12, and 17, taking claim 2 as representative, Ramani discloses the elements of claim 1, as discussed above. Ramani also discloses:
the indicating the memory dependency is performed using a memory dependence prediction methodology associated with the first type (Ramani discloses, at Figure 5 and related description, using the MEMFILE to detect dependencies, which is a dependence prediction methodology associated with the type of instructions for which it is used.).
Regarding claim 4, Ramani discloses the elements of claim 1, as discussed above. Ramani also discloses:
the first type is associated with a symbolic file addressing structure (Ramani discloses, at Figure 5 and related description, writing dispatched stores to a MEMFILE, which discloses a symbolic file addressing structure.); and
the first set of one or more attributes are at least a base register, an index register, a scale, and a displacement (Ramani discloses, at Figure 5 and related description, attributes including base, index, scale, and displacement.).
Regarding claim 5, Ramani discloses the elements of claim 1, as discussed above. Ramani also discloses:
the first type is associated with a stack addressing structure (Ramani discloses, at Figure 11 and related description, stack access instructions, which discloses a stack addressing structure.); and
the first set of one or more attributes is at least an offset (Ramani discloses, at Figure 11 and related description, attributes including stack offset.).
Regarding claim 11, Ramani discloses the elements of claim 10, as discussed above. Ramani also discloses:
the at least one storage medium includes at least one of registers, cache, and random-access memory (Ramani discloses, at ¶ [0098], storage media that includes RAM.).
Regarding claim 20, Ramani discloses the elements of claim 10, as discussed above. Ramani also discloses:
the circuit is one of one or more central processing units (CPUs), one or more processor chiplets of the one or more CPUs, and one or more cores of a processor chiplet (Ramani disclose, at ¶ [0092], implementing the system using CPUs.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 13, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ramani.
Regarding claims 3, 13, and 18, taking claim 3 as representative, Ramani discloses the elements of claim 1, as discussed above. Ramani also discloses:
the set of store instructions dispatched for execution includes a list of stores… (Ramani discloses, at Figure 5 and related description, writing dispatched stores to a MEMFILE, which discloses a list of stores.).
Ramani does not explicitly disclose the stores have multiple types of memory addressing structures.
However, Ramini discloses stores having multiple types of memory addressing structures. For example, Ramini discloses, in addition to the memory loads and stores, stack access instructions, which use another type of memory addressing structure, i.e., stack offset.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Ramini to include the stores having multiple types of memory addressing structures in a single list in order to improve performance by increasing utilization of the list.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ramani in view of US Publication No. 2020/0004550 by Thakker et al. (hereinafter referred to as “Thakker”) in view of US Publication No. 2024/0338321 by Ingalls (hereinafter referred to as “Ingalls”).
Regarding claim 6, Ramani discloses the elements of claim 1, as discussed above. Ramani also discloses:
the first type is associated with a …relative addressing structure (Ramani discloses, at Figure 11 and related description, stack access instructions, which discloses a relative addressing structure. See, e.g., ¶ [0081].).
Ramni does not explicitly disclose the aforementioned relative addressing structure is rip and the first set of one or more attributes is at least a target address hash.
However, in the same field of endeavor (e.g., processors) Thakker discloses:
PC-relative addressing (Thakker discloses, at ¶ [0061], PC-relative load and store instructions, which discloses rip.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Ramani to include PC-relative instructions, as disclosed by Thakker, in order to improve performance by enabling smaller, more efficient machine code.
Also in the same field of endeavor (e.g., processors) Ingalls discloses:
hashing a target address (Ingalls discloses, at ¶ [0014], hashing a target address.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Ramani to include hashing a target address, as disclosed by Ingalls, in order to improve performance by reducing the amount of storage and processing needed for address comparisons.
Claims 7-9, 14, 15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ramani in view of US Patent No. 7,424,496 by Pardo (hereinafter referred to as “Pardo”).
Regarding claims 7, 14, and 19, taking claim 7 as representative, Ramani discloses the elements of claim 1, as discussed above. Ramani also discloses:
the maintaining the set of store instructions dispatched for execution comprises: a first …[portion] having a first plurality of store instructions that have most been dispatched (Ramani discloses, at Figure 5 and related description, the MEMFILE is an age ordered rotating FIFO, which discloses a first portion having the most recently dispatched stores.); and
a second …[portion] having a second plurality of store instructions that have most been removed from the first …[portion] (Ramani discloses, at Figure 5 and related description, the MEMFILE is an age ordered rotating FIFO, which discloses a second portion having stores that were most recently removed from the first portion.).
Ramani does not explicitly disclose two tables.
However, in the same field of endeavor (e.g., processing) Pardo discloses:
dividing a FIFO into several portions (Pardo discloses, at col. 5, lines 36-38, dividing a FIFO into several portions, which discloses two tables.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Ramani to include Pardo’s disclosure of dividing a FIFO into several portions in order to improve performance by allowing multiple concurrent accesses to the FIFO data. See Pardo, col. 5, lines 36-38.
Regarding claims 8 and 15, taking claim 8 as representative, Ramani discloses the elements of claim 9, as discussed above. Ramani also discloses:
the indicating the memory dependency comprises: matching the first set of one or more attributes to the store instruction within the first table having the first plurality of store instructions (Ramani discloses, at Figure 5 and related description, the indication of dependency is based on an address match of the FIFO entries, which discloses, in conjunction with Pardo, the first table.); and
renaming the store instruction within the first table of the set (Ramani discloses, at Figure 5 and related description, renaming the store instructions in the FIFO.).
Regarding claim 9, Ramani discloses the elements of claim 7, as discussed above. Ramani also discloses:
the indicating the memory dependency comprises: matching the first set of one or more attributes to the store instruction within the second table having the second plurality of store instructions (Ramani discloses, at Figure 5 and related description, the indication of dependency is based on an address match of the FIFO entries, which discloses, in conjunction with Pardo, the second table.); and
retrieving data from a store queue entry using information from the second table (Ramani discloses, at Figure 5 and related description, processing the stores in the FIFO, which discloses, in conjunction with Pardo, retrieving data from the FIFO).
Response to Arguments
On pages 8-9 of the response filed August 26, 2026 (“response”), the Applicant argues, “Neither the above section of Ramani, Fig. 5, nor any other section of Ramani discloses "identifying a load instruction having a first type …that corresponds to a store instruction in the set of store instructions dispatched for execution," as recited by claim 1. In fact, Ramani is silent on types of stores and loads, and as such, does not disclose functionality related to such types. The Office Action states that Ramani discloses "comparing loads, which are understood to each have a type, against stores" (Office Action page 3). Even assuming (without conceding) that each load is understood to have some type, Ramani does not disclose identifying a load instruction having a first type that corresponds to a store instruction," as recited in claim 1. The determination described in Ramani is directed solely to an address-based dependency between a load and a prior store. Ramani contains no disclosure that any load instruction is identified as having a type that corresponds to a store instruction, as required by claim 1. For at least these reasons, claim 1 patentably distinguishes Ramani.”
Though fully considered, the Examiner respectfully disagrees. The claim language is broader than is being argued by the Applicant. The Applicant argues that the claim recites “a load instruction having a first type …that corresponds to a store instruction,” and interprets this as requiring a correspondence between the load instruction’s type and the store instruction. Presumably this refers to a match between the load instruction’s type and the store instruction’s type. However, the claim does not say this. The Examiner maintains that the broadest reasonable interpretation of the claim is that the identifying is of a load instruction corresponds to the store instruction. Whether the correspondence is based on a match between the types of the instructions, a match between the attributes of the instructions, or both, is unspecified in the claim. Therefore, Ramani’s disclosure of identifying correspondence between instructions based on an address (attribute) match discloses the claimed identifying of correspondence. Accordingly, the Applicant’s arguments are deemed unpersuasive.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183
