DETAILED ACTION
Status of the Application
1. Claims 1 – 25 are pending and are under examination in this action.
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1 – 4, 10 – 14, and 22 – 25 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (U.S. Pub. 2022/0005886) in view of Park (U.S. Patent 10,825,390).
Regarding claim 1, Jeong teaches: a display apparatus (FIG. 1; paragraph [0040]; display apparatus) comprising:
a substrate including a display region and a peripheral region outside the display region (FIGS. 1, 4; paragraphs [0006], [0061]; base substrate 100 includes display region DA and a peripheral region NDA outside the display region DA);
a display layer on the substrate (FIG. 4; paragraph [0061]; pixel defining [display] layer PDL is disposed on base substrate 100); and
a scan driver layer interposed between the substrate and the display layer (FIG. 4; paragraph [0061]; second via insulating layer 150 is interpreted as a “scan driver layer” that is disposed between base substrate 100 and pixel defining [display] layer PDL),
wherein, when viewed in a direction perpendicular to the substrate, the scan driver layer comprises a dummy scan driver which is located at a center portion of the display region (FIGS. 1, 5, 6; paragraphs [0078], [0079], [0081], [0092]; when viewed perpendicular to the substrate, a dummy pattern [dummy scan driver] is provided in B region [center portion] of the display region DA. Dummy pattern [dummy scan driver] includes horizontal dummy parts DMh and vertical dummy parts DMv which are disposed on second via insulating layer 150 [scan driver layer]), and
the dummy scan driver comprises a dummy clock line extending in a first direction (FIG. 5; paragraph [0079]; horizontal dummy parts DMh [dummy clock lines] extend in a first direction D1).
Jeong fails to explicitly disclose: wherein, when viewed when viewed in a direction perpendicular to the substrate, the scan driver layer comprises a scan driver which is located within a side portion of the display region next to an edge of the display region.
However, in a related field of endeavor, Park disclose a display device that includes an insulation layers 113 [scan driver layer] between a substrate and a display layer in which sub-pixels (P) are provided (FIGS. 3, 5; col. 7, lines 42 – 46; col. 8, lines 51 – 56).
With regard to claim 1, Park teaches: wherein, when viewed when viewed in a direction perpendicular to the substrate, the scan driver layer comprises a scan driver which is located within a side portion of the display region next to an edge of the display region (FIGS. 3, 5; col. 6, lines 42 – 44; gate drive circuit (SR, EMD) is provided among the insulation layers 113 [scan driver layer]. Gate drive circuit (SR, EMD) is provided in a side portion of the a display region next to a left-most edge of the display region, as illustrated).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of Applicant’s claimed invention to combine the known teachings of Jeong and Park to yield predictable results. More specifically, the teachings of a display device which includes a “dummy scan driver” in an insulating layer between a base substrate and a display layer, as taught by Jeong, are known. Additionally, the teachings of a display device which includes a scan driver disposed next to a left-most edge of a display region and in an insulating layer between a base substrate and a display layer, as taught by Park, are known as well. The combination of the known teachings of Jeong and Park would yield the predictable result of a display device which includes both a scan driver and a “dummy scan driver” in an insulating layer between a base substrate and a display layer, where the scan driver is provided in a left-most edge of a display region. Such a combination merely fills in the gaps of Jeong as to where the scan driver is located using the known teachings of Park. This combination requires nothing more than using known teachings in known ways to yield predictable results by locating disclosed circuitry elements of Jeong in the particular location and layer disposed by Park. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of Applicant’s claimed invention to combine the known teachings of Jeong and Park to yield the aforementioned predictable results.
Regarding claim 10, Jeong teaches: a display apparatus (FIG. 1; paragraph [0040]; display apparatus) comprising:
a substrate including a display region and a peripheral region outside the display region (FIGS. 1, 4; paragraphs [0006], [0061]; base substrate 100 includes display region DA and a peripheral region NDA outside the display region DA);
a display layer on the substrate (FIG. 4; paragraph [0061]; pixel defining [display] layer PDL is disposed on base substrate 100); and
a scan driver layer interposed between the substrate and the display layer (FIG. 4; paragraph [0061]; second via insulating layer 150 is interpreted as a “scan driver layer” that is disposed between base substrate 100 and pixel defining [display] layer PDL),
wherein, when viewed in a direction perpendicular to the substrate, the scan driver layer comprises dummy scan drivers which are located at a center portion of the display region (FIGS. 1, 5, 6; paragraphs [0078], [0079], [0081], [0092]; when viewed perpendicular to the substrate, dummy patterns [dummy scan drivers] are provided in B region [center portion] of the display region DA. Dummy patterns [dummy scan drivers] include horizontal dummy parts DMh and vertical dummy parts DMv which are disposed on second via insulating layer 150 [scan driver layer]), and
the dummy scan drivers comprise dummy clock lines extending in a first direction (FIG. 5; paragraph [0079]; horizontal dummy parts DMh [dummy clock lines] extend in a first direction D1).
Jeong fails to explicitly disclose: wherein, when viewed when viewed in a direction perpendicular to the substrate, the scan driver layer comprises a scan driver which is located within a side portion of the display region next to an edge of the display region.
However, Park teaches: wherein, when viewed when viewed in a direction perpendicular to the substrate, the scan driver layer comprises a scan driver which is located within a side portion of the display region next to an edge of the display region (FIGS. 3, 5; col. 6, lines 42 – 44; gate drive circuit (SR, EMD) is provided among the insulation layers 113 [scan driver layer]. Gate drive circuit (SR, EMD) is provided in a side portion of the a display region next to a left-most edge of the display region, as illustrated).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of Applicant’s claimed invention to combine the known teachings of Jeong and Park to yield predictable results for at least the reasons set forth above with regard to claim 1.
Regarding claims 2 and 11, the combination of Jeong and Park teaches: wherein the scan driver extends in the first direction (It is well-known and conventional for scan drivers to be three dimensional. Accordingly, the “scan driver” set forth above would extend in the first direction as well as a second perpendicular direction. Additionally, Park illustrates in FIG. 3 that the gate drive circuit (SR, EMO), extends in a horizontal [first] direction).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of Applicant’s claimed invention to combine the known teachings of Jeong and Park to yield predictable results for at least the reasons set forth above with regard to claim 1.
Regarding claims 3 and 12, Jeong teaches: wherein the display layer comprises a first display element and a first pixel circuit electrically connected to the first display element (FIG. 4; paragraphs [0086], [0089]; light emitting layer 182 [first display element] and first electrode 181 [first pixel circuit] are formed in pixel defining [display] layer PDL. First electrode 181 [first pixel circuit] is electrically connected to light emitting layer 182 [first display element]), and
the dummy clock line is electrically connected to the first pixel circuit (FIG. 4; paragraphs [0071], [0081]; power line VL applies a first power voltage ELVDD to drive light emitting structure 180 and is thus electrically connected to the first electrode 181 [first pixel circuit]. Power line VL is connected to the dummy pattern and thus horizontal dummy parts DMh [dummy clock lines]. Therefore, horizontal dummy parts DMh [dummy clock lines] are electrically connected to first electrode 181 [first pixel circuit]).
Regarding claims 4 and 13, Jeong teaches: wherein the display layer comprises a first display element disposed over the dummy scan driver (FIG. 4; paragraph [0061]; light emitting structure 180 [first display element] is formed in pixel defining [display] layer PDL and thus over the “dummy scan driver”),
Jeong fails to explicitly disclose: wherein the display layer comprises a first pixel circuit electrically connected to the first display element, the first pixel circuit comprises a first wire extending in a second direction crossing the first direction, and the first wire is electrically connected to the dummy clock line.
However, Park teaches: wherein the display layer comprises a first pixel circuit electrically connected to the first display element (FIGS. 2, 5; col. 8, lines 1 – 3; a display layer in which sub-pixels (P) are provided includes driving transistor DT and associated wirings [first pixel circuit]),
the first pixel circuit comprises a first wire extending in a second direction crossing the first direction (FIG. 2; the “first pixel circuit” includes wirings that extend vertically, i.e., a second direction that crosses the first [horizontal] direction).
The combination of Jeong and Park teaches: the first wire is electrically connected to the dummy clock line (Jeong; FIG. 4; paragraphs [0071], [0081]; power line VL applies a first power voltage ELVDD and is also connected to the dummy pattern and thus horizontal dummy parts DMh [dummy clock lines]. Park; FIG. 2; the wiring connected to VDD and driving transistor DT is the “first wire”. When combined, the “first wire” of Park would be connected to ELVDD of Jeong, which would then be combined to the dummy pattern and thus horizontal dummy parts DMh [dummy clock lines] of Jeong).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of Applicant’s claimed invention to combine the known teachings of Jeong and Park to yield predictable results. More specifically, the teachings of a display device having dummy clock lines that are electrically connected to a power line for supplying an ELVDD voltage to a pixel, as taught by Jeong, are known. Additionally, the teachings of a display device having a pixel structure disposed above a scan driver layer, where the pixel structure includes a first pixel circuit having a first wire extending vertically and connected to a power voltage VDD, as taught by Park, are known as well. The combination of the known teachings of Jeong and Park would yield the predictable result of a display device having a pixel structure disposed above a scan driver layer, where the pixel structure includes a first pixel circuit having a first wire extending vertically and connected to a power line that supplies a power voltage VDD to the first pixel circuit, where the power line is electrically connected to dummy clock lines. In other words, it would have been obvious to apply the apply the dummy clock lines of Jeong to the particular pixel configuration of Park. This would utilize the shielding effect (paragraph [0081]) of the dummy pattern and dummy clock lines of Jeong to improve the functionality and operation of the pixel of Park. This combination requires nothing more than using known teachings in known ways to yield predictable results by applying the dummy pattern and corresponding shielding effect via power lines, as disclosed by Jeong, to the particular pixel arrangement of Park. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of Applicant’s claimed invention to combine the known teachings of Jeong and Park to yield the aforementioned predictable results.
Regarding claim 14, the combination of Jeong and Park teaches: wherein each of the first wires is electrically connected to the dummy clock lines (Jeong; FIG. 4; paragraphs [0071], [0081]; each power line VL applies a first power voltage ELVDD and is also connected to the dummy pattern and thus horizontal dummy parts DMh [dummy clock lines]. Park; FIG. 2; the wiring connected to VDD and driving transistor DT is the “first wire”. When combined, the “first wire” of Park would be connected to ELVDD of Jeong, which would then be combined to the dummy pattern and thus horizontal dummy parts DMh [dummy clock lines] of Jeong).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of Applicant’s claimed invention to combine the known teachings of Jeong and Park to yield predictable results for at least the reasons set forth above with regard to claim 1.
Regarding claims 22 and 24, Jeong teaches: an electronic apparatus including the display apparatus of claim(s) 1 [and 10] (FIGS. 1, 11, 12A, 12B; paragraph [0104]; electronic device 500 may include a display apparatus 560, which is display apparatus of previous figures referred to in the rejection of claims 1 and 10).
Regarding claims 23 and 25, Jeong teaches: wherein the electronic apparatus is at least one of a smartphone, a mobile phone, a navigation device, a game device, a television (TV), a vehicle head unit, a notebook computer, a laptop computer, a tablet computer, a personal media player (PMP), or a personal digital assistant (PDA) (FIGS. 11, 12A, 12B; paragraph [0104]; the electronic device 500 may be implemented as a television, phone, tablet, navigation system, laptop, etc.).
5. Claims 5 – 7, 15 – 17, and 20 – 21 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong in view of Park, as applied to claims 4 and 13 above, in further view of Kim (U.S. Pub. 2024/0257764).
Regarding claims 5 and 15, neither Jeong nor Park explicitly disclose: wherein the first wire and the dummy clock line are electrically connected to a common electrode of the first display element.
However, Kim teaches: wherein the first wire and the dummy clock line are electrically connected to a common electrode of the first display element (FIG. 2; paragraphs [0065], [0173], [0189]; light emitting element ED includes common electrode CE that is electrically connected to driving transistor, associated vertical wirings [first wire] and driving voltage EVDD. As set forth above with regard to claim 4, Jeong teaches electrically connecting a driving voltage ELVDD to the dummy clock lines. Accordingly, when combined, driving voltage EVDD would be connected to the dummy clock lines which would then be connected to the common electrode CE via the first wire).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of Applicant’s claimed invention to combine the known teachings of Jeong, Park, and Kim to yield predictable results. More specifically, the teachings of a display device having a pixel structure that includes a first wire extending vertically and connected to a driving transistor and a power line that supplies a power voltage VDD and is electrically connected to dummy clock lines, as taught by the combination of Jeong and Park, are known. Additionally, the teachings of a display device having a pixel structure where a common electrode of a light emitting element is electrically connected to a driving transistor, vertically arranged wiring, and driving voltage source EVDD, as taught by Kim, are known as well. The combination of the known teachings of Jeong, Park, and Kim would yield the predictable result of a display device having a pixel structure that includes a first wire extending vertically and connected to a driving transistor and a power line that supplies a power voltage VDD and is electrically connected to dummy clock lines, where the first wire and dummy clock lines are both connected to a common electrode of a light emitting element. In other words, it would have been obvious to apply the apply the dummy clock lines of Jeong to the particular pixel configuration of Kim. This would utilize the shielding effect (paragraph [0081]) of the dummy pattern and dummy clock lines of Jeong to improve the functionality and operation of the pixel of Kim. This combination requires nothing more than using known teachings in known ways to yield predictable results by applying the dummy pattern and corresponding shielding effect via power lines, as disclosed by Jeong, to the particular pixel arrangement of Kim. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of Applicant’s claimed invention to combine the known teachings of Jeong, Park, and Kim to yield the aforementioned predictable results.
Regarding claims 6 and 16, neither Jeong nor Park explicitly disclose: wherein the first wire and the dummy clock line are electrically connected to an initialization transistor of the first pixel circuit.
However, Kim teaches: wherein the first wire and the dummy clock line are electrically connected to an initialization transistor of the first pixel circuit (FIG. 2; paragraph [0070]; either transistor T6 or T7 are “initialization transistors”. Both transistors T6 and T7 are electrically connected to EVDD, which as set forth above with regard to claims 5 and 15, is connected to the “first wire” and “dummy clock lines”, when combined with Jeong).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of Applicant’s claimed invention to combine the known teachings of Jeong, Park, and Kim to yield predictable results for at least the reasons set forth above with regard to claims 5 and 15.
Regarding claims 7 and 17, neither Jeong nor Park explicitly disclose: wherein the first wire and the dummy clock line are electrically connected to a bias transistor of the first pixel circuit.
However, Kim teaches: wherein the first wire and the dummy clock line are electrically connected to a bias transistor of the first pixel circuit (FIG. 2; paragraph [0070]; transistor T5 is a bias transistor which is electrically connected to EVDD, which as set forth above with regard to claims 5 and 15, is connected to the “first wire” and “dummy clock lines”, when combined with Jeong).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of Applicant’s claimed invention to combine the known teachings of Jeong, Park, and Kim to yield predictable results for at least the reasons set forth above with regard to claims 5 and 15.
Regarding claim 20, Jeong teaches: wherein the display layer comprises first display elements disposed over the dummy scan drivers (FIG. 4; paragraph [0061]; light emitting structures 180 [first display elements] are formed in pixel defining [display] layer PDL and thus over the “dummy scan drivers”).
Neither Jeong nor Park explicitly disclose: wherein the display layer comprises first pixel circuits electrically connected to the first display elements, respectively, the first pixel circuits comprise first first wires extending in a second direction crossing the first direction and arranged in the first direction, and second first wires extending in the second direction and arranged in the first direction, the first first wires are electrically connected to a first group of the dummy clock lines, and the second first wires are electrically connected to a second group of the dummy clock lines.
However, Kim teaches: the first pixel circuits comprise first first wires extending in a second direction crossing the first direction and arranged in the first direction (FIG. 2; the illustrated pixel circuit includes vertical wirings such as the wiring extending between EVDD and Vini and the wiring extending between node N2 and EVSS. Each of these wirings in each pixel circuit may be interpreted as “first first wires” that extend vertically [second direction] but are arranged horizontally [first direction]), and second first wires extending in the second direction and arranged in the first direction (FIG. 2; the illustrated pixel circuit includes horizontal wirings such as the wiring from a source of driving transistor DRT and Vobs, as well as several others. Each of these wirings in each pixel circuit may be interpreted as “second first wires” that extend horizontally [first direction] but are arranged vertically [second direction]),
the first first wires are electrically connected to a first group of the dummy clock lines (As set forth above with regard to claims 5 and 15, EVDD is connected to the “dummy clock lines” when combined with Jeong. Since the “first first wires” are connected to EVDD, the “first first wires” would be connected to the “dummy clock lines”), and
the second first wires are electrically connected to a second group of the dummy clock lines (As set forth above with regard to claims 5 and 15, EVDD is connected to the “dummy clock lines” when combined with Jeong. Since T5 is connected to the “second first wires”, the “second first wires” would be connected to the “dummy clock lines”. Since there is no distinction between the “first group” and “second group”, this relationship is enough to read on the claims as presently recited).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of Applicant’s claimed invention to combine the known teachings of Jeong, Park, and Kim to yield predictable results for at least the reasons set forth above with regard to claims 5 and 15.
Regarding claim 21, neither Jeong nor Park teaches: wherein the first first wires are electrically connected to initialization transistors of the first pixel circuits, and the second first wires are electrically connected to bias transistors of the first pixel circuits.
However, Kim teaches: wherein the first first wires are electrically connected to initialization transistors of the first pixel circuits (FIG. 2; paragraph [0070]; either transistor T6 or T7 are “initialization transistors”. Both transistors T6 and T7 are electrically connected to the “first first wires”, as set forth above with regard to claim 20), and the second first wires are electrically connected to bias transistors of the first pixel circuits (FIG. 2; paragraph [0070]; transistor T5 is a bias transistor which is electrically connected to the “second first wires” as set forth above with regard to claim 20).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of Applicant’s claimed invention to combine the known teachings of Jeong, Park, and Kim to yield predictable results for at least the reasons set forth above with regard to claims 5 and 15.
Allowable Subject Matter
6. Claims 8 – 9 and 18 – 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/RYAN A LUBIT/Primary Examiner, Art Unit 2626