DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamazaki et al. (USP 9,494,830).
Regarding claim 5, Yamazaki et al.’s figure 1B shows A semiconductor device comprising: a first transistor (14), a second transistor (16), a third transistor (17), and a fourth transistor (18), wherein one of a source and a drain of the first transistor (14) is electrically connected to a first output terminal (junction point of 14 and 16), wherein the other of the source and the drain of the first transistor (14) is electrically connected to a first wiring (wire connects to VDD), wherein one of a source and a drain of the second transistor (16) is electrically connected to the first output terminal (junction point of 14 and 16), wherein the other of the source and the drain of the second transistor (16) is electrically connected to a second wiring (wire connects to Vss), wherein one of a source and a drain of the third transistor (17) is electrically connected to a second output terminal (junction point of 15 and 17), wherein the other of the source and the drain of the third transistor (17) is supplied with a first potential (Vss), wherein one of a source and a drain of the fourth transistor (15) is electrically connected to the second output terminal, wherein the other of the source and the drain of the fourth transistor is supplied with a second potential (VDD), wherein a first gate of the second transistor is electrically connected to a second gate of the second transistor (16; gate and back gate are connected together), wherein a gate of the fourth transistor is electrically connected to the first gate of the second transistor, wherein a first signal (RIN) is supplied to the first gate of the second transistor (16), wherein a first gate of the third transistor is electrically connected to a second gate of the third transistor (gate and back gate of the transistor 17 are connected together), and wherein a second signal is supplied to the first gate of the third transistor (LIN) as called for in claim 5.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (USP 9,494,830) in view of Nagatsuka et al. (USP 9,048,105).
Regarding claim 6, Yamazaki et al. reference discloses a semiconductor device comprising all the aspects of the present invention as noted above except for the first to fourth transistors are each a transistor comprising a metal oxide in a channel formation region as called for in claim 6.
Nagatsuka et al. reference teaches that oxide semiconductor transistor has extremely small leakage current. Therefore, it would have been obvious to persons skilled in the art before the effective filing date of the invention to have Miyake’s transistors made with metal oxide in a channel formation region for the purpose of preventing leakage current as taught by Nagatsuka et al. reference.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyake (USP 7,932,888) in view of Elgharbawy et al. (US 2007/0267702).
Regarding claim 7, Miyake’s figure 7B shows A semiconductor device comprising: a first transistor (2030), a second transistor (2040), a third transistor (2020), a fourth transistor (2010), and a fifth transistor (2060), wherein one of a source and a drain of the first transistor (2030) is electrically connected to a first output terminal (junction point of transistors 2030 and 2040), wherein the other of the source and the drain of the first transistor (2030) is electrically connected to a first wiring (wires connected to VDD), wherein one of a source and a drain of the second transistor (204) is electrically connected to the first output terminal (junction point of transistors 2030 and 2040) , wherein the other of the source and the drain of the second transistor (2040) is electrically connected to a second wiring (wire connected to VSS), wherein one of a source and a drain of the third transistor (2020) is electrically connected to a second output terminal (junction point of transistors 2010 and 2020), wherein the other of the source and the drain of the third transistor (2020) is supplied with a first potential (vss), wherein one of a source and a drain of the fourth transistor (2010) is electrically connected to the second output terminal, wherein the other of the source and the drain of the fourth transistor (2010) is supplied with a second potential (VDD), wherein a gate of the fourth transistor (2010) is electrically connected to the first gate of the second transistor (2040), wherein one of a source and a drain of the fifth transistor (2060) is electrically connected to the second output terminal (junction point of transistors 2010 and 2020), wherein a first signal (signal at node 2) is supplied to the first gate of the second transistor (2040), and wherein a second signal (signal at node 3) is supplied to the first gate of the third transistor (2020).
Miyake’s figure 7B does not show wherein a first gate of the second transistor is electrically connected to a second gate of the second transistor; wherein a first gate of the third transistor is electrically connected to a second gate of the third transistor as called for in claim 7.
Elgharbawy et al.’s figure 1 teaches that by connecting a gate electrode and back gate together would enhance performance and lower circuit’s delay (see paragraphs 0010). Therefore, it would have been obvious to person skilled in the art before the effective filing of the present invention to have Miyake’s a first gate of the second transistor is electrically connected to a second gate of the second transistor; and a first gate of the third transistor is electrically connected to a second gate of the third transistor in order to enhance performance and lower circuit’s delay as taught by Elgharbawy et al. reference.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyake (USP 7,932,888) and Elgharbawy et al. (US 2007/0267702) and further in view of Nagatsuka et al. (USP 9,048,105).
Regarding claim 8, the combination of Miyake and Elgharbawy et al. reference discloses a semiconductor device comprising all the aspects of the present invention as noted above except for the first to fifth transistors are each a transistor comprising a metal oxide in a channel formation region as called for in claim 8.
Nagatsuka et al. reference teaches that oxide semiconductor transistor has extremely small leakage current. Therefore, it would have been obvious to persons skilled in the art before the effective filing date of the invention to have Miyake’s transistors made with metal oxide in a channel formation region for the purpose of preventing leakage current as taught by Nagatsuka et al. reference.
Allowable Subject Matter
Claims 2-4 are presently allowed.
The following is a statement of reasons for the indication of allowable subject matter: closest prior art of record, Yamazaki et al. (USP 9,494,830) fails to teach or fairly suggest a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; wherein a first gate of the fifth transistor is electrically connected to the third input terminal, wherein a second gate of the fifth transistor is electrically connected to the first output terminal, wherein one of a source and a drain of the sixth transistor is electrically connected to the first output terminal, wherein the other of the source and the drain of the sixth transistor is electrically connected to the first wiring, wherein a first gate of the sixth transistor is electrically connected to the fourth input terminal, wherein a second gate of the sixth transistor is electrically connected to the first output terminal, wherein one of a source and a drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor, wherein the other of the source and the drain of the seventh transistor is electrically connected to the first wiring, wherein a first gate of the seventh transistor is electrically connected to the first input terminal, wherein a second gate of the seventh transistor is electrically connected to the second output terminal, wherein the other of the source and the drain of the eighth transistor is electrically connected to the second output terminal, wherein a first gate of the eighth transistor is electrically connected to the second input terminal, and wherein a second gate of the eighth transistor is electrically connected to the second output terminal as called for in claim 2.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In this regard, applicant’s cited prior art has been carefully considered.
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/TUAN T LAM/Primary Examiner, Art Unit 2836 6/22/2026
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