DETAILED ACTION
The action is responsive to the following communications: the Application filed April 01, 2025. This application is a CON of 18/364,524.
Claims 1-40 are pending Claims 1-20 were cancelled. Claims 21, 26 and 33 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention, MEMORY SYSTEM, is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The drawings are objected to because:
Figures 1-4 should be designated by a legend such as –Prior Art—because only that which is old is illustrated. See MPEP 608.02(g).
Applicant is reminded of helpful scenario 7, described in MPEP 2004, and encouraged to carefully review instant application’s Specification and Figures to make sure care is taken to see that prior art or other information cited in the Specification and Figures or in an information disclosure statement is properly described and that the information is not incorrectly or incompletely characterized. MPEP 2004, Scenario 7; see also MPEP 2010.
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US Patent No. 12,293,787. Although the claims at issue are not identical, they are not patentably distinct from each other.
Instant Application
US Patent 12,293,787
Comment
Claim 21 A memory system comprising:
a nonvolatile memory including:
a substrate,
a memory block disposed above the substrate in a first direction, the memory block including a first memory string extending in the first direction, a second memory string extending in the first direction, and a third memory string extending in the first direction, the first memory string adjacent to the second memory string in a second direction intersecting the first direction, the first memory string including a first memory cell and a second memory cell connected in series with each other, the second memory string including a third memory cell and a fourth memory cell connected in series with each other, the third memory string including a fifth memory cell and a sixth memory cell connected in series with each other, each of the first to sixth memory cells capable of storing 4-bit data of first to fourth bits identified by sixteen threshold voltage regions,
a first word line connected to a gate of the first memory cell, a gate of the third memory cell, and a gate of the fifth memory cell, and
a second word line connected to a gate of the second memory cell, a gate of the fourth memory cell, and a gate of the sixth memory cell; and
a controller configured to execute a program operation including a first stage program operation and a second stage program operation,
wherein among fifteen boundaries each existing between two adjacent threshold voltage regions from the sixteen threshold voltage regions, a number of first boundaries for determining a value of the first bit of the 4-bit data, a number of second boundaries for determining a value of the second bit of the 4-bit data, a number of third boundaries for determining a value of the third bit of the 4-bit data, and a number of fourth boundaries for determining a value of the fourth bit of the 4-bit data are 1, 2, 6, 6 in that order,
wherein the first stage program operation is executed to store at least the first bit of the 4-bit data at a memory cell of the memory block, and
wherein the second stage program operation is executed to store at least the third bit and the fourth bit of the 4-bit data at the memory cell of the memory block.
Claim 2. A memory system comprising:
a nonvolatile memory which comprises a plurality of
memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first
threshold region indicating an erased state for erasing data and second to sixteenth threshold regions having
higher voltage levels than a voltage level of the first threshold region and indicating a written state for
writing data; and
a controller configured to cause the nonvolatile memory
to execute a first program for writing data of the first bit and then cause the nonvolatile memory to execute a
second program for writing data of the second bit, the third bit, and the fourth bit, wherein among fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, the number of first boundaries used for determining
a value of the data of the first bit, the number of second boundaries used for determining a value of
the data of the second bit, the number of third boundaries used for determining a value of the data of the
third bit, and the number of fourth boundaries used for determining a value of the data of the fourth bit are 1, 4, 5, 5 or 1, 6, 4, 4, or 1, 2, 6, 6 or 1, 5, 5, 4 or 1, 5, 4, 5 or 1, 4, 6, 4 or 1, 4, 4, 6 or 1, 5, 6, 3 or 1, 5, 3, 6 or 40
1, 3, 6, 5 or 1, 3, 5, 6 or 1, 6, 5, 3 or 1, 6, 3, 5 in order.
Claim 7. The memory system according to claim 2, wherein
the plurality of memory cells in the nonvolatile memory comprise a plurality of first memory cells connected to a first word line and a plurality of second memory cells
connected to a second word line adjacent to the first word line, and
the controller is configured to cause the nonvolatile memory to execute the first program on the plurality of
second memory cells after causing the nonvolatile memory to execute the first program on the plurality of
first memory cells, and cause the nonvolatile memory to execute the second program on the plurality of first memory cells after causing the nonvolatile memory to execute the first program on the plurality of second memory cells.
Note footnote1
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 29-31 and 37-39 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 29 and 37 recite “a first program execution command to initiate executing the first stage program operation, after issuing the first input start command and the second input start command”.
Claims 30 and 38 recite “a second program execution command to initiate executing the second stage program operation, after issuing the third input start command and the fourth input start command”.
There is not disclosure of these limitations from the specification. So these languages constitute new matter.
Claims 31 and 39 are rejected due to claim dependency.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-28, 32-36 and 40 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hara et al. (US 9,830,983).
Regarding independent claims 21, 26 and 33, Hara et al. disclose a memory system comprising:
a nonvolatile memory (see FIGS. 3-4) including:
a substrate (FIG. 4 and col. 6, lines 6-7: semiconductor substrate),
a memory block disposed above the substrate (FIGS. 3-4, further it’s an inherent characteristic) in a first direction (vertical direction), the memory block including a first memory string extending in the first direction, a second memory string extending in the first direction, and a third memory string extending in the first direction, the first memory string adjacent to the second memory string in a second direction (horizontal direction) intersecting the first direction, the first memory string including a first memory cell and a second memory cell connected in series with each other, the second memory string including a third memory cell and a fourth memory cell connected in series with each other, the third memory string including a fifth memory cell and a sixth memory cell connected in series with each other, each of the first to sixth memory cells capable of storing 4-bit data of first to fourth bits identified by sixteen threshold voltage regions (see FIG. 3 and FIGS. 36-37, and accompanying disclosure),
a first word line (e.g., WL0) connected to a gate of the first memory cell, a gate of the third memory cell, and a gate of the fifth memory cell, and
a second word line (WL1) connected to a gate of the second memory cell, a gate of the fourth memory cell, and a gate of the sixth memory cell; and
a controller (FIG. 2: CONTROL UNITE) configured to execute a program operation including a first stage program operation and a second stage program operation (FIGS. 36-37, programing operations),
wherein among fifteen boundaries each existing between two adjacent threshold voltage regions from the sixteen threshold voltage regions, a number of first boundaries for determining a value of the first bit of the 4-bit data, a number of second boundaries for determining a value of the second bit of the 4-bit data, a number of third boundaries for determining a value of the third bit of the 4-bit data, and a number of fourth boundaries for determining a value of the fourth bit of the 4-bit data are 1, 2, 6, 6 in that order (see FIGS 36-37 and accompanying disclosure),
wherein the first stage program operation is executed to store at least the first bit of the 4-bit data at a memory cell of the memory block (FIGS. 36-37, Middle or Lower page data), and
wherein the second stage program operation is executed to store at least the third bit and the fourth bit of the 4-bit data at the memory cell of the memory block (FIGS. 36-37, Higher or Upper page data).
Regarding claim 22, which depends from claim 21, Hara et al. further teach the controller is configured to: execute the first stage program operation to the first memory cell of the first memory string, and execute the first stage program operation to the third memory cell of the second memory string, after executing the first stage program operation to the first memory cell of the first memory string (see FIGS. 36-37 along with flash memory strings in FIG. 3, and accompanying disclosure).
Regarding claims 23-24, which depends from claim 22, Hara et al. further teach the controller is configured to: execute the first stage program operation to the fifth memory cell of the third memory string, after executing the first stage program operation to the third memory cell of the second memory string, execute the first stage program operation to the second memory cell of the first memory string, after executing the first stage program operation to the fifth memory cell of the third memory string, and execute the second stage program operation to the first memory cell of the first memory string, after executing the first stage program operation to the second memory cell of the first memory string; and the controller is configured to: execute the first stage program operation to the second memory cell of the first memory string, after executing the first stage program operation to the third memory cell of the second memory string, and execute the second stage program operation to the first memory cell of the first memory string, after executing the first stage program operation to the second memory cell of the first memory string (see FIGS. 36-37 along with flash memory strings in FIG. 3, and accompanying disclosure).
Regarding claim 25, which depends from claim 22, Hara et al. further teach the controller is configured to: execute one sense operation to read the first bit of the 4-bit data, execute six sense operations to read the third bit of the 4-bit data, and execute additional six sense operations to read the fourth bit of the 4-bit data (see e.g., FIG. 29, READ .., and accompanying disclosure; i.e., READ operation which is claimed a sense operation).
Regarding claims 27-28, which depends from claim 26, Hara et al. further teach the controller is configured to adjust the second program voltage, according to the state of the one or more bits of the 4-bit data stored at the first memory cell in the first stage program operation; wherein the second stage program operation includes iteratively incrementing a voltage level of the second program voltage and applying the second program voltage to the first word line, until the remaining bits of the 4-bit data are stored at the first memory cell (see FIGS. 8A-B along with FIGS. 36-37, and accompanying disclosure).
Claim 29 (New) The memory system of claim 26, wherein the controller is configured to:issue, to the nonvolatile memory, a first input start command of the first bit of the 4- bit data to be stored at the first memory cell,issue, to the nonvolatile memory, a second input start command of the second bit of the 4-bit data to be stored at the first memory cell, andissue, to the nonvolatile memory, a first program execution command to initiate executing the first stage program operation, after issuing the first input start command and the second input start command.
Claim 30 (New) The memory system of claim 29, wherein the controller is configured to:issue, to the nonvolatile memory, a third input start command of the third bit of the 4- bit data to be stored at the first memory cell,issue, to the nonvolatile memory, a fourth input start command of the fourth bit of the 4-bit data to be stored at the first memory cell, andissue, to the nonvolatile memory, a second program execution command to initiate executing the second stage program operation, after issuing the third input start command and the fourth input start command.
Claim 31 (New) The memory system of claim 30, wherein the controller is configured to issue the third input start command and the fourth input start command, after issuing the first program execution command.
Regarding claims 32 and 40, which depends from claims 26 and 33, Hara et al. further teach the controller is configured to: execute one sense operation to read the first bit of the 4-bit data, execute six sense operations to read the third bit of the 4-bit data, and execute additional six sense operations to read the fourth bit of the 4-bit data (see e.g., FIG. 12, Read operations, and accompanying disclosure).
Regarding claim 34, which depends from claim 33, Hara et al. further teach the first stage program operation includes applying a third program voltage to the word line to store one or more bits of the 4-bit data at another target NAND memory cell of the group of NAND memory cells, and wherein the second program voltage is applied to the word line to store the remaining bits of the 4-bit data at the target NAND memory cell, after the third program voltage is applied to the word line to store the one or more bits of the 4-bit data at the another target NAND memory cell of the group of NAND memory cells (see e.g., col. 5, lines 26-34: … a memory cell group MG …).
Regarding claims 35-36, which depends from claim 33, Hara et al. further teach the controller is configured to adjust the second program voltage, according to the state of the one or more bits of the 4-bit data stored at the target NAND memory cell in the first stage program operation; wherein the second stage program operation includes iteratively incrementing a voltage level of the second program voltage and applying the second program voltage to the word line, until the remaining bits of the 4-bit data are stored at the target NAND memory cell (see e.g., FIGS. 32-37 and accompanying disclosure, i.e., 4 bits/cell).
Allowable Subject Matter
Claims 29-31 and 37-39 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if overcoming 112(a) rejection as indicated above rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
1 Re independent claims 21, 26 and 33, claims of US Patent recites all the claimed limitations. The various dependent claims are anticipated by/obvious in view of the conflicting patent.
Prosecution Insights