DETAILED ACTION
This Final action is in response to an amendment filed 9/7/2026. Currently claims 1-21 are pending, but claims 5-8, 12-14 and 16-18 remain withdrawn as directed to non-elected subject matter and claims 1-4, 9-11, 15 and 19-21 are examined as follows.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 9-10, 15 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. in US 2023/0215351 (hereinafter Kim).
Regarding claim 1, Kim disclose a display apparatus (Kim’s par. 3-4) comprising:
a display panel (Kim’s Fig. 1 and par. 44) including a pixel (Kim’s Fig. 1 and par. 51: SP); and
a display panel driver (Kim’s Fig. 1 and par. 44: see 120-140, 180) which drives the display panel (Kim’s Fig. 1 and par. 46-49),
wherein the display panel driver (Kim’s Fig. 1: see 120-140, 180) includes a voltage generator (Kim’s Fig. 1 and par. 49: see 180) which applies a power voltage (Kim’s Fig. 1 and par. 49: EVDD or EVSS) based on a power current (Kim’s Fig. 7 and par. 68-69: IEVDD or ISEN) to the display panel (Kim’s Fig. 7: EVDD to 150),
wherein the voltage generator (Kim’s Fig. 7: see 180) generates a compensation current (Kim’s Figs. 8, 13 and par. 72: EVDD CURRENT or EVDD Output Current satisfying set current EVDD SET CURRENT) during a period synchronized to a period during which the pixel emits light (Kim’s Figs. 13, 16 and par. 90-91, 101: EVDD Output Current is generated during the periods synchronized with emission in Gli-1, Gli and Gli+1), and
wherein the power voltage (Kim’s Fig. 7: EVDD) is applied to the display panel (Kim’s Fig. 7: see 150) based on the compensation current (Kim’s Fig. 8 and par. 91: EVDD based on EVDD set current).
Regarding claim 2, Kim discloses wherein the display panel driver (Kim’s Fig. 1: see 120-140, 180) further includes:
an emission driver (Kim’s Fig. 1 and par. 47: scan driver 130 which includes lines GL1 for supplying EM1 in Fig. 6 per par. 60) which outputs an emission signal (Kim’s Fig. 6 and par. 60: EM1); and
a driving controller (Kim’s Fig. 1 and par. 44: see 120) which controls the voltage generator and the emission driver (Kim’s Figs. 1, 4 and par. 46),
wherein the pixel emits light in response to the emission signal (Kim’s Fig. 6 and par. 60-61: emission control signal applied during emission period), and
wherein the compensation current is generated during a period in which the emission signal has an activation level (Kim’s Fig. 8 and par. 91-93: EVDD current maintained to EVDD set current [thus generated] during emission operation, where the emission period includes the activation level of the emission signal per par. 60-61 and Fig. 6).
Regarding claim 9, Kim disclose wherein a frame period (Kim’s Fig. 7: scan of AA) in which the pixel is driven (Kim’s par. 59-61) includes a writing period in which a data voltage is applied (Kim’s Fig. 6 and par. 61: writing period) and an emission period in which the pixel emits light based on the data voltage (Kim’s Fig. 6 and par. 61: emission period), and wherein the compensation current is generated in the emission period (Kim’s Fig. 8 and par. 91-93: EVDD current maintained to EVDD set current [thus generated] during emission operation).
Regarding claim 10, discloses wherein a frame period (Kim’s Fig. 7: scan of AA) in which the pixel is driven (Kim’s par. 59-61) includes a writing period in which a data voltage is applied (Kim’s Fig. 6 and par. 61: writing period) and an emission period in which the pixel emits light based on the data voltage (Kim’s Fig. 6 and par. 61: emission period), and wherein the voltage generator (Kim’s Fig. 7: see 180) outputs the compensation current to the display panel in the emission period (Kim’s par. 91-93: EVDD current output during emission operation).
Regarding claim 15, Kim disclose wherein power voltage (Kim’s Fig. 1 and par. 49: EVDD or EVSS) includes a first power voltage and a second power voltage (Kim’s Fig. 1 and par. 49: EVDD and EVSS), and the first power voltage is applied based on the power current (Kim’s Fig. 7 and par. 68-69: EVDD applied based on IEVDD or ISEN), wherein the pixel (Kim’s Fig. 6) includes:
a first transistor (Kim’s Fig. 6: see DT) which generates a driving current (Kim’s Fig. 6 and par. 61: driving current) based on a data voltage (Kim’s Fig. 6 and par. 61: data voltage);
a second transistor (Kim’s Fig. 6: see T2) which applies the data voltage to the first transistor (Kim’s Fig. 6 and par. 61: data voltage from DL1 to DT [shown through T2]) in response to a gate signal (Kim’s Fig. 6 and par. 60: T2 turned on in response to scan signal);
a third transistor (Kim’s Fig. 6: see T3) which applies the first power voltage (Kim’s Fig. 6: EVDD) to the first transistor (Kim’s Fig. 6: DT) in response to an emission signal (Kim’s Fig. 6 and par. 60-61: EM1); and
a light emitting element (Kim’s Fig. 6 and par. 61: OLED) which emits light based on the driving current (Kim’s Fig. 6 and par. 61).
Regarding claim 21, Kim disclose an electronic apparatus (Kim’s par. 3-4: display device) comprising:
a display panel (Kim’s Fig. 1 and par. 44) including a pixel (Kim’s Fig. 1 and par. 51: SP);
a display panel driver (Kim’s Fig. 1 and par. 44: see 120-140, 180) which drives the display panel (Kim’s Fig. 1 and par. 46-49) based on an input control signal (Kim’s Fig. 1 and par. 45: driving signals from 110); and
a processor (Kim’s Fig. 1 and par. 45: host 110 supplying images) which outputs the input control signal (Kim’s Fig. 1 and par. 45: driving signals from 110),
wherein the display panel driver (Kim’s Fig. 1: see 120-140, 180) includes a voltage generator (Kim’s Fig. 1 and par. 49: see 180) which applies a power voltage (Kim’s Fig. 1 and par. 49: EVDD or EVSS) based on a power current (Kim’s Fig. 7 and par. 68-69: IEVDD or ISEN) to the display panel (Kim’s Fig. 7: EVDD to 150),
wherein the voltage generator (Kim’s Fig. 7: see 180) generates a compensation current (Kim’s Figs. 8, 13 and par. 72: EVDD CURRENT or EVDD Output Current satisfying set current EVDD SET CURRENT) during a period synchronized to a period during which the pixel emits light (Kim’s Figs. 13, 16 and par. 90-91, 101: EVDD Output Current is generated during the periods synchronized with emission in Gli-1, Gli and Gli+1), and
wherein the power voltage (Kim’s Fig. 7: EVDD) is applied to the display panel (Kim’s Fig. 7: see 150) based on the compensation current (Kim’s Fig. 8 and par. 91: EVDD based on EVDD set current).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kim.
Kim discloses wherein the driving controller (Kim’s Fig. 1: see 120) outputs an emission start signal (Kim’s par. 47: gate timing control signal GDC) to the emission driver (Kim’s par. 47: scan driver 130), wherein the emission driver (Kim’s par. 47: scan driver 130) generates the emission signal based on the emission start signal (Kim’s par. 47: scan signal in response to signal GDC, where the scan signal is supplied to lines GL1 which include the supply of signal EM1 in Fig. 6 per par. 60).
Kim fails to disclose wherein the compensation current is generated based on the emission start signal.
However, Kim does disclose continuously adjusting the EVDD current for the scanning of each line (Kim’s par. 91), and the scanning of each line based on the emission start signal (Kim’s par. 47: gate timing control signal GDC controls the line GL1 which supplies the emission signal EM in Fig. 6). Therefore, given that the compensation current (Kim’s Fig. 13: EVDD Output current satisfying EVDD set current) is adjusted [generated] every scan line including during emission (Kim’s Fig. 13 and par. 91), and given that the scanning of each line is based on the emission start signal (Kim’s par. 47: GDC), thus it would have been obvious to one of ordinary skill in the art that the EVDD Output current is generated based on the gate timing control signal GDC, in order to obtain the predictable result of adjusting the EVDD Output current during the scan (Kim’s par. 91) as initiated by GDC (Kim’s par. 47).
By doing such combination, Kim discloses:
wherein the compensation current is generated based on the emission start signal (Kim’s Fig. 13 and par. 91: EVDD CURRENT satisfying set current continuously adjusted [generated] as each line of subpixels is scanned, and because the scanning of each line is based on the gate timing control signal GDC per par. 47, thus it is obvious that EVDD current satisfying the set current is generated based on the gate timing control signal GDC).
Allowable Subject Matter
Claims 19-20 are allowed and Claims 4 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 9/07/2026 have been fully considered but they are not persuasive.
On the Remarks pgs. 11-12, Applicant argues with respect to claim 1 that Kim does not disclose the amended limitation, because Kim’s power supply 180 outputs a standard operating current EVDD_CURRENT to satisfy a target set current EVDD SET CURRENT when pixels begin light emission, while being silent as to a voltage generator that actively generates a discrete compensation current during a period synchronized to the pixel’s light emission period. The office must respectfully disagree, please see above rejection addressing the amended limitations. Independent claims 1 or 21 do not require a discrete compensation current, nor does the term “discrete” appear in the specification. Kim’s Figs. 13, 16 and par. 90-91 and 101 disclose the generation of the EVDD Output Current in synchronization with the emission operation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/LILIANA CERULLO/Primary Examiner, Art Unit 2621
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