DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The references cited in the IDS have been considered by examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: DISPLAY DEVICE HAVING A DATA DRIVER HAVING DIFFERENT TRANSISTOR AREAS AND ELECTRONIC DEVICE INCLUDING THE SAME.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu (U.S. Patent Pub. No. 2015/0325214) in view of Hwang et al (U.S. Patent Pub. No. 2021/0335277).
Regarding claim 1, Ryu discloses a data driver (100), (fig. 1), comprising:
a first latch (LT2_1) that provides a first color grayscale (red data R1) in a first voltage range (VDD1), (fig. 2, [0060 and 0077-0082]);
a first level shifter (LS_1) that converts the first color grayscale (R1) in the first voltage range (VDD1) into a first color grayscale (i.e. shifts a voltage level of the data from the latch LT2_1 and outputs data with a shifted increased voltage level) in a second voltage range (VDD2) greater than the first voltage range (i.e. VDD2 is higher than VDD1), (fig. 2 [0060 and 0083-0085]);
a first digital-to-analog converter (DAC_1) that provides a first gamma voltage (i.e. grayscale voltage Vk) of the first color grayscale based on the second voltage range (VDD2), (fig. 2, [0063 and 0086-0087]).
However, Ryu does not mention a first decoder.
In a similar field of endeavor, Hwang teaches
a first decoder (174) that generates a first gate control signal (SWS1-SWS2N-M) in the second voltage range (i.e. since the decoder 174 is in the DAC 170, hence it would be driven by voltage VDD2 as taught by Ryu) based on the first color grayscale (red data R1 taught by Ryu) in the second voltage range (voltage VDD2 taught by Ryu), (figs. 1 and 12, [0049 and 0070-0071]); and
a first digital-to-analog converter (172) that provides a first gamma voltage (TDGVS1-TDGVS2N-M) of the first color grayscale (red data R1 taught by Ryu) based on the first gate control signal (SWS1-SWS2N-M) in the second voltage range (voltage VDD taught by Ryu), (fig. 12, [0071]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Ryu, by specifically providing the decoder, as taught by Hwang, for the purpose of providing a data driver having a reduced size, [0004].
Regarding claim 3, Hwang discloses wherein the first decoder (174) receives the first color grayscale (PDAT) through N wires (i.e. one wire line for transmitting data PDAT to decoder 174), and outputs the first gate control signal (i.e. decoder 174 output signals SWS1 to SWS2N-M) through M wires (i.e. N-M lines for controlling switches SW1-SW2N-M), N is an integer greater than 0, and M is an integer greater than N, (fig. 12, [0071]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Ryu, by specifically providing the decoder, as taught by Hwang, for the purpose of providing a data driver having a reduced size, [0004].
Regarding claim 4, Ryu discloses further comprising:
a second latch (LT2_2) that provides a second color grayscale (green data G1) in the first voltage range (VDD1), (fig. 2, [0060 and 0077-0082]);
a second level shifter (LS_2) that converts the second color grayscale (G1) in the first voltage range (VDD1) into the second color grayscale (i.e. shifts a voltage level of the data from the latch LT2_1 and outputs data with a shifted increased voltage level) in the second voltage range (VDD2), (fig. 2, [0060 and 0083-0085]);
a second digital-to-analog converter (DAC_2) that provides a second gamma voltage (i.e. voltage Vk applied to DAC_2) of the second color grayscale based on the second voltage range (VDD2), (fig. 2, [0063 and 0086-0087]).
However, Ryu does not mention a second decoder.
In a similar field of endeavor, Hwang teaches
a second decoder (decoder 174 of a second channel CH) that generates a second gate control signal (SWS1-SWS2N-M) in the second voltage range (i.e. since the decoder 174 is in the DAC 170, hence it would be driven by voltage VDD2 as taught by Ryu) based on the second color grayscale (green data G1 taught by Ryu) in the second voltage range (voltage VDD2 taught by Ryu), (figs. 1 and 12, [0049 and 0070-0071]); and
a second digital-to-analog converter (DAC 172 of a second channel CH) that provides a second gamma voltage (TDGVS1-TDGVS2N-M) of the second color grayscale (green data G1 taught by Ryu) based on the second gate control signal (SWS1-SWS2N-M) in the second voltage range (voltage VDD taught by Ryu), (fig. 12, [0071]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Ryu, by specifically providing the decoder, as taught by Hwang, for the purpose of providing a data driver having a reduced size, [0004].
Regarding claim 6, Hwang discloses wherein the second decoder (decoder 174 of a second channel CH) receives the second color grayscale (PDAT) through N wires (i.e. one wire line for transmitting data PDAT to decoder 174), and outputs the second gate control signal (i.e. decoder 174 output signals SWS1 to SWS2N-M) through M wires (i.e. N-M lines for controlling switches SW1-SW2N-M), N is an integer greater than 0, and M is an integer greater than N, (fig. 12, [0071]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Ryu, by specifically providing the decoder, as taught by Hwang, for the purpose of providing a data driver having a reduced size, [0004].
Claims 11, 13-14, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (U.S. Patent Pub. No. 2024/0169881) in view of Ryu and in view of Hwang.
Regarding claim 11, Lee discloses a display device (fig. 1, [0053]), comprising:
a first sub-pixel (i.e. first color sub-pixel R) emitting light in a first color (red);
a second sub-pixel (i.e. second color sub-pixel G) emitting light in a second color (green);
a third sub-pixel (i.e. third color sub-pixel B) emitting light in a third color (blue), (fig. 4, [0083]); and
a data driver (400) that supplies a first gamma voltage (VGREF1) to the first sub-pixel (R) based on a first color grayscale (DATA_R), supplies a second gamma voltage (VGREF2) to the second sub-pixel (G) based on a second color grayscale (DATA_R), and supplies a third gamma voltage (VGREF3) to the third sub-pixel (B) based on a third color grayscale (DATA_R), (fig. 5, [0074, 0076 and 0088]),
wherein the data driver (400) includes:
a first latch (HL) that provides the first color grayscale (DATA_R), (fig. 5, [0075]);
a first level shifter (LS), (fig. 5, [0086]);
a first digital-to-analog converter (DAC) that provides the first gamma voltage (VGREF1) of the first color grayscale, (fig. 5, [0088]).
However, Lee does not mention the data driver includes a first latch that provides the first color grayscale in a first voltage range.
In a similar field of endeavor, Ryu teaches a data driver (100), (fig. 1), comprising:
a first latch (LT2_1) that provides the first color grayscale (red data R1) in a first voltage range (VDD1), (fig. 2, [0060 and 0077-0082]);
a first level shifter (LS_1) that converts the first color grayscale (R1) in the first voltage range (VDD1) into a first color grayscale (i.e. shifts a voltage level of the data from the latch LT2_1 and outputs data with a shifted increased voltage level) in a second voltage range (VDD2) greater than the first voltage range (i.e. VDD2 is higher than VDD1), (fig. 2 [0060 and 0083-0085]);
a first digital-to-analog converter (DAC_1) that provides a first gamma voltage (i.e. grayscale voltage Vk) of the first color grayscale (R1) based on the second voltage range (VDD2), (fig. 2, [0063 and 0086-0087]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lee, by specifically providing the first latch that provides the first color grayscale in the first voltage range, as taught by Ryu, for the purpose of reducing EMI, [0007].
However, Lee in view of Ryu does not mention a first decoder.
In a similar field of endeavor, Hwang teaches
a first decoder (174) that generates a first gate control signal (SWS1-SWS2N-M) in the second voltage range (i.e. since the decoder 174 is in the DAC 170, hence it would be driven by voltage VDD2 as taught by Ryu) based on the first color grayscale (R1 taught by Ryu) in the second voltage range (voltage VDD2 taught by Ryu), (figs. 1 and 12, [0049 and 0070-0071]); and
a first digital-to-analog converter (172) that provides the first gamma voltage (TDGVS1-TDGVS2N-M) of the first color grayscale (R1 taught by Ryu) based on the first gate control signal (SWS1-SWS2N-M) in the second voltage range (voltage VDD taught by Ryu), (fig. 12, [0071]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lee in view of Ryu, by specifically providing the decoder, as taught by Hwang, for the purpose of providing a data driver having a reduced size, [0004].
Regarding claim 13, Hwang discloses wherein the first decoder (174) receives the first color grayscale (PDAT) through N wires (i.e. one wire line for transmitting data PDAT to decoder 174), and outputs the first gate control signal (i.e. decoder 174 output signals SWS1 to SWS2N-M) through M wires (i.e. N-M lines for controlling switches SW1-SW2N-M), N is an integer greater than 0, and M is an integer greater than N, (fig. 12, [0071]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lee in view of Ryu, by specifically providing the decoder, as taught by Hwang, for the purpose of providing a data driver having a reduced size, [0004].
Regarding claim 14, Ryu discloses further comprising:
a second latch (LT2_2) that provides the second color grayscale (green data G1) in the first voltage range (VDD1), (fig. 2, [0060 and 0077-0082]);
a second level shifter (LS_2) that converts the second color grayscale (G1) in the first voltage range (VDD1) into the second color grayscale (i.e. shifts a voltage level of the data from the latch LT2_1 and outputs data with a shifted increased voltage level) in the second voltage range (VDD2), (fig. 2, [0060 and 0083-0085]);
a second digital-to-analog converter (DAC_2) that provides a second gamma voltage (i.e. voltage Vk applied to DAC_2) of the second color grayscale based on the second voltage range (VDD2), (fig. 2, [0063 and 0086-0087]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lee, by specifically providing the second latch that provides the second color grayscale in the first voltage range, as taught by Ryu, for the purpose of reducing EMI, [0007].
However, Lee in view of Ryu does not mention a second decoder.
In a similar field of endeavor, Hwang teaches
a second decoder (decoder 174 of a second channel CH) that generates a second gate control signal (SWS1-SWS2N-M) in the second voltage range (i.e. since the decoder 174 is in the DAC 170, hence it would be driven by voltage VDD2 as taught by Ryu) based on the second color grayscale (green data G1 taught by Ryu) in the second voltage range (voltage VDD2 taught by Ryu), (figs. 1 and 12, [0049 and 0070-0071]); and
a second digital-to-analog converter (DAC 172 of a second channel CH) that provides the second gamma voltage (TDGVS1-TDGVS2N-M) of the second color grayscale (green data G1 taught by Ryu) based on the second gate control signal (SWS1-SWS2N-M) in the second voltage range (voltage VDD taught by Ryu), (fig. 12, [0071]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lee in view of Ryu, by specifically providing the decoder, as taught by Hwang, for the purpose of providing a data driver having a reduced size, [0004].
Regarding claim 16, Hwang discloses wherein the second decoder (decoder 174 of a second channel CH) receives the second color grayscale (PDAT) through N wires (i.e. one wire line for transmitting data PDAT to decoder 174), and outputs the second gate control signal (i.e. decoder 174 output signals SWS1 to SWS2N-M) through M wires (i.e. N-M lines for controlling switches SW1-SW2N-M), N is an integer greater than 0, and M is an integer greater than N, (fig. 12, [0071]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lee in view of Ryu, by specifically providing the decoder, as taught by Hwang, for the purpose of providing a data driver having a reduced size, [0004].
Regarding claim 20, Lee discloses an electronic device (1000), (fig. 15, [0142]), comprising:
a processor (1010) that provides image data (IMG), (fig. 14, [0056 and 0142]); and
a display device that displays an image based on the image data (IMG), (fig. 1, [0053-0054]),
wherein the display device (fig. 1, [0053]), includes:
a first sub-pixel (i.e. first color sub-pixel R) emitting light in a first color (red);
a second sub-pixel (i.e. second color sub-pixel G) emitting light in a second color (green);
a third sub-pixel (i.e. third color sub-pixel B) emitting light in a third color (blue), (fig. 4, [0083]); and
a data driver (400) that supplies a first gamma voltage (first color gamma reference voltage VGREF1) to the first sub-pixel (R) based on a first color grayscale (DATA_R), supplies a second gamma voltage (VGREF2) to the second sub-pixel (G) based on a second color grayscale (DATA_R), and supplies a third gamma voltage (VGREF3) to the third sub-pixel (B) based on a third color grayscale (DATA_R), (fig. 5, [0074, 0076 and 0088]),
wherein the data driver (400) includes:
a first latch (HL) that provides the first color grayscale (DATA_R), (fig. 5, [0075]);
a first level shifter (LS), (fig. 5, [0086]);
a first digital-to-analog converter (DAC) that provides the first gamma voltage (VGREF1) of the first color grayscale, (fig. 5, [0088]).
However, Lee does not mention the data driver includes a first latch that provides the first color grayscale in a first voltage range.
In a similar field of endeavor, Ryu teaches a data driver (100), (fig. 1), comprising:
a first latch (LT2_1) that provides the first color grayscale (red data R1) in a first voltage range (VDD1), (fig. 2, [0060 and 0077-0082]);
a first level shifter (LS_1) that converts the first color grayscale (R1) in the first voltage range (VDD1) into a first color grayscale (i.e. shifts a voltage level of the data from the latch LT2_1 and outputs data with a shifted increased voltage level) in a second voltage range (VDD2) greater than the first voltage range (i.e. VDD2 is higher than VDD1), (fig. 2 [0060 and 0083-0085]);
a first digital-to-analog converter (DAC_1) that provides a first gamma voltage (i.e. grayscale voltage Vk) of the first color grayscale (R1) based on the second voltage range (VDD2), (fig. 2, [0063 and 0086-0087]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lee, by specifically providing the first latch that provides the first color grayscale in the first voltage range, as taught by Ryu, for the purpose of reducing EMI, [0007].
However, Lee in view of Ryu does not mention a first decoder.
In a similar field of endeavor, Hwang teaches
a first decoder (174) that generates a first gate control signal (SWS1-SWS2N-M) in the second voltage range (i.e. since the decoder 174 is in the DAC 170, hence it would be driven by voltage VDD2 as taught by Ryu) based on the first color grayscale (R1 taught by Ryu) in the second voltage range (voltage VDD2 taught by Ryu), (figs. 1 and 12, [0049 and 0070-0071]); and
a first digital-to-analog converter (172) that provides the first gamma voltage (TDGVS1-TDGVS2N-M) of the first color grayscale (R1 taught by Ryu) based on the first gate control signal (SWS1-SWS2N-M) in the second voltage range (voltage VDD taught by Ryu), (fig. 12, [0071]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lee in view of Ryu, by specifically providing the decoder, as taught by Hwang, for the purpose of providing a data driver having a reduced size, [0004].
Allowable Subject Matter
Claims 2, 5, 7-10, 12, 15 and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
Claim 2, Hsia (U.S. Patent No. 9,929,741) teaches the concept of a decoder 10 and a latch 11 implemented in a lower voltage domain in order to reduce power consumption and circuit areas, (fig. 1, col. 2, lines 23-26).
However, none of the prior art of record teaches alone or in combination the limitation “wherein an area of each of first transistors of the first latch is smaller than an area of each of second transistors of the first decoder, the first level shifter, and the first digital-to-analog converter.”
Claims 5, 12 and 15 are allowed for similar reason as mentioned above in claim 2.
Claim 7, Lee teaches wherein the second level shifter (LS2[1]) are disposed between the first latch (HL1[1]) and the first level shifter (LS1[1]), (fig. 12, [0134-0135]).
However, none of the prior art of record teaches alone or in combination the limitation “the second level shifter, the second decoder, and the second digital-to-analog converter are disposed between the first latch and the first level shifter.”
Claims 8-10 are dependent upon claim 7 and are allowed for the reason mentioned above in claim 7.
Claim 17 is allowed for similar reason as mentioned above in claim 7.
Claims 18-19 are dependent upon claim 17 and are allowed for the reason mentioned above in claim 17.
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/LONG D PHAM/ Primary Examiner, Art Unit 2623