DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 21-40 have been examined.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(a)-(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. The instant application claims priority to US Patent 12,288,066, which claims priority to U.S. Provisional Application 63/376,865, filed September 22, 2022.
Information Disclosure Statement
The Applicant's submission of the Information Disclosure Statements dated April 1, 2025, May 30, 2025 and June 18, 2025 is acknowledged by the Examiner and the cited references have been considered in the examination of the claims now pending. Copies of the PTOL-1449s initialed and dated by the Examiner are attached to the instant office action.
Examiner’s Note
Claim 30 is improperly ordered. As noted at MPEP § 608.01(n)(IV), “A claim which depends from a dependent claim should not be separated therefrom by any claim which does not also depend from said "dependent claim." In this case, dependent claim 30 depends from dependent claim 24 and is separated therefrom by claims 25-29, which do not.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21, 24-36, 38, and 40 are rejected on the ground of nonstatutory double patenting as being unpatentable over corresponding claims of U.S. Patent No. 12,288,066. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the reference patent anticipate those in the instant application..
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21, 22, 24-26, 28, 29, 31-33 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2018/0267775 by Gopal et al. (hereinafter referred to as “Gopal”) in view of US Publication No. 2010/0095091 by Asanaka (hereinafter referred to as “Asanaka”).
Regarding claims 21 and 32, taking claim 21 as representative, Gopal discloses:
a processor configured to implement an instruction set architecture, the processor comprising: a load/store circuit coupled to a first register file…, the load/store circuit configured to execute one or more ops decoded from individual instructions defined within the instruction set architecture, wherein the load/store circuit comprises (Gopal discloses, at Figure 1 and related description, a processor, which discloses being configured to implement an instruction set architecture. See, e.g., ¶ [0027]. Gopal also discloses, at Figure 1 and related description, the processor includes a load-store unit (LSU) configured to execute decode ops from individual instructions. See, e.g., ¶ [0028] et seq. Gopal also discloses, at Figure 1 and related description, the LSU is coupled to a register, i.e., a first register file. See, e.g., ¶ [0031].):
a memory execution circuit configured to execute memory access ops (Gopal discloses, at Figure 1 and related description, the LSU executes memory access ops, which discloses an execution circuit configured to do so. See, e.g., ¶ [0031].); and
…wherein the load/store circuit is configured to direct a given op to one of the memory execution circuit or the register transfer execution circuit (Gopal discloses, at Figure 1 and related description, the LSU executes memory access ops, which discloses directing a given op to the memory execution circuit).
Gopal does not explicitly disclose a second register file and a register transfer execution circuit configured to execute an op specifying a transfer of data from the first register file to the second register file and further specifying an additional operation to be performed using the data.
However, in the same field of endeavor (e.g., processing) Asanaka discloses:
a second register file (Asanaka discloses, at Figure 3 and related description, a first and second register file.); and
a register transfer execution circuit configured to execute an op specifying a transfer of data from the first register file to the second register file and further specifying an additional operation to be performed using the data (Asanaka discloses, at Figure 3 and related description, operand processing circuitry that executes an instruction that transfers data from one register file to another and converts the data from one format to another, i.e., performs an additional operation. See, e.g., ¶ [0075] et seq.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gopal to include the processing and register files used in Asanaka in order to improve performance by allowing parallel execution of instructions that use different types of data. See, e.g., Asanaka, ¶ [0047].
Regarding claim 22, Gopal, as modified, discloses the elements of claim 21, as discussed above. Gopal also discloses:
the processor is configured for storing … values in the first register file… (Gopal discloses, at ¶ [0031], storing values in a first register.).
Gopal does not explicitly disclose the aforementioned values are integers and floating-point values in the second register file.
However, in the same field of endeavor (e.g., processing) Asanaka discloses:
integer values and floating-point values in the second register file (Asanaka discloses, at Figure 3 and related description, integer and floating point register files.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gopal to include the processing and register files used in Asanaka in order to improve performance by allowing parallel execution of instructions that use different types of data. See, e.g., Asanaka, ¶ [0047].
Regarding claim 24, Gopal, as modified, discloses the elements of claim 21, as discussed above. Gopal also discloses:
the load/store circuit further comprises an issue port configured to receive the one or more ops for execution (Gopal discloses, at Figure 1 and related description, a load store unit the executes instructions, which discloses receiving the instructions through an issue port.).
Regarding claims 25 and 33, taking claim 25 as representative, Gopal, as modified, discloses the elements of claim 26, as discussed above. Gopal does not explicitly disclose the additional operation is an integer-to-floating-point conversion operation; and the register transfer execution circuit includes an integer-to-floating-point conversion circuit.
However, in the same field of endeavor (e.g., processing) Asanaka discloses:
the additional operation is an integer-to-floating-point conversion operation; and the register transfer execution circuit includes an integer-to-floating-point conversion circuit (Asanaka discloses, at Figure 3 and related description, operand processing circuitry that executes an instruction that transfers data from one register file to another and converts the data from integer to floating point. See, e.g., ¶ [0075] et seq.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gopal to include the processing and register files used in Asanaka in order to improve performance by allowing parallel execution of instructions that use different types of data. See, e.g., Asanaka, ¶ [0047].
Regarding claim 26, Gopal, as modified, discloses the elements of claim 25, as discussed above. Gopal does not explicitly disclose the processor includes an additional integer-to- floating point conversion circuit.
However, in the same field of endeavor (e.g., processing) Asanaka discloses an integer-to-floating point conversion circuit. It would have been obvious to include an additional such circuit because duplicating parts is a well-known way to improve performance by increasing parallelism and instruction throughput.
Regarding claim 28, Gopal, as modified, discloses the elements of claim 21, as discussed above. Gopal also discloses:
a decoder circuit coupled to the load/store circuit, wherein the decoder circuit is configured to: receive a fetched transfer instruction involving transfer of data… (Gopal discloses, at Figure 1 and related description, a decode unit coupled to a fetch unit configured to decode instructions, including a transfer instruction involving transfer of data.); and
decode the fetched transfer instruction into an op for execution… (Gopal discloses, at Figure 1 and related description, a decode unit, which discloses decoding fetched transfer instructions.).
Gopal does not explicitly disclose the aforementioned transfer is from the first register file to the second register file and is executed by the register transfer execution circuit.
However, in the same field of endeavor (e.g., processing) Asanaka discloses:
transferring between register files by a register transfer execution unit (Asanaka discloses, at Figure 3 and related description, operand processing circuitry that executes an instruction that transfers data from one register file to another.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gopal to include the processing and register files used in Asanaka in order to improve performance by allowing parallel execution of instructions that use different types of data. See, e.g., Asanaka, ¶ [0047].
Regarding claim 29, Gopal, as modified, discloses the elements of claim 21, as discussed above. Gopal also discloses:
Gopal does not explicitly disclose the first register file is not directly accessible by a second execution circuit coupled to the second register file.
However, in the same field of endeavor (e.g., processing) Asanaka discloses:
the first register file is not directly accessible by a second execution circuit coupled to the second register file (Asanaka discloses, at ¶ [0078], that FP numbers must first be converted before being stored in the integer register file, which discloses being not directly accessible.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gopal to include the processing and register files used in Asanaka in order to improve performance by allowing parallel execution of instructions that use different types of data. See, e.g., Asanaka, ¶ [0047].
Regarding claims 31 and 35, taking claim 31 as representative, Gopal, as modified, discloses the elements of claim 21, as discussed above. Gopal also discloses:
a dispatch circuit configured to issue to the load/store circuit the op specifying a transfer of data… (Gopal discloses, at Figure 1 and related description, instructions are dispatched by the decode unit to the LSU, which discloses a dispatch circuitr configured to do so.).
Gopal does not explicitly disclose the aforementioned transfer is from the first register file to the second register file and the aforementioned op further specifies an additional operation to be performed using the data.
However, in the same field of endeavor (e.g., processing) Asanaka discloses:
a register transfer execution circuit configured to execute an op specifying a transfer of data from the first register file to the second register file and further specifying an additional operation to be performed using the data (Asanaka discloses, at Figure 3 and related description, operand processing circuitry that executes an instruction that transfers data from one register file to another and converts the data from one format to another, i.e., performs an additional operation. See, e.g., ¶ [0075] et seq.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gopal to include the processing and register files used in Asanaka in order to improve performance by allowing parallel execution of instructions that use different types of data. See, e.g., Asanaka, ¶ [0047].
Claims 23, 27, and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Gopal in view of Asanaka in view of US Publication No. 2013/0073838 by Gschwind et al. (hereinafter referred to as “Gschwind”).
Regarding claim 23, Gopal, as modified, discloses the elements of claim 21, as discussed above. Gopal also discloses:
the processor is configured for storing …values in the first register file …(Gopal discloses, at ¶ [0031], storing values in a first register.).
Gopal does not explicitly disclose the aforementioned values are scalars and vector values in the second register file.
However, in the same field of endeavor (e.g., processing) Gschwind discloses:
scalar and vector register files (Gschwind discloses, at ¶ [0027], scalar register files, e.g., 114 and 116 and a vector register file, e.g., 118.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gopal to include the processing and register files used in Gschwind in order to improve performance by allowing vector processing in addition to scalar processing.
Regarding claims 27 and 34, taking claim 27 as representative, Gopal, as modified, discloses the elements of claim 21, as discussed above. Gopal does not explicitly disclose the additional operation is a duplication operation; and the register transfer execution circuit includes a duplication circuit configured to read a value from the first register file and copy the value to one or more vector elements stored in the second register file.
However, in the same field of endeavor (e.g., processing) Gschwind discloses:
the additional operation is a duplication operation; and the register transfer execution circuit includes a duplication circuit configured to read a value from the first register file and copy the value to one or more vector elements stored in the second register file. (Gschwind discloses, at Figure 10 and related description, duplicating a value read from one register to another, e.g., at 1006.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gopal to include the processing and register files used in Gschwind in order to improve performance by allowing vector processing in addition to scalar processing.
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Gopal in view of Asanaka in view of US Publication No. 2011/0035570 by Col et al. (hereinafter referred to as “Col”).
Regarding claim 30, Gopal, as modified, discloses the elements of claim 24, as discussed above. Gopal does not explicitly disclose the issue port comprises a reservation station.
However, in the same field of endeavor (e.g., processing) Col discloses:
reservation stations (Col discloses, at Figure 1 and related description, reservation stations.)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gopal to include the reservation stations disclosed by in Col in order to improve performance by enabling out of order execution.
Claims 36-38 are rejected under 35 U.S.C. 103 as being unpatentable over Gopal in view of Asanaka in view of Official notice.
Regarding claim 36, this claim corresponds to claim 21. Corresponding elements are disclosed as discussed above. Gopal does not explicitly disclose: one or more memory controllers; one or more peripheral components; …and a communication fabric configured to interconnect the one or more memory controllers, the one or more peripheral components and the processor.
The Examiner takes official notice that one or more memory controllers; one or more peripheral components; …and a communication fabric configured to interconnect the one or more memory controllers, the one or more peripheral components and the processor were notoriously well-known in the art prior to the effective filing date of the claimed invention. Such elements allow for processing at a practical speed and scale that would otherwise be impossible.
Regarding claim 37, this claim corresponds to claim 22. Corresponding elements are disclosed as discussed above.
Regarding claim 38, this claim corresponds to claim 25. Corresponding elements are disclosed as discussed above.
Claims 39 and 40 are rejected under 35 U.S.C. 103 as being unpatentable over Gopal in view of Asanaka in view of Official Notice
Regarding claim 39, this claim corresponds to claim 23. Corresponding elements are disclosed as discussed above.
Regarding claim 40, this claim corresponds to claim 27. Corresponding elements are disclosed as discussed above.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure.
US 20110264896 by Parks discloses register to register move plus another operation, a reservation station.
US 5805486 by Sharangpani discloses moving between integer and FP registers and converting.
US 10838729 by Al-Otoom discloses register to register-to-register move.
US 20090019262 by Tashiro discloses register to register move and load/store.
US 20190303155 by Eapen discloses LSU and vector permute units.
US 20190026173 by Stephens discloses LSU and vector permute units.
US 20150134935 by Blasco discloses separate int and FP register files and EXUs.
US 6754810 by Elliott discloses transfer and conversion between integer and FP register files.
US 6292888 by Nemirovsky discloses a register transfer unit.
US 20200042319 by Lloyd discloses LSU and vector scalar units, including permutation units.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/Primary Examiner, Art Unit 2183
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