Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Gui (US 20240420644).
Regarding claim 1 Gui teaches a driver comprising:
a first transistor (fig. 4A, 116) comprising a control electrode configured to receive a clock signal (fig. 4A, CLK1), a first electrode configured to receive an input signal (fig. 4A, GST), and a second electrode connected to a first node (fig. 4A, Q2);
a second transistor (fig. 4A, 118) comprising a control electrode connected to the first node (fig. 4A, Q2), a first electrode configured to receive a first voltage (fig. 4A, VGH), and a second electrode connected to a second node (fig. 4A, QB);
a third transistor (fig. 4A, 114) comprising a control electrode configured to receive a second voltage (fig. 4A, VGL), a first electrode connected to the first node (Q2), and a second electrode connected to a third node (fig. 4A, Q);
a fourth transistor (fig.4A, 120) comprising an NMOS transistor comprising a control electrode connected to the first node (Q2), and a first electrode connected to the second node (QB), and configured to have a gate-source voltage (fig. 4a, 121 from double gate is connected source and source has voltage of VDC) that is less than zero ([0047] voltage VDC can be equal to VGL, less than VGL, therefore VDC is less than zero);
a fifth transistor (fig.4A, 112) comprising a control electrode connected to the second node (fig.4A, QB), a first electrode configured to receive the first voltage (fig.4A, VGH), and a second electrode connected to an output node (fig.4A, OUT); and
a sixth transistor (fig.4A, 110) comprising a control electrode connected to the third node (fig.4A, Q), a first electrode connected to the output node (fig.4A, OUT), and a second electrode configured to receive the second voltage (fig.4A, VGL).
Regarding claim 2 Gui teaches further comprising a first capacitor (fig.4A, CQ) comprising a first electrode connected to the third node (fig.4A, Q), and a second electrode connected to the output node (fig.4A, OUT).
Regarding claim 3 Gui teaches further comprising a second capacitor (fig.4A, CB) comprising a first electrode configured to receive the first voltage (fig.4A, VGH), and a second electrode connected to the second node (fig.4A, QB), wherein the first voltage comprises a high-power voltage (VGH).
Regarding claim 4 Gui teaches wherein the first transistor, the second transistor, the third transistor, the fifth transistor, and the sixth transistor comprise PMOS transistors (fig. 4A, 116, 118, 114, 112, 110 are PMOS).
Regarding claim 6 Gui teaches wherein the fourth transistor (fig. 4A, 121) further comprises a second electrode configured to receive a third voltage (fig.4A, voltage at QB node), wherein the second voltage comprises a low power voltage (fig. 4, VGL), and wherein the third voltage comprises another low power voltage that is different from the second voltage (fig. 4A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gui (US 20240420644) in view of Shang (US 20210090484).
Regarding claim 5 Gui is silent on wherein the fourth transistor further comprises a second control electrode connected to the control electrode of the fourth transistor.
However, Shang teach wherein the fourth transistor further comprises a second control electrode connected to the control electrode of the fourth transistor ([0394] dual-gate transistor connected in parallel and the bottom gate of the parallel dual-gate transistor are arranged to be short-circuited with each other).
Therefore, it would have been obvious to one of the ordinary skilled in the art to combine Gui in light of Shang teaching so that it may include wherein the fourth transistor further comprises a second control electrode connected to the control electrode of the fourth transistor.
The motivation is to reduce leakage current.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gui (US 20240420644) in view of Seo (US 20210027683).
Regarding claim 19 Gui teaches a display apparatus (fig.2), comprising: a display panel comprising a pixel; a gate driver configured to output a gate signal to the pixel; a data driver configured to output a data voltage to the pixel (fig.2);
at least one stage (fig.5) comprising:
a first transistor (fig. 4A, 116) comprising a control electrode configured to receive a clock signal (fig. 4A, CLK1), a first electrode configured to receive an input signal (fig. 4A, GST), and a second electrode connected to a first node (fig. 4A, Q2);
a second transistor (fig. 4A, 118) comprising a control electrode connected to the first node (fig. 4A, Q2), a first electrode configured to receive a first voltage (fig. 4A, VGH), and a second electrode connected to a second node (fig. 4A, QB);
a third transistor (fig. 4A, 114) comprising a control electrode configured to receive a second voltage (fig. 4A, VGL), a first electrode connected to the first node (Q2), and a second electrode connected to a third node (fig. 4A, Q);
a fourth transistor (fig.4A, 120) comprising an NMOS transistor comprising a control electrode connected to the first node (Q2), and a first electrode connected to the second node (QB), and configured to have a gate-source voltage (fig. 4a, 121 from double gate is connected source and source has voltage of VDC) that is less than zero ([0047] voltage VDC can be equal to VGL, less than VGL, therefore VDC is less than zero);
a fifth transistor (fig.4A, 112) comprising a control electrode connected to the second node (fig.4A, QB), a first electrode configured to receive the first voltage (fig.4A, VGH), and a second electrode connected to an output node (fig.4A, OUT); and
a sixth transistor (fig.4A, 110) comprising a control electrode connected to the third node (fig.4A, Q), a first electrode connected to the output node (fig.4A, OUT), and a second electrode configured to receive the second voltage (fig.4A, VGL).
Gui is silent on an emission driver configured to output an emission signal to the pixel.
However, Seo teaches an emission driver configured to output an emission signal to the pixel (fig.3 [0088]).
Therefore, it would have been obvious to one of the ordinary skilled in the art to combine Gui in light of Seo teaching so that it may include an emission driver configured to output an emission signal to the pixel.
The motivation is to provide a method of driving the display apparatus.
Regarding claim 20 Gui in view of Seo teaches an electronic (fig.1) apparatus, comprising:
a display panel comprising a pixel (fig.2);
a gate driver (fig.2, gate driver circuitry 34,) configured to output a gate signal to the pixel (fig.2, pixels 22);
a data driver (fig.2, 30) configured to output a data voltage to the pixel;
a first transistor (fig. 4A, 116) comprising a control electrode configured to receive a clock signal (fig. 4A, CLK1), a first electrode configured to receive an input signal (fig. 4A, GST), and a second electrode connected to a first node (fig. 4A, Q2);
a second transistor (fig. 4A, 118) comprising a control electrode connected to the first node (fig. 4A, Q2), a first electrode configured to receive a first voltage (fig. 4A, VGH), and a second electrode connected to a second node (fig. 4A, QB);
a third transistor (fig. 4A, 114) comprising a control electrode configured to receive a second voltage (fig. 4A, VGL), a first electrode connected to the first node (Q2), and a second electrode connected to a third node (fig. 4A, Q);
a fourth transistor (fig.4A, 120) comprising an NMOS transistor comprising a control electrode connected to the first node (Q2), and a first electrode connected to the second node (QB), and configured to have a gate-source voltage (fig. 4a, 121 from double gate is connected source and source has voltage of VDC) that is less than zero ([0047] voltage VDC can be equal to VGL, less than VGL, therefore VDC is less than zero);
a fifth transistor (fig.4A, 112) comprising a control electrode connected to the second node (fig.4A, QB), a first electrode configured to receive the first voltage (fig.4A, VGH), and a second electrode connected to an output node (fig.4A, OUT); and
a sixth transistor (fig.4A, 110) comprising a control electrode connected to the third node (fig.4A, Q), a first electrode connected to the output node (fig.4A, OUT), and a second electrode configured to receive the second voltage (fig.4A, VGL).
Gui is silent on an emission driver configured to output an emission signal to the pixel; a driving controller configured to control the gate driver, the data driver, and the emission driver; and a processor configured to output image data and a control signal to the driving controller.
However, Seo teaches an emission driver configured to output an emission signal to the pixel (fig. 3, [0088]);
a driving controller (fig.3, 200) configured to control the gate driver, the data driver, and the emission driver; and a processor ([0252]) configured to output image data and a control signal to the driving controller (fig.3, 200).
Therefore, it would have been obvious to one of the ordinary skilled in the art to combine Gui in light of Seo teaching so that it may include an emission driver configured to output an emission signal to the pixel; a driving controller configured to control the gate driver, the data driver, and the emission driver; and a processor configured to output image data and a control signal to the driving controller.
The motivation is to provide a method of driving the display apparatus.
Allowable Subject Matter
Claims 7-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
EBISUNO US 20150091444
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TOWFIQ ELAHI whose telephone number is (571)270-1687. The examiner can normally be reached M-F: 10AM-3PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Boddie can be reached at (571)272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TOWFIQ ELAHI/Primary Examiner, Art Unit 2625
Prosecution Insights