DETAILED ACTION
This Final action is in response to an amendment filed 6/18/2026. Currently claims 1-5 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto in US 2020/0118506 (hereinafter Yamamoto) in view of Yamaguchi et al. in US 2015/0022770 (hereinafter Yamaguchi) and Miyake in US 2016/0329392 (hereinafter Miyake).
Regarding claim 1, Yamamoto disclose a display substrate (Yamamoto’s par. 27) comprising:
a plurality of first wires extending in a first direction (Yamamoto’s Fig. 1 and par. 50: see GL);
a plurality of second wires extending in a second direction intersecting the first direction (Yamamoto’s Fig. 1 and par. 50: see SL);
a plurality of first thin-film transistors (Yamamoto’s Fig. 1 and par. 51: TFT Pt), each first thin-film transistor connected to any of the plurality of first wires and any of the plurality of second wires (Yamamoto’s Fig. 1 and par. 51: TFT Pt connected to GL and SL);
a plurality of pixel electrodes arranged in a matrix in the first direction and the second direction (Yamamoto’s Fig. 1 and par. 51: see PE), each pixel electrode connected to a corresponding one of the plurality of first thin-film transistors (Yamamoto’s Fig. 1 and par. 51: see PE connected to Pt in pixel PIX matrix);
a driver (Yamamoto’s Fig. 1: see SD) that supplies image signals (Yamamoto’s par. 59: video signal) to the plurality of second wires (Yamamoto’s Fig. 1 and par. 59: SL);
a plurality of second thin-film transistors (Yamamoto’s Figs. 1-2 and par. 61: see Ta-Tc) forming a demultiplexer circuit (Yamamoto’s Figs. 1-2 and par. 54: DMX) that distributes, to the plurality of second wires (Yamamoto’s Figs. 1-2: SL), the image signals supplied by the driver (Yamamoto’s Figs. 1-2 and par. 58-59: see DMX between SD and SL); and
wherein each of the first thin-film transistors (Yamamoto’s Figs. 1, 18 and par. 163: see Pt/130) includes:
a first gate electrode (Yamamoto’s Figs. 18 and par. 165: see 103) connected to a corresponding one of the first wires (Yamamoto’s Fig. 18a: see GL), and
a first semiconductor component placed opposite the first gate electrode across a first insulating film (Yamamoto’s Fig. 18b and par. 165: 107 placed opposite 103 across 5), and
each of the second thin-film transistors (Yamamoto’s Figs. 2, 4: see Ta-Tc/10) includes:
a second gate electrode (Yamamoto’s Fig. 4 and par. 82: see 3);
a second semiconductor component placed opposite the second gate electrode across the first insulating film (Yamamoto’s Fig. 4 and par. 82: see 7s opposite 3 across 5), and
a third gate electrode placed above a portion of the second semiconductor component that faces away from the second gate electrode (Yamamoto’s Fig. 4 and par. 84: see 14 at top side of 7 facing away from 3) and placed opposite the second semiconductor component across a second insulating film (Yamamoto’s Fig. 4 and par. 84: see 11).
Yamamoto fails to disclose a protective circuit provided between the driver and the demultiplexer circuit, or the second gate electrode having a gate length that is smaller than a gate length of the first gate electrode.
However, in the same field of endeavor of demultiplexers for display panels, Yamaguchi discloses a protective circuit provided between the driver and the demultiplexer circuit (Yamaguchi’s Fig. 12 and par. 78: see protection circuit 9e located between the driver IC [connected at bottom of lines 8] and demultiplexer 3; the driver IC is located on region M in Fig. 11 per par. 80).
Therefore, it would have been obvious to one of ordinary skill in the art, for Yamamoto’s display to include a protective circuit (as described by Yamaguchi’s Fig. 12 and par. 78), in order to obtain the benefit of protecting the demultiplexer (Yamaguchi’s par. 94)
Still, Yamamoto fails to disclose the second gate electrode having a gate length that is smaller than a gate length of the first gate electrode.
Nevertheless, in the same field of endeavor of transistors for display panels, Miyake disclose that the channel length of a double-gated transistor is smaller than the channel length of a single-gated transistor (Miyake’s Figs. 27 and par. 227: see channel length La2 of double-gated transistor TA1 which is smaller than channel length Lb2 of single-gated transistor TB1).
Thus, it would also have been obvious to one of ordinary skill in the art, that Yamamoto’s double-gated second transistor (Yamamoto’s Fig. 4: Ta-Tc with second gate electrode 3 which upon combination has a gate length La2 per Mikaye’s Fig. 27B and par. 227) have a gate length smaller than the single-gated transistor (Yamamoto’s Fig. 18b: transistor 130 with first gate electrode 103 which upon combination has a gate length Lb1 per Mikaye’s Fig. 27C and par. 227), in order to obtain the predictable result of known characteristics of double-gate transistor vs. single-gate transistor (Mikaye’s Figs 27 and par. 227), and the benefit of decreasing the area occupied by the double-gated transistor (Miyake’s par. 136).
By doing such combination, Yamamoto in view of Yamaguchi and Miyake disclose:
a protective circuit (Yamamoto’s Fig. 1 includes a protection circuit 9e between SD and DMX per Yamaguchi’s Fig. 12 and par. 78) provided between the driver (Yamamoto’s Fig. 1: see SD equivalent to the driver IC mounted at the bottom side of lines 8 on region M in Yamaguchi’s Figs. 11-12 per par. 80) and the demultiplexer circuit ((Yamamoto’s Fig. 1: see DMX equivalent to the demux 3 in Yamaguchi’s Fig. 12 per par. 78);
the second gate electrode (Yamamoto’s Fig. 4: see 3 [part of double-gated TFT 10] and equivalent to GE3 in Miyake’s Fig. 27C per par. 227) having a gate length that is smaller than a gate length of the first gate electrode (Yamamoto’s Fig. 18: see 103 [part of single-gated TFT 130] and equivalent to GE2 in Miyake’s Fig. 27B per par. 227, where La2 is smaller than Lb1).
Regarding claim 2, Yamamoto in view of Yamaguchi and Miyake disclose further comprising a transparent conductive film (Yamamoto’s Figs. 4-5, 18 and par. 163: see common electrode CE shown as 15 on top of insulation layer 12) placed above the second insulating film (Yamamoto’s Figs. 4, 18: see top side of insulator 11) across which the third gate electrode is placed (Yamamoto’s Fig. 4: see gate 14), wherein the third gate electrode (Yamamoto’s Fig. 4: see gate 14) is formed by a material that is identical to that of the transparent conductive film (Yamamoto’s par. 90: gate 14 formed using same transparent conductive film than common electrode CE).
Regarding claim 3, Yamamoto fails to disclose position detection electrodes or position detection wires. However, Miyake does disclose a touch panel on the top side of a display panel (Miyake’s Fig. 43B and par. 465) with position detection electrodes and position detection wires (Miyake’s Fig. 43B and par. 467) that detect capacitive touch by a finger (Miyake’s par. 468-471), and where the position detection wires are formed by the same material than common electrodes (Miyake’s par. 477).
Therefore, it would also have been obvious to one of ordinary skill in the art, that Yamamoto includes a touchpanel as described by Miyake, in order to obtain the benefit of a touch sensor as an input device (Miyake’s par. 463).
By doing such combination, Yamamoto in view of Yamaguchi and Miyake disclose further comprising:
a position detection electrode (Miyake’s Fig. 43B and par. 472: see 2591/2592), formed by a transparent conductive film (Miyake’s par. 477), that forms a capacitance with a position input body that performs position input (Miyake’s par. 468-470, 533: capacitive sensor senses finger for input detection); and
a position detection wire (Miyake’s Fig. 43B and par. 467: see 2598), connected to the position detection electrode (Miyake’s Fig. 43B and par. 467, 472), through which a position detection signal is transmitted (Miyake’s par. 467: from 2595 to terminal and FPC 2509, and are driver per par. 469),
wherein the position detection wire (Miyake’s Fig. 43B: see 2598) is placed above the second insulating film (Miyake’s Figs. 43B: see wires 2598 on top side of display panel 2501, where display panel 2501 upon combination includes the second insulating film 11 of Yamamoto’s Figs. 4, 18) across which the third gate electrode is placed (Yamamoto’s Fig. 4: third gate 14 is also at top side of second insulating film 11), and is formed by a material that is identical to that of the third gate electrode (Yamamoto’s par. 90: gate 14 formed using same transparent conductive film than common electrode CE, and Miyake’s par. 477: the common electrode is formed by the same material than the wiring 2598).
Regarding claim 5, Yamamoto in view of Yamaguchi and Miyake disclose a display device (Yamamoto’s par. 49) comprising:
the display substrate according to claim 1 (as explained above, also see Fig. 1 per par. 51: substrate 1000); and
a counter substrate placed opposite the display substrate (Yamamoto’s par. 51: counter substrate).
Allowable Subject Matter
Claim 4 is allowed. The following is a statement of reasons for allowance:
Claim 4 includes previously indicated as allowable subject matter and was amended to include ALL limitations of interceding limitations.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. In specific, the office agrees that Yamamoto in view of Miyake fail to disclose the added protection circuit; however, a new reference to Yamaguchi has been included addressing this limitation. Please see above rejection for further details.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/LILIANA CERULLO/Primary Examiner, Art Unit 2621
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