DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Display device and substrate with demultiplexer circuit with double-gate transistors”.
Claim Objections
Claim 1 is objected to because of the following informalities: Claim 1 line 23 reads “first electrode across a first insulating film, and” but should read “first gate electrode…” for consistency throughout the claim. Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“signal supply unit” in claim 1, which maps to a driver composed of an LSI chip having a driving circuit inside per par. 14, 16.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto in US 2020/0118506 (hereinafter Yamamoto) in view of Miyake in US 2016/0329392 (hereinafter Miyake).
Regarding claim 1, Yamamoto disclose a display substrate (Yamamoto’s par. 27) comprising:
a plurality of first wires extending in a first direction (Yamamoto’s Fig. 1 and par. 50: see GL);
a plurality of second wires extending in a second direction intersecting the first direction (Yamamoto’s Fig. 1 and par. 50: see SL);
a plurality of first thin-film transistors each connected to any of the plurality of first wires and any of the plurality of second wires (Yamamoto’s Fig. 1 and par. 51: TFT Pt connected to GL and SL);
a plurality of pixel electrodes arranged in a matrix in the first direction and the second direction and each connected to a corresponding one of the plurality of first thin-film transistors (Yamamoto’s Fig. 1 and par. 51: see PE connected to Pt in pixel PIX matrix);
a signal supply unit (112f: driver circuit)(Yamamoto’s Fig. 1: see SD) that supplies image signals (Yamamoto’s par. 59: video signal) to the plurality of second wires (Yamamoto’s Fig. 1 and par. 59: SL); and
a plurality of second thin-film transistors (Yamamoto’s Figs. 1-2 and par. 61: see Ta-Tc) constituting a demultiplexer circuit (Yamamoto’s Figs. 1-2 and par. 54: DMX) that distributes, to the plurality of second wires (Yamamoto’s Figs. 1-2: SL), the image signals supplied from the signal supply unit (Yamamoto’s Figs. 1-2 and par. 58-59: see DMX between SD and SL),
wherein each of the first thin-film transistors (Yamamoto’s Figs. 1, 18 and par. 163: see Pt/130) includes
a first gate electrode (Yamamoto’s Figs. 18 and par. 165: see 103) connected to a corresponding one of the first wires (Yamamoto’s Fig. 18a: see GL), and
a first semiconductor component placed opposite the first gate electrode across a first insulating film (Yamamoto’s Fig. 18b and par. 165: 107 placed opposite 103 across 5), and
each of the second thin-film transistors (Yamamoto’s Figs. 2, 4: see Ta-Tc/10) includes
a second gate electrode (Yamamoto’s Fig. 4 and par. 82: see 3);
a second semiconductor component placed opposite the second gate electrode across the first insulating film (Yamamoto’s Fig. 4 and par. 82: see 7s opposite 3 across 5), and
a third gate electrode placed at a side of the second semiconductor component that faces away from the second gate electrode (Yamamoto’s Fig. 4 and par. 84: see 14 at top side of 7 facing away from 3) and placed opposite the second semiconductor component across a second insulating film (Yamamoto’s Fig. 4 and par. 84: see 11).
Yamamoto fails to disclose the second gate electrode having a gate length that is smaller than a gate length of the first gate electrode.
However, in the same field of endeavor of transistors for display panels, Miyake disclose that the channel length of a double-gated transistor is smaller than the channel length of a single-gated transistor (Miyake’s Figs. 27 and par. 227: see channel length La2 of double-gated transistor TA1 which is smaller than channel length Lb2 of single-gated transistor TB1).
Therefore, it would have been obvious to one of ordinary skill in the art, that Yamamoto’s double-gated second transistor (Yamamoto’s Fig. 4: Ta-Tc with second gate electrode 3 which upon combination has a gate length La2 per Mikaye’s Fig. 27B and par. 227) have a gate length smaller than the single-gated transistor (Yamamoto’s Fig. 18b: transistor 130 with first gate electrode 103 which upon combination has a gate length Lb1 per Mikaye’s Fig. 27C and par. 227), in order to obtain the predictable result of known characteristics of double-gate transistor vs. single-gate transistor (Mikaye’s Figs 27 and par. 227), and the benefit of decreasing the area occupied by the double-gated transistor (Miyake’s par. 136).
By doing such combination, Yamamoto in view of Miyake disclose:
the second gate electrode (Yamamoto’s Fig. 4: see 3 [part of double-gated TFT 10] and equivalent to GE3 in Miyake’s Fig. 27C per par. 227) having a gate length that is smaller than a gate length of the first gate electrode (Yamamoto’s Fig. 18: see 103 [part of single-gated TFT 130] and equivalent to GE2 in Miyake’s Fig. 27B per par. 227, where La2 is smaller than Lb1).
Regarding claim 2, Yamamoto in view of Miyake disclose further comprising a transparent conductive film (Yamamoto’s Figs. 4-5, 18 and par. 163: see common electrode CE shown as 15 on top of insulation layer 12) placed at a side of the second insulating film (Yamamoto’s Figs. 4, 18: see top side of insulator 11) at which the third gate electrode is placed (Yamamoto’s Fig. 4: see gate 14), wherein the third gate electrode (Yamamoto’s Fig. 4: see gate 14) is constituted by a material that is identical to that of the transparent conductive film (Yamamoto’s par. 90: gate 14 formed using same transparent conductive film than common electrode CE).
Regarding claim 3, Yamamoto fails to disclose position detection electrodes or position detection wires. However, Miyake does disclose a touch panel on the top side of a display panel (Miyake’s Fig. 43B and par. 465) with position detection electrodes and position detection wires (Miyake’s Fig. 43B and par. 467) that detect capacitive touch by a finger (Miyake’s par. 468-471), and where the position detection wires are formed by the same material than common electrodes (Miyake’s par. 477).
Therefore, it would also have been obvious to one of ordinary skill in the art, that Yamamoto includes a touchpanel as described by Miyake, in order to obtain the benefit of a touch sensor as an input device (Miyake’s par. 463).
By doing such combination, Yamamoto in view of Miyake disclose further comprising:
a position detection electrode (Miyake’s Fig. 43B and par. 472: see 2591/2592), constituted by a transparent conductive film (Miyake’s par. 477), that forms a capacitance with a position input body that performs position input (Miyake’s par. 468-470, 533: capacitive sensor senses finger for input detection); and
a position detection wire (Miyake’s Fig. 43B and par. 467: see 2598), connected to the position detection electrode (Miyake’s Fig. 43B and par. 467, 472), through which a position detection signal is transmitted (Miyake’s par. 467: from 2595 to terminal and FPC 2509, and are driver per par. 469),
wherein the position detection wire (Miyake’s Fig. 43B: see 2598) is placed at a side of the second insulating film (Miyake’s Figs. 43B: see wires 2598 on top side of display panel 2501, where display panel 2501 upon combination includes the second insulating film 11 of Yamamoto’s Figs. 4, 18) at which the third gate electrode is placed (Yamamoto’s Fig. 4: third gate 14 is also at top side of second insulating film 11), and is constituted by a material that is identical to that of the third gate electrode (Yamamoto’s par. 90: gate 14 formed using same transparent conductive film than common electrode CE, and Miyake’s par. 477: the common electrode is formed by the same material than the wiring 2598).
Regarding claim 5, Yamamoto in view of Miyake disclose a display device (Yamamoto’s par. 49) comprising:
the display substrate according to claim 1 (as explained above, also see Fig. 1 per par. 51: substrate 1000); and
a counter substrate placed opposite the display substrate (Yamamoto’s par. 51: counter substrate).
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding independent claim 4: the prior art fails to disclose the limitations as described in addition to ALL limitations of claim 1.
Yamamoto does not disclose a position detection electrode or a position detection wire. Furthermore, the gate electrode wire connected to the third gate electrode is located at the bottom side of the second insulating film (Yamamoto’s Figs. 3-4: wire 8/B connected to gate 14/BG and below insulator 11).
Miyake disclose a position detection electrode and a position detection wire on top of the display panel that includes the insulating film for the transistors (Miyake’s Figs. 43-44), but Miyake fails to disclose or make obvious a gate electrode wire is placed at a side of the second insulating film at which the position detection wire is placed (top side of insulating film in the display panel), this is partly because Miyake’s back gate electrode [equivalent to the claim third electrode] is connected to the gate below the insulating films (Figs. 28).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wang et al. in US 2024/0355832, Lai et al. in US 2022/0208797 and Umezaki et al. in US 2018/0226040 all directed to the transistors in a demux or drivers vs. pixel transistors.
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/LILIANA CERULLO/ Primary Examiner, Art Unit 2621