DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Miscellaneous
The Applicant has cancelled claim 1 and added new claims 2-21; therefore, only claims 2-21 remain for this Office Action.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 12,287,712. Although the claims at issue are not identical, they are not patentably distinct from each other because they contain substantially similar subject matter (see chart below).
Claims 2-13 and 15-20 are also rejected as being dependent on claims 1, 14 and may also correspond to claims 2-12 and 14-19 of the ‘217 patent.
Instant Application
US Patent No. 12,287,716
2. A memory device comprising: a base memory die having: a bottom base-die face including first and second bottom base-die contacts; a top base-die face including first and second top base-die contacts; a switchable connection between the first bottom base-die contact and the first top base-die contact; base-die drive circuitry having a drive-circuitry input communicatively coupled to the second top base-die contact and a drive-circuity output coupled to the first bottom base-die contact; and a base-die memory core coupled to the drive-circuitry input; and an alternate memory die affixed to the base memory die, the alternate memory die having: a bottom alternate-die face including a first bottom alternate-die contact connected to the first top base-die contact and a second bottom alternate-die contact connected to the second top base-die contact; and an alternate-die memory core coupled to the drive-circuitry input via the second bottom alternate-die contact and the second top base-die contact.
1. A memory device comprising: a base memory die having: a bottom base-die face including a bottom base-die (first) primary data contact; a top base-die face extending through the three-dimensional memory device and including a top base-die primary data contact and a top base-die (second) secondary data contact; a switchable connection between the bottom base-die (first) primary data contact and the top base-die (first) primary data contact; base-die drive circuitry having a drive-circuitry input coupled to the top base-die (second) secondary data contact and a drive-circuitry output coupled to the bottom base-die (first) primary data contact; and a base-die memory core coupled to the drive-circuitry input; and an alternate memory die affixed atop the base memory die, the alternate memory die having: a bottom alternate-die face extending through the three-dimensional memory device adjacent the top base-die face, the bottom alternate-die face including a bottom alternate-die primary data contact in contact with the top base-die (first) primary data contact and a bottom alternate-die (second) secondary data contact in contact with the top base-die (second) secondary data contact; and an alternate-die memory core coupled to the drive-circuitry input via the bottom alternate-die (second) secondary data contact and the top base-die (second) secondary data contact.
14. A memory module comprising: a printed-circuit board; a base memory die including: a bottom base-die face including a bottom base-die contact electrically connected to the printed-circuit board; a top base-die face including a first top base-die contact and a second top base-die contact; a switchable connection between the bottom base-die contact and the first top base-die contact; base-die drive circuitry between the second top base-die contact and the bottom base-die contact; and a base-die memory core coupled to the base-die drive circuitry; and an alternate memory die including: a bottom alternate-die face including a first bottom alternate-die contact connected to the first top base-die contact and a second bottom alternate-die contact connected to the second top base-die contact; and an alternate-die memory core coupled to the base-die drive circuitry the second bottom alternate-die contact and the second top base-die contact.
13. A memory module comprising: a printed-circuit board; a base memory die including: a bottom base-die face including a bottom base-die (first) primary data contact electrically connected to the printed-circuit board; a top base-die face including a top base-die primary data contact and a top base-die (second) secondary data contact; a switchable connection between the bottom base-die (first) primary data contact and the top base-die (first) primary data contact; base-die drive circuitry having a drive-circuitry input coupled to the top base-die (second) secondary data contact and a drive-circuitry output coupled to the bottom base-die (first) primary data contact; and a base-die memory core coupled to the drive-circuitry input; and an alternate memory die affixed atop the base memory die, the alternate memory die including: a bottom alternate-die face adjacent the top base-die face, the bottom alternate-die face including a bottom alternate-die (first) primary data contact in contact with the top base-die (first) primary data contact and a bottom alternate-die (second) secondary data contact in contact with the top base-die (second) secondary data contact; and an alternate-die memory core coupled to the drive-circuitry input via the bottom alternate-die secondary data contact and the top base-die (second) secondary data contact.
Allowable Subject Matter
Claim 21 is allowed. The following is an examiner’s statement of reasons for allowance:
In regards to claim 21, the closest available and relevant prior art of US 2018/0095127 to Pappu et al. discloses of a majority of the claimed method subject matter, however, Pappu does not disclose of nor render obvious the method further comprising a switchable connection between the first bottom base-die contact and the first top base-die contact; and bonding an alternate memory die to the base memory die, the alternate memory die having: a bottom alternate-die face including a first bottom alternate-die contact connected to the first top base-die contact and a second bottom alternate-die contact connected to the second top base-die contact; and an alternate-die memory core coupled to the drive-circuitry input via the second bottom alternate-die contact and the second top base-die contact, nor would it have been obvious to one of ordinary skill in the art to do so.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason M Crawford whose telephone number is (571)272-6004. The examiner can normally be reached Mon-Fri 6:30am-3:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON M CRAWFORD/Primary Examiner, Art Unit 2845
Prosecution Insights