DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 19/098,829, filed on April 2, 2025.
Oath/Declaration
Oath/Declaration as filed on April 2, 2025 is noted by the Examiner.
Claim Objections
Claim 11 is objected to because of the following informalities:
Claim 11 is missing a comma in eighteenth line of the claim. The Examiner suggests adding a comma between the words “node and” in the eighteenth line of the claim because as presently drafted it is not exactly clear how the fourth transistor is connected. Accordingly, any claim(s) dependent on claim 11 are objected to based on same above reasoning.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 6, 8, 10-12, 16-17, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al., U.S. Patent Application Publication 2024/0071305 A1 (hereinafter Kim I).
Regarding claim 1, Kim I teaches a pixel comprising: a first transistor having a first electrode connected to a first power line, a gate electrode connected to a first node, and a second electrode connected to a second node; a light emitting element connected between the second node and a second power line (PXa, T1, ELVDD, N1, N2, OLED, ELVSS FIGS. 2-3, paragraph[0095] of Kim I teaches referring to FIG. 3, the pixel PXa may include an organic light emitting diode OLED as a display element and a pixel circuit PC connected to the organic light emitting diode OLED; the pixel circuit PC may include first to sixth transistors T1 to T6 and first and second capacitors C1 and C2; the first transistor T1 may be a driving transistor outputting a driving current corresponding to a data signal, and the second to sixth transistors T2 to T6 may be switching transistors configured to transmit signals; a first terminal (first electrode) of each of the first to sixth transistors T1 to T6 may be a source or a drain, and a second terminal (second electrode) may be a terminal different from the first terminal; for example, when the first terminal is a drain, the second terminal may be a source; and a node to which a first gate of the first transistor T1 is connected may be defined as a first node N1, and a node to which a second terminal of the first transistor T1 is connected may be defined as a second node N2, and See also at least paragraphs[0080]-[0094], and [0096]-[0105] of Kim I (i.e., Kim I teaches a pixel having a first transistor that has a first terminal connected to a first driving voltage, a first gate connected to a first node, a second terminal connected to a second node, and an organic light emitting diode (OLED) connected between the second node a second driving voltage));
a second transistor connected between a data line and the first node and having a gate electrode connected to a first scan line (T2, DL, GWL, GL FIGS. 2-3, paragraph[0098] of Kim I teaches the second transistor T2 may be connected between the first gate of the first transistor T1 and the data line DL; the second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1; and the second transistor T2 may be turned on by the first gate signal GW received through the first gate line GWL to electrically connect the data line DL with the first node N1 and transmit the data signal Vdata received through the data line DL to the first node N1, and See also at least paragraphs[0080]-[0097], and [0099]-[0105] of Kim I (i.e., Kim I teaches a second transistor that is connected between a data line and the first node, wherein the second transistor has a first gate line connected to a first gate signal via a corresponding gate line));
a third transistor connected between the second node and a lead-out line and having a gate electrode connected to a second scan line (T6, VL2, GBL, GL FIGS. 2-3, paragraph[0102] of Kim I teaches the sixth transistor T6 may be connected between the first transistor T1 and the second initialization voltage line VL2; the sixth transistor T6 may include a gate connected to the fourth gate line GBL, a first terminal connected to the second node N2, and a second terminal connected to the second initialization voltage line VL2; and the sixth transistor T6 may be turned on by the fourth gate signal GB received through the fourth gate line GBL to transmit the second initialization voltage Vaint received through the second initialization voltage line VL2 to the second node N2, and See also at least paragraphs[0080]-[0101], and [0103]-[0105] of Kim I (i.e., Kim I teaches a sixth transistor that is connected between the second node and second initialization voltage line, wherein the sixth transistor has a fourth gate line connected to a fourth gate signal via a corresponding gate line)); and
a fourth transistor having a first electrode connected to the first node or the second node, a second electrode connected to the lead-out line or a third power line, and a gate electrode connected to a third scan line (T4, T3; VL1, VRL FIGS. 2-3, paragraphs[0099]-[0100] of Kim I teaches the third transistor T3 may be connected between the first gate of the first transistor T1 and the reference voltage line VRL; the third transistor T3 may include a gate connected to the third gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VRL; and the third transistor T3 may be turned on by the third gate signal GR received through the third gate line GRL to transmit the reference voltage Vref received through the reference voltage line VRL to the first node N1; the fourth transistor T4 may be connected between the first transistor T1 and the first initialization voltage line VL1; the fourth transistor T4 may include a gate connected to the second gate line GIL, a first terminal connected to the second node N2, and a second terminal connected to the first initialization voltage line VL1; and the fourth transistor T4 may be turned on by the second gate signal GI received through the second gate line GIL to transmit the first initialization voltage Vint received through the first initialization voltage line VL1 to the second node N2, and See also at least paragraphs[0080]-[0098], and [0101]-[0105] of Kim I (i.e., Kim I teaches at least the following: a fourth transistor that has a first terminal connected to the second node, a second terminal connected to a first initialization voltage via a first initialization voltage line, and a second gate line connected to a second gate signal via a corresponding gate line; or even a third transistor having a second terminal connected to the first node, a first terminal connected to a reference voltage via a reference voltage line, and a third gate line connected to a third gate signal via a corresponding gate line)).
Regarding claim 2, Kim I teaches the pixel of claim 1, wherein a voltage of a first initialization power source is supplied to the lead-out line, and a second initialization power source having a voltage equal to or less than the first initialization power source is supplied to the third power line (Vaint, Vint FIGS. 2-3, paragraph[0087] of Kim I teaches the voltage level of the first driving voltage ELVDD may be higher than the voltage level of the second driving voltage ELVSS; the voltage level of the reference voltage Vref may be lower than the voltage level of the first driving voltage ELVDD; the voltage level of the first initialization voltage Vint may be lower than the voltage level of the second driving voltage ELVSS; the voltage level of the second initialization voltage Vaint may be higher than the voltage level of the first initialization voltage Vint; and the voltage level of the second initialization voltage Vaint may be equal to or higher than the voltage level of the second driving voltage ELVSS, and See also at least paragraphs[0080]-[0086], and [0088]-[0105] of Kim I (i.e., Kim I teaches a second initialization voltage is transmitted via the second initialization voltage line, wherein the first initialization voltage, which is transmitted via the first initialization voltage line, is equal to or less than the second initialization voltage)).
Regarding claim 6, Kim I teaches the pixel of claim 2, wherein the first electrode of the fourth transistor is connected to the second node, and the second electrode of the fourth transistor is connected to the third power line (T4, T3; VL1, VRL FIGS. 2-3, paragraphs[0099]-[0100] of Kim I teaches the third transistor T3 may be connected between the first gate of the first transistor T1 and the reference voltage line VRL; the third transistor T3 may include a gate connected to the third gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VRL; and the third transistor T3 may be turned on by the third gate signal GR received through the third gate line GRL to transmit the reference voltage Vref received through the reference voltage line VRL to the first node N1; the fourth transistor T4 may be connected between the first transistor T1 and the first initialization voltage line VL1; the fourth transistor T4 may include a gate connected to the second gate line GIL, a first terminal connected to the second node N2, and a second terminal connected to the first initialization voltage line VL1; and the fourth transistor T4 may be turned on by the second gate signal GI received through the second gate line GIL to transmit the first initialization voltage Vint received through the first initialization voltage line VL1 to the second node N2, and See also at least paragraphs[0080]-[0098], and [0101]-[0105] of Kim I (i.e., Kim I teaches at least the following: the fourth transistor that has the first terminal connected to the second node, the second terminal connected to the first initialization voltage via the first initialization voltage line, and the second gate line connected to the second gate signal via the corresponding gate line)).
Regarding claim 8, Kim I teaches the pixel of claim 1, wherein the fourth transistor is turned on during a first period of a frame period, and the second transistor and the third transistor are turned on during a second section after the first period (P1, P3 and P4 FIGS. 2-4, paragraphs[0106]-[0107] of Kim I teaches the pixel PXa may display an image in each frame period; referring to FIG. 4, one frame period may include a non-emission period NEP in which the pixel PXa does not emit light and an emission period EP in which the pixel PXa emits light; the non-emission period NEP may include a first initialization period P1, a compensation period P2, a write period P3, and a second initialization period P4; each of the first gate signal GW, the second gate signal GI, the third gate signal GR, the fourth gate signal GB, and the emission control signal EM may have a high-level voltage during some period and may have a low-level voltage during some period; and here, the high-level voltage may be an on voltage for turning on the transistor, and the low-level voltage may be an off voltage for turning off the transistor, and See also at least paragraphs[0080]-[0105], and [0108]-[0118] of Kim I (i.e., Kim I teaches at least the following: the fourth transistor that turned on by the second gate signal during a first initialization period of a frame period responsive to a corresponding gate signal, and the second transistor and the fourth transistor are turned on during a write period and a second initialization period, respectively response to a corresponding gate signal)).
Regarding claim 10, Kim I teaches the pixel of claim 1, further comprising: a storage capacitor connected between the first node and the second node (C1 FIGS. 2-3, paragraph[0103] of Kim I teaches the first capacitor C1 may be connected between the first gate of the first transistor T1 and the organic light emitting diode OLED; a first electrode of the first capacitor C1 may be connected to the first node N1 and a second electrode thereof may be connected to the second node N2; and the first capacitor C1 may be a storage capacitor and may store a voltage corresponding to a threshold voltage of the first transistor T1 and the data signal, and See also at least paragraphs[0080]-[0102], and [0104]-[0105] of Kim I (i.e., Kim I teaches a first capacitor connected between the first node and the second node)).
Regarding claim 11, Kim I teaches a display device comprising: pixels connected to scan lines, data lines, and lead-out lines; a scan driver driving the scan lines; and a data driver driving the data lines, (10a, PX, GL, DL, VL2, 13, 15 FIGS. 2-3, paragraphs[0078]-[0080] of Kim I teaches referring to FIG. 2, a display apparatus 10a according to an embodiment may include a pixel unit 11, a gate driving circuit 13, a data driving circuit 15, a power supply circuit 17, and a controller 19; the pixel unit 11 may be provided in the display area DA; various conductive lines for transmitting electrical signals to the display area DA, peripheral circuits electrically connected to pixel circuits, and/or pads to which a printed circuit board or a driver IC chip is configured to be connected may be located in the peripheral area PA; for example, the gate driving circuit 13, the data driving circuit 15, the power supply circuit 17, and the controller 19 may be provided in the peripheral area PA; as illustrated in FIG. 2, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels PX connected to the plurality of gate lines GL and the plurality of data lines DL may be arranged in the display area DA; the plurality of pixels PX may be arranged in various forms such as stripe arrangement, pentile arrangement (diamond arrangement), and mosaic arrangement to implement an image; each pixel PX may include an organic light emitting diode OLED as a display element (light emitting element), and the organic light emitting diode OLED may be connected to a pixel circuit; the pixel circuit may include a plurality of transistors and at least one capacitor; the pixel PX may emit, for example, red, green, blue, or white light from the organic light emitting diode OLED; and each pixel PX may be connected to at least one corresponding gate line among the plurality of gate lines GL and a corresponding data line among the plurality of data lines DL, and See also at least paragraphs[0081]-[0105] of Kim I (i.e., Kim I teaches a display apparatus having pixels connected to a plurality of gate lines and data lines, corresponding second initialization voltage lines, a gate driving circuit that supplies a corresponding gate signal to each of the plurality of gate lines, and a data driving circuit that supplies a corresponding data signal to each of the data lines)) wherein at least one of the pixels comprises: a first transistor having a first electrode connected to a first power line, a gate electrode connected to a first node, and a second electrode connected to a second node; a light emitting element connected between the second node and a second power line (PXa, T1, ELVDD, N1, N2, OLED, ELVSS FIGS. 2-3, paragraph[0095] of Kim I teaches referring to FIG. 3, the pixel PXa may include an organic light emitting diode OLED as a display element and a pixel circuit PC connected to the organic light emitting diode OLED; the pixel circuit PC may include first to sixth transistors T1 to T6 and first and second capacitors C1 and C2; the first transistor T1 may be a driving transistor outputting a driving current corresponding to a data signal, and the second to sixth transistors T2 to T6 may be switching transistors configured to transmit signals; a first terminal (first electrode) of each of the first to sixth transistors T1 to T6 may be a source or a drain, and a second terminal (second electrode) may be a terminal different from the first terminal; for example, when the first terminal is a drain, the second terminal may be a source; and a node to which a first gate of the first transistor T1 is connected may be defined as a first node N1, and a node to which a second terminal of the first transistor T1 is connected may be defined as a second node N2, and See also at least paragraphs[0080]-[0094], and [0096]-[0105] of Kim I (i.e., Kim I teaches a pixel having a first transistor that has a first terminal connected to a first driving voltage, a first gate connected to a first node, a second terminal connected to a second node, and an organic light emitting diode (OLED) connected between the second node a second driving voltage));
a second transistor connected between one of the data lines and the first node and configured to turn on in response to a first scan signal being received from the scan driver (T2, DL, GWL, GL FIGS. 2-3, paragraph[0098] of Kim I teaches the second transistor T2 may be connected between the first gate of the first transistor T1 and the data line DL; the second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1; and the second transistor T2 may be turned on by the first gate signal GW received through the first gate line GWL to electrically connect the data line DL with the first node N1 and transmit the data signal Vdata received through the data line DL to the first node N1, and See also at least paragraphs[0080]-[0097], and [0099]-[0118] of Kim I (i.e., Kim I teaches a second transistor that is connected between a data line and the first node, wherein the second transistor has a first gate line connected to a first gate signal via a corresponding gate line, and wherein the second transistor turns on responsive to a corresponding gate signal from the gate driving circuit));
a third transistor connected between a lead-out line of the lead-out lines and the second node and configured to turn on in response to a second scan signal being received from the scan driver (T6, VL2, GBL, GL FIGS. 2-3, paragraph[0102] of Kim I teaches the sixth transistor T6 may be connected between the first transistor T1 and the second initialization voltage line VL2; the sixth transistor T6 may include a gate connected to the fourth gate line GBL, a first terminal connected to the second node N2, and a second terminal connected to the second initialization voltage line VL2; and the sixth transistor T6 may be turned on by the fourth gate signal GB received through the fourth gate line GBL to transmit the second initialization voltage Vaint received through the second initialization voltage line VL2 to the second node N2, and See also at least paragraphs[0080]-[0101], and [0103]-[0118] of Kim I (i.e., Kim I teaches a sixth transistor that is connected between second initialization voltage line and the second node, wherein the sixth transistor has a fourth gate line connected to a fourth gate signal via a corresponding gate line, and wherein the sixth transistor turns on responsive to a corresponding gate signal from the gate driving circuit));
a fourth transistor having a first electrode connected between the first node and the second node and a second electrode connected between the lead-out line and a third power line, and configured to turn on in response to a third scan signal being received from the scan driver (T4, VL1 FIGS. 2-3, paragraphs[0099]-[0100] of Kim I teaches the third transistor T3 may be connected between the first gate of the first transistor T1 and the reference voltage line VRL; the third transistor T3 may include a gate connected to the third gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VRL; and the third transistor T3 may be turned on by the third gate signal GR received through the third gate line GRL to transmit the reference voltage Vref received through the reference voltage line VRL to the first node N1; the fourth transistor T4 may be connected between the first transistor T1 and the first initialization voltage line VL1; the fourth transistor T4 may include a gate connected to the second gate line GIL, a first terminal connected to the second node N2, and a second terminal connected to the first initialization voltage line VL1; and the fourth transistor T4 may be turned on by the second gate signal GI received through the second gate line GIL to transmit the first initialization voltage Vint received through the first initialization voltage line VL1 to the second node N2, and See also at least paragraphs[0080]-[0098], and [0101]-[0118] of Kim I (i.e., Kim I teaches at least the following: a fourth transistor that has a first terminal connected to the second node at a position between the second node and the first node, a second terminal connected to a first initialization voltage via a first initialization voltage line, and a second gate line connected to a second gate signal via a corresponding gate line wherein the fourth transistor turns on responsive to a corresponding gate signal from gate the driving circuit)); and
a storage capacitor connected between the first node and the second node (C1 FIGS. 2-3, paragraph[0103] of Kim I teaches the first capacitor C1 may be connected between the first gate of the first transistor T1 and the organic light emitting diode OLED; a first electrode of the first capacitor C1 may be connected to the first node N1 and a second electrode thereof may be connected to the second node N2; and the first capacitor C1 may be a storage capacitor and may store a voltage corresponding to a threshold voltage of the first transistor T1 and the data signal, and See also at least paragraphs[0080]-[0102], and [0104]-[0105] of Kim I (i.e., Kim I teaches a first capacitor connected between the first node and the second node)).
Regarding claim 12, Kim I teaches the display device of claim 11, wherein a voltage of a first initialization power source is supplied to the lead-out line, and a second initialization power source having a voltage equal to or less than the first initialization power source is supplied to the third power line (Vaint, Vint FIGS. 2-3, paragraph[0087] of Kim I teaches the voltage level of the first driving voltage ELVDD may be higher than the voltage level of the second driving voltage ELVSS; the voltage level of the reference voltage Vref may be lower than the voltage level of the first driving voltage ELVDD; the voltage level of the first initialization voltage Vint may be lower than the voltage level of the second driving voltage ELVSS; the voltage level of the second initialization voltage Vaint may be higher than the voltage level of the first initialization voltage Vint; and the voltage level of the second initialization voltage Vaint may be equal to or higher than the voltage level of the second driving voltage ELVSS, and See also at least paragraphs[0080]-[0086], and [0088]-[0105] of Kim I (i.e., Kim I teaches a second initialization voltage is transmitted via the second initialization voltage line, wherein the first initialization voltage, which is transmitted via the first initialization voltage line, is equal to or less than the second initialization voltage)).
Regarding claim 16, Kim I teaches the display device of claim 12, wherein the first electrode of the fourth transistor is connected to the second node, and the second electrode of the fourth transistor is connected to the third power line (T4, VL1 FIGS. 2-3, paragraphs[0099]-[0100] of Kim I teaches the third transistor T3 may be connected between the first gate of the first transistor T1 and the reference voltage line VRL; the third transistor T3 may include a gate connected to the third gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VRL; and the third transistor T3 may be turned on by the third gate signal GR received through the third gate line GRL to transmit the reference voltage Vref received through the reference voltage line VRL to the first node N1; the fourth transistor T4 may be connected between the first transistor T1 and the first initialization voltage line VL1; the fourth transistor T4 may include a gate connected to the second gate line GIL, a first terminal connected to the second node N2, and a second terminal connected to the first initialization voltage line VL1; and the fourth transistor T4 may be turned on by the second gate signal GI received through the second gate line GIL to transmit the first initialization voltage Vint received through the first initialization voltage line VL1 to the second node N2, and See also at least paragraphs[0080]-[0098], and [0101]-[0105] of Kim I (i.e., Kim I teaches at least the following: the fourth transistor that has the first terminal connected to the second node, the second terminal connected to the first initialization voltage via the first initialization voltage line, and the second gate line connected to the second gate signal via the corresponding gate line)).
Regarding claim 17, Kim I teaches the display device of claim 11, wherein the scan driver is configured to supply a third scan signal during a first period of a frame period, and to supply the first scan signal and the second scan signal during a second period after the first period (P1, P3 and P4 FIGS. 2-4, paragraphs[0106]-[0107] of Kim I teaches the pixel PXa may display an image in each frame period; referring to FIG. 4, one frame period may include a non-emission period NEP in which the pixel PXa does not emit light and an emission period EP in which the pixel PXa emits light; the non-emission period NEP may include a first initialization period P1, a compensation period P2, a write period P3, and a second initialization period P4; each of the first gate signal GW, the second gate signal GI, the third gate signal GR, the fourth gate signal GB, and the emission control signal EM may have a high-level voltage during some period and may have a low-level voltage during some period; and here, the high-level voltage may be an on voltage for turning on the transistor, and the low-level voltage may be an off voltage for turning off the transistor, and See also at least paragraphs[0080]-[0105], and [0108]-[0118] of Kim I (i.e., Kim I teaches at least the following: the fourth transistor that turned on by the second gate signal during a first initialization period of a frame period responsive to a corresponding gate signal from the gate driving circuit, and the second transistor and the fourth transistor are turned on during a write period and a second initialization period, respectively response to a corresponding gate signal form the gate driving circuit)).
Regarding claim 19, Kim I teaches an electronic device comprising: a display panel comprising pixels; a processor configured to drive the display panel; and a voltage generation circuit configured to supply a voltage of a driving power source to the display panel (10a, PX, 19, 17 FIGS. 2-3, paragraphs[0078]-[0080] of Kim I teaches referring to FIG. 2, a display apparatus 10a according to an embodiment may include a pixel unit 11, a gate driving circuit 13, a data driving circuit 15, a power supply circuit 17, and a controller 19; the pixel unit 11 may be provided in the display area DA; various conductive lines for transmitting electrical signals to the display area DA, peripheral circuits electrically connected to pixel circuits, and/or pads to which a printed circuit board or a driver IC chip is configured to be connected may be located in the peripheral area PA; for example, the gate driving circuit 13, the data driving circuit 15, the power supply circuit 17, and the controller 19 may be provided in the peripheral area PA; as illustrated in FIG. 2, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels PX connected to the plurality of gate lines GL and the plurality of data lines DL may be arranged in the display area DA; the plurality of pixels PX may be arranged in various forms such as stripe arrangement, pentile arrangement (diamond arrangement), and mosaic arrangement to implement an image; each pixel PX may include an organic light emitting diode OLED as a display element (light emitting element), and the organic light emitting diode OLED may be connected to a pixel circuit; the pixel circuit may include a plurality of transistors and at least one capacitor; the pixel PX may emit, for example, red, green, blue, or white light from the organic light emitting diode OLED; and each pixel PX may be connected to at least one corresponding gate line among the plurality of gate lines GL and a corresponding data line among the plurality of data lines DL, and See also at least paragraphs[0081]-[0105] of Kim I (i.e., Kim I teaches a display apparatus, which includes display panel, having pixels connected to a plurality of gate lines and data lines, corresponding second initialization voltage lines, a gate driving circuit that supplies a corresponding gate signal to each of the plurality of gate lines, and a data driving circuit that supplies a corresponding data signal to each of the data lines, wherein a controller generates a gate control signal to the gate driving circuit and a data control signal to the data driving circuit in order for the transmit gate signals and data signals respectively to drive corresponding pixels in a pixel unit (i.e., in a display panel), and wherein a power supply circuit generate voltages necessary for driving each of the pixels in response to a power control signal PCS from the controller)), wherein at least one of the pixels comprises: a first transistor having a first electrode connected to a first power line, a gate electrode connected to a first node, and a second electrode connected to a second node; a light emitting element connected between the second node and a second power line (PXa, T1, ELVDD, N1, N2, OLED, ELVSS FIGS. 2-3, paragraph[0095] of Kim I teaches referring to FIG. 3, the pixel PXa may include an organic light emitting diode OLED as a display element and a pixel circuit PC connected to the organic light emitting diode OLED; the pixel circuit PC may include first to sixth transistors T1 to T6 and first and second capacitors C1 and C2; the first transistor T1 may be a driving transistor outputting a driving current corresponding to a data signal, and the second to sixth transistors T2 to T6 may be switching transistors configured to transmit signals; a first terminal (first electrode) of each of the first to sixth transistors T1 to T6 may be a source or a drain, and a second terminal (second electrode) may be a terminal different from the first terminal; for example, when the first terminal is a drain, the second terminal may be a source; and a node to which a first gate of the first transistor T1 is connected may be defined as a first node N1, and a node to which a second terminal of the first transistor T1 is connected may be defined as a second node N2, and See also at least paragraphs[0080]-[0094], and [0096]-[0105] of Kim I (i.e., Kim I teaches a pixel having a first transistor that has a first terminal connected to a first driving voltage, a first gate connected to a first node, a second terminal connected to a second node, and an organic light emitting diode (OLED) connected between the second node a second driving voltage));
a second transistor connected between a data line and the first node and having a gate electrode connected to a first scan line (T2, DL, GWL, GL FIGS. 2-3, paragraph[0098] of Kim I teaches the second transistor T2 may be connected between the first gate of the first transistor T1 and the data line DL; the second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1; and the second transistor T2 may be turned on by the first gate signal GW received through the first gate line GWL to electrically connect the data line DL with the first node N1 and transmit the data signal Vdata received through the data line DL to the first node N1, and See also at least paragraphs[0080]-[0097], and [0099]-[0118] of Kim I (i.e., Kim I teaches a second transistor that is connected between a data line and the first node, wherein the second transistor has a first gate line connected to a first gate signal via a corresponding gate line, and wherein the second transistor turns on responsive to a corresponding gate signal from the gate driving circuit));
a third transistor connected between the second node and a lead-out line and having a gate electrode connected to a second scan line (T6, VL2, GBL, GL FIGS. 2-3, paragraph[0102] of Kim I teaches the sixth transistor T6 may be connected between the first transistor T1 and the second initialization voltage line VL2; the sixth transistor T6 may include a gate connected to the fourth gate line GBL, a first terminal connected to the second node N2, and a second terminal connected to the second initialization voltage line VL2; and the sixth transistor T6 may be turned on by the fourth gate signal GB received through the fourth gate line GBL to transmit the second initialization voltage Vaint received through the second initialization voltage line VL2 to the second node N2, and See also at least paragraphs[0080]-[0101], and [0103]-[0118] of Kim I (i.e., Kim I teaches a sixth transistor that is connected between second initialization voltage line and the second node, wherein the sixth transistor has a fourth gate line connected to a fourth gate signal via a corresponding gate line, and wherein the sixth transistor turns on responsive to a corresponding gate signal from the gate driving circuit));
a fourth transistor having a first electrode connected to the first node or the second node, a second electrode connected to the lead-out line or a third power line, and a gate electrode connected to a third scan line (T4, T3; VL1, VRL FIGS. 2-3, paragraphs[0099]-[0100] of Kim I teaches the third transistor T3 may be connected between the first gate of the first transistor T1 and the reference voltage line VRL; the third transistor T3 may include a gate connected to the third gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VRL; and the third transistor T3 may be turned on by the third gate signal GR received through the third gate line GRL to transmit the reference voltage Vref received through the reference voltage line VRL to the first node N1; the fourth transistor T4 may be connected between the first transistor T1 and the first initialization voltage line VL1; the fourth transistor T4 may include a gate connected to the second gate line GIL, a first terminal connected to the second node N2, and a second terminal connected to the first initialization voltage line VL1; and the fourth transistor T4 may be turned on by the second gate signal GI received through the second gate line GIL to transmit the first initialization voltage Vint received through the first initialization voltage line VL1 to the second node N2, and See also at least paragraphs[0080]-[0098], and [0101]-[0118] of Kim I (i.e., Kim I teaches at least the following: a fourth transistor that has a first terminal connected to the second node at a position between the second node and the first node, a second terminal connected to a first initialization voltage via a first initialization voltage line, and a second gate line connected to a second gate signal via a corresponding gate line wherein the fourth transistor turns on responsive to a corresponding gate signal from gate the driving circuit)); and
a storage capacitor connected between the first node and the second node (C1 FIGS. 2-3, paragraph[0103] of Kim I teaches the first capacitor C1 may be connected between the first gate of the first transistor T1 and the organic light emitting diode OLED; a first electrode of the first capacitor C1 may be connected to the first node N1 and a second electrode thereof may be connected to the second node N2; and the first capacitor C1 may be a storage capacitor and may store a voltage corresponding to a threshold voltage of the first transistor T1 and the data signal, and See also at least paragraphs[0080]-[0102], and [0104]-[0105] of Kim I (i.e., Kim I teaches a first capacitor connected between the first node and the second node)).
Regarding claim 20, Kim I teaches the electronic device of claim 19, wherein a voltage of a first initialization power source is supplied to the lead-out line, and a second initialization power source having a voltage equal to or less than the first initialization power source is supplied to the third power line (Vaint, Vint FIGS. 2-3, paragraph[0087] of Kim I teaches the voltage level of the first driving voltage ELVDD may be higher than the voltage level of the second driving voltage ELVSS; the voltage level of the reference voltage Vref may be lower than the voltage level of the first driving voltage ELVDD; the voltage level of the first initialization voltage Vint may be lower than the voltage level of the second driving voltage ELVSS; the voltage level of the second initialization voltage Vaint may be higher than the voltage level of the first initialization voltage Vint; and the voltage level of the second initialization voltage Vaint may be equal to or higher than the voltage level of the second driving voltage ELVSS, and See also at least paragraphs[0080]-[0086], and [0088]-[0105] of Kim I (i.e., Kim I teaches a second initialization voltage is transmitted via the second initialization voltage line, wherein the first initialization voltage, which is transmitted via the first initialization voltage line, is equal to or less than the second initialization voltage)).
Potentially Allowable Subject Matter
Claims 3-5, 7, 9, 13-15, and 18 would be allowable if rewritten to overcome applicable objection(s) indicated above, and if rewritten in independent form including all of the limitations of the base claim and any intervening, because for each of the claims 3-5, 7, 9, 13-15, and 18 the prior art references of record do not teach the combination of all element limitations as presently claimed.
Conclusion
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/ABDUL-SAMAD A ADEDIRAN/Primary Examiner, Art Unit 2621