Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1 – 20 are presented for examination.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 120 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/15/2025 was received. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract of the disclosure is objected to because the language “may receive”, “may generate”, “may store”, “may perform”, and “may, for a write operation, re-request” are speculative and fail to provide a concise statement of the technical disclosure of the patent.
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are:
Claim 1
one or more controllers associated with one or more memory devices, wherein the one or more controllers are configured to cause the memory system to:
Figure 3 – 5; paragraph [0037]-[0039], [0075]-[0080]
receive a plurality of data units in accordance with a first protocol, the plurality of data units comprising first sets of parity bits;
generate a plurality of protocol units using the plurality of data units in accordance with a second protocol; and
compare the first sets of parity bits to second sets of parity bits generated for corresponding data in the plurality of protocol units based on receiving the plurality of data units and generating the plurality of protocol units.
Claim 2
the one or more controllers are further configured to cause the memory system to:
Figure 3 – 5; paragraph [0037]-[0039], [0075]-[0080]
generate one or more data storage units using the plurality of protocol units in accordance with a third protocol based on the first sets of parity bits matching the second sets of parity bits; and
compare the second sets of parity bits to third sets of parity bits generated for corresponding data in the one or more data storage units.
Claim 3
the one or more controllers are further configured to cause the memory system to: transfer the one or more data storage units and the third sets of parity bits to one or more memory arrays of the memory system based on the second sets of parity bits matching the third sets of parity bits.
Figure 3 – 5; paragraph [0037]-[0039], [0075]-[0080]
Claim 4
the one or more controllers are further configured to cause the memory system to:
Figure 3 – 5; paragraph [0037]-[0039], [0075]-[0080]
transmit one or more data requests corresponding to one or more data units associated with the plurality of protocol units based on the second sets of parity bits not matching the third sets of parity bits;
receive a second plurality of data units in accordance with the first protocol based on transmitting the one or more data requests, the second plurality of data units comprising fourth sets of parity bits;
generate a second plurality of protocol units using the second plurality of data units in accordance with the second protocol; and
compare the fourth sets of parity bits to fifth sets of parity bits generated for corresponding data in the second plurality of protocol units based on receiving the second plurality of data units and generating the second plurality of protocol units.
Claim 5
the one or more controllers are further configured to cause the memory system to:
Figure 3 – 5; paragraph [0037]-[0039], [0075]-[0080]
generate one or more second data storage units using the second plurality of protocol units in accordance with the third protocol;
compare the fifth sets of parity bits to sixth sets of parity bits generated for corresponding data in the one or more second data storage units; and
transfer the one or more second data storage units and the sixth sets of parity bits to one or more memory arrays of the memory system based on the fifth sets of parity bits matching the sixth sets of parity bits.
Claim 6
the one or more controllers are further configured to cause the memory system to:
Figure 3 – 5; paragraph [0037]-[0039], [0075]-[0080]
receive a write command indicating a range of logical addresses of one or more memory arrays of the memory system; and
[0078]-[0080], [0096], [0101]
transmit a plurality of data requests each comprising an indicator of a respective subset of the range of logical addresses indicated in the write command, wherein the plurality of data units are received based on transmitting the plurality of data requests.
Claim 7
the one or more controllers are further configured to cause the memory system to: determine one or more errors associated with the plurality of protocol units based on the first sets of parity bits not matching the second sets of parity bits.
Figure 3 – 5; paragraph [0037]-[0039], [0075]-[0080]
Claim 9
one or more controllers associated with one or more memory devices, wherein the one or more controllers are configured to cause the memory system to:
Figure 3 – 5; paragraph [0037]-[0039], [0075]-[0080]
receive one or more data storage units in accordance with a first protocol, the one or more data storage units comprising first sets of parity bits;
generate a plurality of protocol units using the one or more data storage units in accordance with a second protocol; and
compare the first sets of parity bits to second sets of parity bits generated for corresponding data in the plurality of protocol units based on receiving the one or more data storage units and generating the plurality of protocol units.
Claim 10
the one or more controllers are further configured to cause the memory system to:
Figure 3 – 5; paragraph [0037]-[0039], [0075]-[0080]
generate a plurality of data units using the plurality of protocol units in accordance with a third protocol based at least in part on the first sets of parity bits matching the second sets of parity bits; and
compare the second sets of parity bits to third sets of parity bits generated for corresponding data in the plurality of data units.
Claim 11
the one or more controllers are further configured to cause the memory system to: transmit the plurality of data units based on the second sets of parity bits matching the third sets of parity bits.
Figure 3 – 5; paragraph [0037]-[0039], [0075]-[0080]
Claim 12
the one or more controllers are further configured to cause the memory system to:
Figure 3 – 5; paragraph [0037]-[0039], [0075]-[0080]
receive second copies of the one or more data storage units in accordance with the first protocol based on the second sets of parity bits not matching the third sets of parity bits;
regenerate the plurality of protocol units using the second copies of the one or more data storage units in accordance with the second protocol; and
compare the first sets of parity bits to fourth sets of parity bits generated for corresponding data in the regenerated plurality of protocol units based on receiving the one or more data storage units and regenerating the plurality of protocol units.
Claim 13
the one or more controllers are further configured to cause the memory system to:
Figure 3 – 5; paragraph [0037]-[0039], [0075]-[0080]
generate a second plurality of data units using the regenerated plurality of protocol units in accordance with the third protocol;
compare the fourth sets of parity bits to fifth sets of parity bits generated for corresponding data in the second plurality of data units; and
transmit the second plurality of data units based on the fourth sets of parity bits matching the fifth sets of parity bits.
Claim 14
the one or more controllers are further configured to cause the memory system to: receive a read command indicating a range of logical addresses of one or more memory arrays of the memory system, wherein the one or more data storage units are received in accordance with the first protocol based on the read command.
Figure 3 – 5; paragraph [0078]-[0080], [0096], [0101]
Claim 15
the one or more controllers are further configured to cause the memory system to: determine one or more errors associated with the plurality of protocol units based on the first sets of parity bits not matching the second sets of parity bits.
Figure 3 – 5; paragraph [0037]-[0039], [0075]-[0080]
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1 – 20 are rejected on the ground of nonstatutory double patenting over claims 1, 10, 12, and 14 of U.S. Patent No. 12,292,795 since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows:
Claim 1 – Application 19/098910
Claim 10 – Patent 12,292,795
A memory system, comprising:
A memory system, comprising:
one or more controllers associated with one or more memory devices, wherein the one or more controllers are configured to cause the memory system to:
one or more controllers associated with one or more memory devices, wherein the one or more controllers are configured to cause the memory system to:
receive a plurality of data units in accordance with a first protocol, the plurality of data units comprising first sets of parity bits;
read, from one or more memory arrays of the memory system, at least one data storage unit corresponding to a range of logical addresses;
generate a plurality of protocol units using the plurality of data units in accordance with a second protocol; and
generate a plurality of protocol units comprising data from the at least one data storage unit, the plurality of protocol units corresponding to the range of logical addresses;
compare the first sets of parity bits to second sets of parity bits generated for corresponding data in the plurality of protocol units based on receiving the plurality of data units and generating the plurality of protocol units.
Claim 12
compare respective sets of parity bits from a plurality of first sets of parity bits with respective sets of parity bits from a plurality of second sets of parity bits;
One of ordinary skill in the art would clearly recognize independent claim 1, of application 19/098910 is an obvious variation of the claimed subject matter of independent claims 10 and 12, of patent 12,292,795. Specifically, both claim 1, of the current application 19/098910, and claims 10 and 12, of patent 12,292,795 discloses: “A memory system, comprising: one or more controllers associated with one or more memory devices, wherein the one or more controllers are configured to cause the memory system to:” comprising such steps as “generate a plurality of protocol units” and “compare respective sets of parity bits from a plurality of first sets of parity bits with respective sets of parity bits from a plurality of second sets of parity bits”.
One of ordinary skill in the art would recognize the memory system disclosed by claim 1, of the current application 19/098910, as a broad recitation of the operations performed by the memory system disclosed in claims 10 and 12 of Patent 12,292,795. Specifically, one of ordinary skill would understand “receive a plurality of data units” as a broad recitation of “read, from one or more memory arrays of the memory system”. A memory system performing operations and a memory system capable of performing the disclosed operations would be recognize by one of ordinary skill in the art as obvious variants of each other.
Therefore, one of ordinary skill in the art would recognize the memory system of claim 1, of the current application 19/098910, as performing the operations of the memory system of claim 10 and 12, of U.S. Patent 12,292,795, and as such are obvious variants of each other.
Claim 2 – Application 19/098910
Claim 14 – Patent 12,292,795
Claim 3 – Application 19/098910
Claim 12 – Patent 12,292,795
Claim 4 – Application 19/098910
Claim 14 – Patent 12,292,795
Claim 5 – Application 19/098910
Claim 14 – Patent 12,292,795
Claim 6 – Application 19/098910
Claim 1 – Patent 12,292,795
Claim 7 – Application 19/098910
Claim 10 – Patent 12,292,795
Claim 8 – Application 19/098910
Claim 10/12 – Patent 12,292,795
Claim 9 – Application 19/098910
Claim 10/12 – Patent 12,292,795
Claim 10 – Application 19/098910
Claim 14 – Patent 12,292,795
Claim 11 – Application 19/098910
Claim 12 – Patent 12,292,795
Claim 12 – Application 19/098910
Claim 14 – Patent 12,292,795
Claim 13 – Application 19/098910
Claim 10 – Patent 12,292,795
Claim 14 – Application 19/098910
Claim 10/12 – Patent 12,292,795
Claim 15 – Application 19/098910
Claim 10 – Patent 12,292,795
Claim 16 – Application 19/098910
Claim 10/12 – Patent 12,292,795
Claim 17 – Application 19/098910
Claim 10/12 – Patent 12,292,795
Claim 18 – Application 19/098910
Claim 14 – Patent 12,292,795
Claim 19 – Application 19/098910
Claim 12 – Patent 12,292,795
Claim 20 – Application 19/098910
Claim 14 – Patent 12,292,795
Claims XX are rejected on the ground of nonstatutory double patenting over claims XX of U.S. Patent No. 11,914,473 since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows:
Claim 1 – Application 19/098910
Claim 8 – Patent 11,914,473
A memory system, comprising:
An apparatus, comprising:
one or more controllers associated with one or more memory devices, wherein the one or more controllers are configured to cause the memory system to:
a controller associated with a memory device, wherein the controller is configured to cause the apparatus to:
receive a plurality of data units in accordance with a first protocol, the plurality of data units comprising first sets of parity bits;
receive, at a memory system, a read command for a range of logical addresses of a memory array of the memory system;
generate a plurality of protocol units using the plurality of data units in accordance with a second protocol; and
generate a plurality of protocol units comprising data from the range of logical addresses corresponding to the at least one data storage unit;
compare the first sets of parity bits to second sets of parity bits generated for corresponding data in the plurality of protocol units based on receiving the plurality of data units and generating the plurality of protocol units.
Claim 9
compare respective sets of parity bits from a plurality of first sets of parity bits with respective sets of parity bits from a plurality of second sets of parity bits generated by a protocol controller; and determine that one or more parity bits from the plurality of first sets of parity bits does not match corresponding parity bits from the plurality of second sets of parity bits, wherein determining the error associated with the one or more protocol units of the plurality of protocol units is based at least in part on determining that the one or more parity bits from the plurality of first sets of parity bits does not match the corresponding parity bits from the plurality of second sets of parity bits.
One of ordinary skill in the art would clearly recognize independent claim 1, of application 19/098910is an obvious variation of the claimed subject matter of independent claims 8 and 9, of patent 11,914,473. Specifically, both claim 1, of the current application 19/098910, and claims 8 and 9, of patent 11,914,473 discloses: one or more controllers associated with one or more memory devices, wherein the one or more controllers are configured to cause the memory system to: comprising such steps as “generate a plurality of protocol units” and compare respective sets of parity bits from a plurality of first sets of parity bits with respective sets of parity bits from a plurality of second sets of parity bits generated by a protocol controller.
One of ordinary skill in the art would recognize the memory device disclosed by claim 1, of the current application 19/098910, as a broad recitation of the operations performed by the apparatus disclosed in claims 8 and 9 of Patent 11,914,473. An apparatus performing operations and a memory device capable of performing the disclosed operations would be recognize by one of ordinary skill in the art as obvious variants of each other.
Therefore, one of ordinary skill in the art would recognize the memory device claim 1, of the current application 19/098910, as performing the operations of the apparatus of claims 8 and 9, of U.S. Patent 11,914,473, and as such are obvious variants of each other.
Claim 2 – Application 19/098910
Claim 11 – Patent 11,914,473
Claim 3 – Application 19/098910
Claim 8 – Patent 11,914,473
Claim 4 – Application 19/098910
Claim 11 – Patent 11,914,473
Claim 5 – Application 19/098910
Claim 11 – Patent 11,914,473
Claim 6 – Application 19/098910
Claim 1 – Patent 11,914,473
Claim 7 – Application 19/098910
Claim 9 – Patent 11,914,473
Claim 8 – Application 19/098910
Claim 15 – Patent 11,914,473
Claim 9 – Application 19/098910
Claim 8/9 – Patent 11,914,473
Claim 10 – Application 19/098910
Claim 11 – Patent 11,914,473
Claim 11 – Application 19/098910
Claim 8 – Patent 11,914,473
Claim 12 – Application 19/098910
Claim 11 – Patent 11,914,473
Claim 13 – Application 19/098910
Claim 11 – Patent 11,914,473
Claim 14 – Application 19/098910
Claim 8 – Patent 11,914,473
Claim 15 – Application 19/098910
Claim 9 – Patent 11,914,473
Claim 16 – Application 19/098910
Claim 15 – Patent 11,914,473
Claim 17 – Application 19/098910
Claim 8/9 – Patent 11,914,473
Claim 18 – Application 19/098910
Claim 11 – Patent 11,914,473
Claim 19 – Application 19/098910
Claim 11 – Patent 11,914,473
Claim 20 – Application 19/098910
Claim 8 – Patent 11,914,473
Closest Prior Arts of Record
Kim, U.S. Publication 2020/0174865 teaches: A controller for use in a memory device includes an error information generator configured to receive error information about an error occurring while a command is being processed at a protocol layer, generate command error information corresponding to the command based on the received error information, and store the generated command error information in a first storage area, and an error information manager configured to store the command error information, stored in the first storage area, in a second storage area in response to an external request.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
KUO; Ming-I US 20170220419 A1
Sanders; Richard et al. US 20070079080 A1
HILLEL; Eliad et al. US 20230244532 A1
Tamura; Takayuki et al. US 20070101237 A1
Rowlands, et al. US 20050081127 A1
Mills; Peter et al. US 20200293395 A1
Singhal; Ashok et al. US 7836329 B1
Avritch; Steven A. et al. US 6360290 B1
Zitlaw; Cliff US 10141034 B1
Pawlowski; J. Thomas US 20150347226 A1
Siegel; Michael S. et al. US 20220050787 A1
generate a plurality of protocol units using the plurality of data units in accordance with a second protocol; and
compare the first sets of parity bits to second sets of parity bits generated for corresponding data in the plurality of protocol units based on receiving the plurality of data units and generating the plurality of protocol units.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL F MCMAHON whose telephone number is (571)270-3232. The examiner can normally be reached Monday-Thursday 9am - 5pm EST.
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/Daniel F. McMahon/Primary Examiner, Art Unit 2111
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