DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed February 3, 2025.
Claims 1-13, 15, 17-23, 26-30, 32 and 35-36 are pending. Claims 14, 16, 24-25, 31 and 33-34 were canceled by preliminary amendments. Claim 1 is independent.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on February 3, 2025. This IDS has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 9-13, 15, 17, 21, 23, 26-27, 30, 32 and 36 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yang et al. (U.S. 2024/0045655; hereinafter “Yang”).
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Regarding independent claim 1, Yang discloses a multi-processor computer system (Fig. 1), comprising:
an in-memory computer (Fig. 1: Slice #0-#63) comprising memory components (Fig. 1: plurality of 6T-Cell Cluster + MAC), each memory component comprising a compute engine (Fig. 1: MAC) and a storage element for storing data (Fig. 1: 6T-Cell Cluster), the compute engine operable to read, write, and process data stored in the storage element of the memory component (see page 3, par. 0037); and
a processor external to the in-memory computer connected to the in-memory computer (Fig. 1: SRAM Readout, Drivers, Timing, DAC, ADC, Digital Peri., CLK, Shared Logic), wherein each storage element is mapped into a memory space of the processor (see page 2, par. 0014) and is accessible at memory addresses of the processor through a bit line (Fig. 1: Input BL, Global BL),
wherein each memory component is connected to the bit line through a memory select (MEMSEL) switch, and in that the MEMSEL switch can isolate or connect the bit line of each memory component from or to external control or data circuits (see Examiner’s Markup Yang’s Figure 4A).
Regarding claim 2, Yang discloses wherein each compute engine is operable to process data stored in the storage element in response to an operate command (Fig. 4A, for example: MAC circuit is operable receiving signal from the input port).
Regarding claim 3, Yang discloses wherein the processor provides an operate command together with data as part of a storage element write operation that writes data into the storage elements of the memory components (see page 3, par. 0037 and 0043-0044).
Regarding claim 4, Yang discloses wherein each memory component is directly connected to at least one other memory component to transmit, share, or receive data directly to and from the other memory component (see page 3, par. 0037 and 0043-0044).
Regarding claim 5, Yang discloses the limitations with respect to claim 1.
As discussed above, Yang’s multi-processor computer system is substantially identical in structure to the claimed “multi-processor computer system,” where the differences reside only in the remaining limitations relating to function and properties of “wherein the storage elements are responsive to in-memory-computer addresses in an in-memory-computer address range and the processor is operable to write data to memory components at the in-memory-computer addresses.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Yang’s multi-processor computer system appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 6, Yang disclose the limitations with respect to claim 5.
As discussed above, Yang’s multi-processor computer system is substantially identical in structure to the claimed “multi-processor computer system,” where the differences reside only in the remaining limitations relating to function and properties of “wherein the processor has a processor address space and the storage elements are memory mapped into the processor address space.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Yang’s multi-processor computer system appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 9, Yang discloses wherein each memory component comprises one or more of a bit memory, a multi-bit memory, a single-bit multiplier, or an iterative multi-bit multiplier (see page 3, par. 0043-0044).
Regarding claim 10, Yang discloses wherein each compute engine comprises a capacitive product storage circuit, a capacitive accumulator storage circuit, or both a product storage circuit and a capacitive accumulator storage circuit (see page 5, par. 0072-0073).
Regarding claim 11, Yang discloses the limitations with respect to claim 10.
As discussed above, Yang’s multi-processor computer system is substantially identical in structure to the claimed “multi-processor computer system,” where the differences reside only in the remaining limitations relating to function and properties of “wherein the capacitive product storage circuits of two or more memory components are connected together to share data.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Yang’s multi-processor computer system appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 12, Yang discloses wherein the two or more memory components connected together are disposed in adjacent memory components (Fig. 1: 6T-Cell Clusters are adjacent to each other).
Regarding claim 13, Yang discloses wherein the processor comprises a controller that controls the in-memory computer, and wherein the controller receives analog data from the memory components (Fig. 1: ADC#0-ADC#31 and Digital Peri.).
Regarding claim 15, Yang discloses wherein the controller converts the received analog data to digital data, and wherein the controller accumulates data received from one or more memory components (see page 3, par. 0037).
Regarding claim 17, Yang discloses wherein the memory components are disposed in an array in which bit lines each connect a row of memory components and word lines each connect a column of memory components, or vice versa, controller by the processor or controller (see Fig. 1).
Regarding claim 21, Yang discloses the limitations with respect to claim 1.
As discussed above, Yang’s multi-processor computer system is substantially identical in structure to the claimed “multi-processor computer system,” where the differences reside only in the remaining limitations relating to function and properties of “wherein the each of the compute engines is connected to the bit line and the compute engine is operable to read data stored in the storage element of the memory components through the bit line and process the data, and wherein the storage elements are accessible at memory addresses of the processor through the bit line.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Yang’s multi-processor computer system appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 23, Yang discloses wherein the compute engine comprises an analog-to-digital converter (Fig. 1: ADCs), wherein the compute engine is operable to accumulate data stored in controllably selected bit cells, and wherein the compute engine is operable to convert data stored in the bit cells from an analog value to a digital value or to process data stored in the bit cells and convert the processed data from an analog value to a digital value (see page 3, par. 0037).
Regarding claim 26, Yang discloses wherein the compute engine operates using analog circuits (see Fig. 4A).
Regarding claim 27, Yang discloses wherein the storage elements of the memory components are memory-mapped into a memory space of the processor or controller (see page 2, par. 0014) and the processor or controller is operable to read and write data into any subset of the storage elements (see page 3, par. 0037).
Regarding claim 30, Yang discloses wherein the analog-to-digital converter is disposed in the compute engine or wherein the analog-to-digital converter is disposed in the external processor (see Fig. 1).
Regarding claim 32¸Yang discloses a digital adder for adding partial accumulated sums each digitized by an analog-to-digital converter, wherein the digital adder is disposed in the compute or wherein the digital adder is disposed in the external processor (see page 3, par. 0037).
Regarding claim 35, Yang discloses each storage element comprises one or more bit cells (Fig. 4A: 6T Cells), each bit cell connected to the compute engine with a bit line, each bit line connected to and controlled by the processor or controller (Fig. 4A: LBL and GBL).
Regarding claim 36¸ Yang discloses wherein the storage elements of the memory components are memory-mapped into a memory space of the processor or controller through the word lines and the bit lines (see page 2, par. 0014), the bit lines transmitting bits to the memory components and the word lines select and enable each memory component to write the bits into the memory components, and each compute engine is operable to read data stored in the storage element through the bit line and process the data (see page 5, par. 0072)
Allowable Subject Matter
Claims 7-8, 18-19, 22 and 28-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 7, there is no teaching or suggestion in the prior art of record to provide the recited processor memory connected to the processor, wherein the processor is operable to write and read processor data to an from the processor memory, and the processor memory is memory mapped into the processor address space at a processor-memory address range distinct from the in-memory-computer address range.
With respect to claim 18, there is no teaching or suggestion in the prior art of record to provide the recited each compute engine comprises a capacitive product storage circuit and the capacitive product storage circuits of a row or column of memory components are connected together.
With respect to claim 19, there is no teaching or suggestion in the prior art of record to provide the recited each compute engine in a row or column of memory components comprises an iterative multi-bit multiplier.
With respect to claim 22, there is no teaching or suggestion in the prior art of record to provide the recited wherein the in-memory computer comprises a multiplexer disposed between and connected to the storage element and the compute engine and operable to select bit cells in the storage element so that the compute engine is operable to process the data stored in the selected bit cells.
With respect to claim 28, there is no teaching or suggestion in the prior art of record to provide the recited some of the compute engines comprise bit multipliers that store bit products in capacitors, two or more of the capacitors are electrically connected in parallel and to an analog-to-digital converter, the analog-to-digital converter having a precision less than the maximum possible value of the accumulated bit products stored in the parallel-connected capacitors.
With respect to claim 29, there is no teaching or suggestion in the prior art of record to provide the recited some of the compute engines comprise iterative bit multiplier that store accumulated bit products in a capacitor, the capacitor is electrically connected to an analog-to-digital converter, and the analog-to-digital converter has a precision less than the maximum possible value of the accumulated bit products stored in the parallel-connected capacitors to provide a digital accumulated value.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
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