DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on February 3, 2025 has been fully considered by the examiner.
Drawings
3. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the substrate and the spatial disposition of components over the substrate (see claims 7-9) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
4. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: FIG. 3A, reference characters Q.sub.0 – Q.sub.31.
In the disclosure, capital Q is used to describe charge deposited on analog storage circuit 16 (e.g., FIG. 6A; page 15, lines 16-24), while lowercase q is used to describe bits stored in a bit cell (e.g., FIGS. 1-2, 3B; page 11, lines 29-33). Examiner believes capital Q in FIG. 3A is intended to describe bits stored in bit cells and should be modified accordingly. Alternatively, the specification may be modified to clarify the drawing.
5. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7. Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation, “in the row of memory components” in lines 6-7. It is unclear if this refers to “memory components arranged in rows” in line 2 or “a respective row of memory components” in line 5. Because of the immediate context in lines 5-7, for the purpose of this action, “in the row of memory components” in lines 6-7 shall be interpreted as “in the respective row of memory components.” Claims 2-15 depend on claim 1.
Claim 1 recites the limitation, “in the column of memory components” in lines 9-11. It is unclear if this refers to “memory components arranged in rows and columns” in line 2 or “a respective column of memory components” in line 8. Because of the immediate context in lines 8-11, for the purpose of this action, lines 8-11 shall be interpreted as: “word lines, each word line connected to a respective column of memory components, the word lines operable to enable each memory component in the respective column of memory components to write a bit into each memory component in the respective column of memory components.”
Claim 2 recites the limitation “the bitline internal to the memory component” in line 4. There is insufficient antecedent basis for this limitation in the claim (note the location of “bit lines” in claim 1, line 5, is not identified). For the purpose of this action, “the bitline internal to the memory component” in line 4 shall be interpreted as “[[the]] a bitline internal to the memory component.” Claim 3 depends on claim 2.
Claim 2 recites the limitation, “wherein each memory component is connected to a bit line external to the memory component through a memory select (MEMSEL) switch that is operable to connect the memory component to the bit line internal to the memory component or isolate the memory component from the bit line external to the memory component.” This description does appear to accurately describe FIG. 3A and page 11, lines 1-3 of the present application.
Specifically, a bit line internal to a memory component cannot be connected to the memory component by a switch because the bit line internal to the memory component is an integral part of the memory component.
Page 11, lines 1-3, recite, “MEMSEL switch 60 can isolate or connect bit line 24 (e.g., an internal bit line 24) of each memory component 40 from or to external control or data circuits (e.g., external bit line 25 and controller 70 as shown in Fig. 1).” This accurately describes FIG. 3A.
For the purpose of this action, claim 2 shall be interpreted as follows: “wherein each memory component is connected to a bit line external to the memory component through a memory select (MEMSEL) switch that is operable to connect the memory component to the bit line external to the memory component or isolate the memory component from the bit line external to the memory component.”
Claim 4 recites the limitation, “connected to the compute engine” in line 3. The location/identity of the compute engine is not clearly defined. For the purpose of this action, “connected to the compute engine” shall be interpreted as “connected to the compute engine of the same memory component.” Claim 5 depends on claim 4.
Claim 5 recites the limitation, “connected directly to the compute engine” in lines 2-3. The location/identity of the compute engine is not clearly defined. Claim 5 also recites the limitation, “each bit cell in a memory component” in line 2. It is unclear if this refers to “the bit cell” of “each memory component” in claim 1, lines 2-3, or “each bit cell of the multiple bit cells” in claim 4, line 3.
For the purpose of this action, claim 5 shall be interpreted as: “The compact in-memory computer architecture of claim 4, wherein each bit cell of the multiple bit cells is connected directly to the compute engine of the same memory component.”
Claims 7-9 each recite the limitation “spatially disposed” (claims 7 and 9) or “disposed spatially” (claim 8). It is unclear what meaning is intended by “spatially.” One dictionary definition of “spatially” is “in a way that relates to space or to the location or extent of objects in three-dimensional space.” This appears to add ambiguity to the claims as the implication of the present disclosure is a two-dimensional array (e.g., FIGS. 3A and 10; page 8, lines 31-33).
For the purpose of this action, the term “spatially” in claims 7-9 shall be disregarded.
Claim 8 recites the limitation, “the bit cell or bit cells of the memory component” in line 3. There is insufficient antecedent basis for this limitation in the claim. Neither claim 1 nor claim 7, upon which claim 8 depends, provide antecedent basis for “the…bit cells” (i.e., claims 1 and 7 define only a single bit cell in each memory component).
For the purpose of this action, “the bit cell or bit cells of the memory component” shall be interpreted as “the bit cell of the memory component.”
Claim 9 recites the limitation, “the bit cell or bit cells of the memory component” in line 3 and “the bit cell or bit cells of the adjacent memory component” in line 4. There is insufficient antecedent basis for these limitations in the claim. Neither claim 1 nor claim 7, upon which claim 8 depends, provide antecedent basis for “the…bit cells” (i.e., claims 1 and 7 define only a single bit cell in each memory component).
For the purpose of this action, lines 3-4 of claim 9 shall be interpreted as: “disposed between the bit cell of the memory component and the bit cell of the adjacent memory component.”
Claim 10 recites the limitation, “each compute engine of a memory component” in line 2. It is unclear what is meant by “each compute engine of a memory component” as claims 1 and 7, upon which claim 10 depends, appear to define only one compute engine per memory component.
For the purpose of this action, “each compute engine of a memory component” shall be interpreted as “the compute engine of a memory component.”
Claim 11 recites the limitation, “the compute engine is connected to the bit cell with the corresponding bit line.” There is insufficient antecedent basis for this limitation in the claim (no bit line appears to be provided within a memory component in claim 1, and therefore there is no antecedent basis for “the corresponding bit line” connecting components within a memory component).
For the purpose of this action, “the compute engine is connected to the bit cell with the corresponding bit line” shall be interpreted as “the compute engine is connected to the bit cell with [[the]] a corresponding bit line.”
Claim 13 recites the limitation, “the controller” in line 3. There is insufficient antecedent basis for this limitation in the claim (“a controller” is introduced in claim 6, which does not provide antecedent basis for claim 13). For the purpose of this action, “the controller” shall be interpreted as “[[the]] a controller.” Claims 14-15 depend on claim 13.
Claim 14 recites the limitation, “to process the stored bit” in line 7. It is unclear which bit among the each bit line is to be processed. For the purpose of this action, “to process the stored bit” in line 7 shall be interpreted as “to process the stored bit of the respective memory component.”
Regarding claim 15, it is unclear if the listed items are intended to be possible steps of a method or different embodiments of a method. Examiner believes the listed items may be intended to reflect the various embodiments described on page 4 in lines 10-27. However, claim 15 does not denote embodiment (ii), and embodiments (i) and (iii) appear to repeat the identical embodiment three times, each reciting, “multiplying multiple bits of a first multi-bit value by a bit of a second multi-bit value in parallel.”
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
9. Claims 1-2, 4-5, and 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang, et al (US 20240045655 A1), hereinafter Yang.
Regarding independent claim 1, Yang teaches a compact in-memory computer architecture, comprising:
memory components (FIG. 1, each having a MAC and 6T-Cell Cluster, which is the IMC block of FIG. 3A) arranged in rows and columns (FIG. 1 illustrates bit lines as columns; together with FIGS. 4-7 and ¶[0072], word lines are understood to be in rows), each memory component comprising a bit cell (FIG. 3A, one of SRAM cell 121) and a compute engine connected to the bit cell (FIG. 3A, MAC 130, shown connected to SRAM cells 121), wherein the bit cell is operable to store a bit and the compute engine is operable to process the bit (the MAC is a multiple-and-accumulate circuit; ¶[0003]);
bit lines (FIG. 1, Global BL (GBL)), each bit line connected to a respective row of memory components (FIG. 4A shows the GBL connection to memory components; note the “row” of the present application is the bit line direction, while Yang illustrates bit lines as columns), the bit lines operable to provide a bit to each memory component in the row of memory components (FIG. 4A shows the global bit line GBL connected to local bit line LBL via switch S.sub.p); and
word lines, each word line connected to a respective column of memory components, the word lines operable to enable each memory component in the column of memory components to write a bit into each memory component in the column of memory components (¶[0072] teaches “one of the 6T cells is accessed by turning on the corresponding word line (WL)”; WLs are understood to be horizontal lines coupled to 6T SRAM Cells in FIG. 4A; Note the “column” of the present application is the WL direction, while Yang illustrates WLs as rows).
Regarding claim 2, Yang teaches the limitations of claim 1.
Yang further teaches each memory component is connected to a bit line external to the memory component (FIGS. 1, 4A, GBL) through a memory select (MEMSEL) switch (FIG. 4A, S.sub.p; ¶[0052]) that is operable to connect the memory component to the bit line internal to the memory component (FIG. 4A, LBL; that is, when closed, the switch connects the LBL to the GBL; compare Yang FIG. 4A to FIG. 3A and page 11, lines 1-3 of the present application) or isolate the memory component from the bit line external to the memory component (FIG. 4A, GBL; that is, when open, the switch isolates the LBL from the GBL; compare Yang FIG. 4A to FIG. 3A and page 11, lines 1-3 of the present application).
Regarding claim 4, Yang teaches the limitations of claim 1.
Yang further teaches each memory component comprises multiple bit cells connected to the compute engine (FIG. 3A shows multiple 6T SRAM Cells 121 connected to a common MAC 130; ¶[0003]) and each bit cell of the multiple bit cells is connected to a common bit line (¶[0003] teaches “The LBL is connected to a bit-line of each of the 6T SRAM cells”; see LBL connections in FIG. 4A) and to a different word line (¶[0072] teaches “one of the 6T cells is accessed by turning on the corresponding word line (WL)”; WLs are understood to be horizontal lines coupled to 6T SRAM Cells in FIGS. 4-7; each 6T cell in FIG. 4A is connected to a different WL).
Regarding claim 5, Yang teaches the limitations of claim 4.
Yang further teaches each bit cell in a memory component is connected directly to the compute engine (FIG. 4A, the MAC circuit, including transistor M1 (see ¶[0051]) is connected directly to each of the 6T Cells; see also FIG. 3A).
Regarding claim 11, Yang teaches the limitations of claim 1.
Yang further teaches for each memory component the compute engine is connected to the bit cell with the corresponding bit line (e.g., FIG. 4A shows the compute engine comprising M1 is connected to corresponding 6T Cells with local bit line LBL).
Regarding claim 12, Yang teaches the limitations of claim 1.
Yang further teaches the compute engine comprises a bit multiplier for multiplying bits stored in the bit cells to calculate a product and a product storage circuit that is or comprises a capacitor for storing the product (¶[0003] teaches “a charge-domain multiply-and-accumulate computing (MAC)” circuit “includes: a metal-oxide-semiconductor (MOS) transistor; an input switch; an output switch; an input port; an output port; and a capacitor”).
Claim Rejections - 35 USC § 103
10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
11. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yang, et al (US 20240045655 A1), hereinafter Yang, in view of Zhang, et al (US 20200174786 A1), hereinafter Zhang.
Regarding claim 3, Yang teaches the limitations of claim 2.
Yang does not teach the memory select (MEMSEL) switch of each memory component is controlled in common.
Zhang teaches the memory select (MEMSEL) switch of each memory component is controlled in common (FIG. 4 shows memory select switches 23 controlled in common such that an external bit line is simultaneously coupled to memory component 41; ¶[0040-0042]; see also FIG. 2).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Zhang into the method of Yang to include commonly-controllable memory component access switches. The ordinary artisan would have been motivated to modify Yang in the above manner for the purpose of supporting multi-bit MAC operations (Zhang ¶[0008]).
12. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yang, et al (US 20240045655 A1), hereinafter Yang, in view of Fujiwara, et al (US 20230315389 A1), hereinafter Fujiwara.
Regarding claim 6, Yang teaches the limitations of claim 1.
Yang does not teach a controller for controlling the memory components.
Fujiwara teaches a controller for controlling the memory components (FIG. 1, 38; ¶[0038]).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Fujiwara into the method of Yang to include a memory controller. The ordinary artisan would have been motivated to modify Yang in the above manner for the purpose of controlling operations of the compute-in-memory device (providing control signals to a read/write circuit to select bit lines, etc.) (Fujiwara ¶[0038]).
13. Claims 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yang, et al (US 20240045655 A1), hereinafter Yang, in view of Jia, et al (US 20230074229 A1), hereinafter Jia.
Regarding claim 7, Yang teaches the limitations of claim 1.
Yang does not explicitly teach a substrate (inherent to a semiconductor memory device) and wherein each memory component is spatially disposed on or over a different portion of the substrate and adjacent to another memory component.
Jia teaches substrate (¶[0011]) and wherein each memory component is spatially disposed on or over a different portion of the substrate and adjacent to another memory component (FIG. 21A; ¶[0041]).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Jia into the method of Yang to include compute-in-memory units (CIMUs) disposed adjacent to one another. The ordinary artisan would have been motivated to modify Yang in the above manner for the purpose of creating short, high-bandwidth face-to-face connections between the outputs of adjacent CIMUs (Jia ¶[0114]).
Regarding claim 8, Yang as modified by Jia teaches the limitations of claim 7.
Yang further teaches the compute engine of each memory component is disposed spatially adjacent to the bit cell or bit cells of the memory component (FIG. 3A shows the MAC circuit implemented separately from the 6T SRAM Cells while still part of the same IMC (see also FIG. 4A), and therefore one or more SRAM Cells must be located adjacent to the MAC).
Regarding claim 9, Yang as modified by Jia teaches the limitations of claim 7.
Yang as modified by Jia teaches at least one of the compute engines in the memory components is spatially disposed between the bit cell or bit cells of the memory component and the bit cell or bit cells of the adjacent memory component (Jia shows in FIG. 21A CIMUs physically adjacent to one another; Yang in FIG. 3A shows the MAC circuit implemented separately from the 6T SRAM Cells while still part of the same IMC (see also FIG. 4A), and therefore one or more SRAM Cells must be located adjacent to the MAC (FIG. 1 also implies adjacent placement of IMC units, in which the MACs in one slice would be adjacent to the bit cells in another slice); together, Yang and Jia teach adjacent “memory components” with a compute engine in one memory component adjacent to bit cells in another memory component).
Regarding claim 10, Yang as modified by Jia teaches the limitations of claim 7.
Jia further teaches each compute engine of a memory component is connected to the compute engine of an adjacent memory component (FIG. 2A shows input lines x connecting compute engines of different IMCs horizontally and output lines y connecting compute engines of different IMCs vertically).
14. Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Yang, et al (US 20240045655 A1), hereinafter Yang, in view of Jia, et al (US 20230074229 A1), hereinafter Jia, and further in view of Fujiwara, et al (US 20230315389 A1), hereinafter Fujiwara.
Regarding claim 13, Yang as modified by Jia teaches the limitations of claim 7.
Yang does not teach using the controller to provide a bit on each bit line.
Fujiwara teaches using the controller (FIG. 1, 38; ¶[0038]) to provide a bit on each bit line (referencing FIG. 1, ¶[0038] teaches “the memory controller 38 provides control signals to a read/write circuit 40 that is electrically connected to the bit-lines of the memory array 22 to select bit-lines, i.e., columns, of the memory array 22. The read/write circuit 40 receives and provides input/output (I/O) data.”).
using the controller to enable the word line of a column of memory components to store the bit into the bit cell of each memory component in the column of memory components (¶[0036] teaches “data is written into and read from the SRAM cell via one or more bit-lines, such as a bit-line (BL) and a complementary bit-line, referred to as bit-line bar (BLB). The data is written into and read from the SRAM cell upon activation of one or more access transistors in the SRAM cell by a word line (WL) signal.”); and
using the compute engine of each memory component in the column of memory components to process the stored bit (referencing FIG. 2, ¶[0043] teaches “The multiplication circuit 58 includes logic gates for multiplying the input data signal XIN that is received from the word line driver 56 and bits of data from the memory cells 52 and 54”).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Fujiwara into the method of Yang to include a memory controller. The ordinary artisan would have been motivated to modify Yang in the above manner for the purpose of controlling operations of the compute-in-memory device (providing control signals to a read/write circuit to select bit lines, etc.) (Fujiwara ¶[0038]).
Regarding claim 14, Yang as modified by Jia and Fujiwara teaches the limitations of claim 13.
Yang further teaches each memory component is connected to a corresponding bit line (FIG. 4A, GBL) through a memory select (MEMSEL) switch (S.sub.p) and comprising using the controller (i) to turn the MEMSEL switch on (FIG. 8A; ¶[0073] assumes switch S.sub.p is NMOS for this example) before using the controller to provide the bit on each bit line (FIG. 8A, switch S.sub.p is turned on the initiate the Precharge phase; ¶[0073]) and (ii) to turn the MEMSEL switch off after using the controller to provide the bit on each bit line before using the compute engine of each memory component in the column of memory components to process the stored bit (switch S.sub.p is turned off to initiate the multiplication phase, during which the bit provided on LBL is identified in the timing diagram; ¶[0073] teaches “it can be seen in FIG. 8A that the LBL has the value of VDD in the pre-charging phase (‘Precharge’ in the figure) and in the digital-to-analog conversion phase (‘DAC’ in the figure); if the data bit is 0,' then the LBL drops to GND in the multiplication phase (‘Multiplication’ in the figure) and rises to VDD in the accumulation phase (‘Accumulation’ in the figure); and if the data bit is ‘1,’ then the LBL remains at VDD in the multiplication phase and the accumulation phase”).
Regarding claim 15, Yang as modified by Jia and Fujiwara teaches the limitations of claim 13.
Jia further teaches (i) multiplying multiple bits of a first multi-bit value by a bit of a second multi-bit value in parallel; multiplying multiple bits of a first multi-bit value by a bit of a second multi-bit value in parallel; (iii) multiplying multiple bits of a first multi-bit value by a bit of a second multi-bit value in parallel; (iv) multiplying all of the bits of a first multi-bit value by a bit of a second multi-bit value in parallel; (v) multiplying multiple bits of a first multi-bit value by multiple bits of a second multi-bit value in parallel; (vi) multiplying all of the bits of a first multi-bit value by all of the bits of a second multi-bit value in parallel; (vii) storing bit products in capacitors and summing the bit products by connecting the capacitors in parallel; or (viii) iteratively summing and scaling bit products in an accumulating capacitor (FIG. 2A and ¶[0076] illustrate case (i) in which a single bit (e.g., x.sub.1) of multi-bit value x.sub.n is multiplied in parallel with multiple bits of multi-bit value a.sub.m,1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
Prosecution Insights