Prosecution Insights
Last updated: October 25, 2026
Application No. 19/100,889

PHOTOLITHOGRAPHY METHOD AND PHOTOLITHOGRAPHY SYSTEM

Non-Final OA §103§112
Filed
Feb 03, 2025
Priority
Aug 05, 2022 — CN 202210937838.8 +1 more
Examiner
KIM, PETER B
Art Unit
2882
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Shanghai Optoelectronics Science And Technology Innovation Center
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
10m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
810 granted / 975 resolved
+15.1% vs TC avg
Moderate +9% lift
Without
With
+9.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
23 currently pending
Career history
1000
Total Applications
across all art units

Statute-Specific Performance

§101
2.9%
-37.1% vs TC avg
§103
42.1%
+2.1% vs TC avg
§102
21.8%
-18.2% vs TC avg
§112
20.2%
-19.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 975 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claim 30 objected to because of the following informalities: on line 4, after “negative photoresist” instead of a semicolon, a period is used. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 26 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The structural relationship between the chromium adhesion layer, the gold film and the positive photoresist layer and the negative photoresist layer is not clear. It is also unclear at what point of the process a chromium film and gold film are provided. The specification simply declares in a step after development of the negative photoresist that the wafer is placed in an evaporation coater and a chromium film and gold film are thermally evaporated without disclosing that they were provided in the first place. In order to expedite prosecution, the metal films are provided for forming electrical patterns. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 20, 23, 24, 27 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (Hu ‘302) (2013/0234302). Regarding claim 20, Hu ‘302 discloses a photolithography method, wherein the method comprises: providing a substrate (300, Fig. 9, para 0029), forming a negative photoresist layer (302) on the substrate using a negative photoresist, and forming a positive photoresist layer (303) on the negative photoresist layer using a positive photoresist (para 0030); patterning the negative photoresist layer and the positive photoresist layer to form a positive pattern region (304) on the positive photoresist layer and a negative pattern region (305) on the negative photoresist layer (Fig. 10, para 0041); developing the positive photoresist layer with developer for positive photoresist to remove the positive photoresist in the positive pattern region (para 0047); and developing the negative photoresist layer with developer for negative photoresist to remove the negative photoresist located near the negative pattern region (para 0048), thereby providing an exposed region associated with a size of the positive pattern region and a size the negative pattern region, to expose the substrate (para 0047-0049). Although Hu does not disclose wherein a size of the positive pattern region is larger than a size of the negative pattern region, Hu discloses exposure light intensity distribution’s effect on the exposure regions of the positive and the negative layers (para 0041). Therefore, it would have been obvious to one of ordinary skill in the art to adjust the intensity distribution of the light and tuning the relative sensitivity of the two resist layers to obtain wider positive pattern region depending on the intended design. Regarding claim 23, Hu ‘302 discloses wherein under an exposure source, the positive photoresist layer and the negative photoresist layer are exposed by using a lithographic mask (50) with a template pattern or by focused direct writing, thereby forming a positive pattern region on the positive photoresist layer and a negative pattern region on the negative photoresist layer (para 0041-0044). Regarding claim 24, although Hu ‘302 does not explicitly disclose forming a pattern on the substrate through material deposition technology or etching technology, deposition or etching to form patterns in a substrate material is a routine step in semiconductor manufacturing art. Therefore, it would have been obvious to one of ordinary skill in the art to perform material deposition or etching to form patterns in a substrate material to building layers of circuits or electrical pathways. Regarding claim 27, Hu ‘302 discloses wherein the positive photoresist and the negative photoresist respond differently to exposure flux at specific wavelengths (para 0041). Regarding claim 28, Hu ‘302 discloses wherein the material of the substrate includes semiconductor, metal, insulator, polymer or composite material (para 0029). Claim(s) 20-25, 27-33 and 35-37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (Hu) (CN 103365094 in IDS, translation provide in the Office Action, the paragraph number in the rejection refers the translation). Regarding claim 20, Hu discloses a photolithography method, wherein the method comprises: providing a substrate (10, Fig. 8, para 0069), forming a negative photoresist layer (22’) on the substrate using a negative photoresist, and forming a positive photoresist layer (24’) on the negative photoresist layer using a positive photoresist (para 0069); patterning the negative photoresist layer and the positive photoresist layer to form a positive pattern region (241, Fig. 8) on the positive photoresist layer and a negative pattern region (221) on the negative photoresist layer (Fig. 8, para 0070); developing the positive photoresist layer with developer for positive photoresist to remove the positive photoresist in the positive pattern region (para 0071); and developing the negative photoresist layer with developer for negative photoresist to remove the negative photoresist located near the negative pattern region (para 0074), thereby providing an exposed region associated with a size of the positive pattern region and a size the negative pattern region, to expose the substrate (para 0071-0074). Although Hu does not disclose wherein a size of the positive pattern region is larger than a size of the negative pattern region, Hu discloses exposure light intensity distribution’s effect on the exposure regions of the positive and the negative layers (para 0070). Therefore, it would have been obvious to one of ordinary skill in the art to adjust the intensity distribution of the light and tuning the relative sensitivity of the two resist layers to obtain wider positive pattern region depending on the intended design. Regarding claim 30, Hu discloses a photolithography method (Fig. 8), wherein the method comprises: providing a substrate (10), forming a positive photoresist layer (22’) on the substrate using a positive photoresist, forming an interlayer (23) on the positive photoresist layer and forming a negative photoresist layer (24’) on the interlayer using a negative photoresist (para 0069); patterning the negative photoresist layer and the positive photoresist layer to form a positive pattern region (241, Fig. 8) on the positive photoresist layer and a negative pattern region (221) on the negative photoresist layer (Fig. 8, para 0070); developing the negative photoresist layer with developer for negative photoresist to remove the negative photoresist outside the negative pattern region (para 0074); developing the interlayer with developer for interlayer, or etching the interlayer with a pattern of the developed negative photoresist layer as an anti-etching mask, so that the pattern of the interlayer matches pattern of the developed negative photoresist layer (para 0059, 0072, 0073); and developing the positive photoresist layer with developer for positive photoresist to remove the positive photoresist at an edge portion of the positive pattern region (para 0071), thereby providing an exposed region associated with a size of the positive pattern region and a size of the negative pattern region, to expose the substrate. Although Hu does not disclose wherein a size of the positive pattern region is larger than a size of the negative pattern region, Hu discloses exposure light intensity distribution’s effect on the exposure regions of the positive and the negative layers (para 0070). Therefore, it would have been obvious to one of ordinary skill in the art to adjust the intensity distribution of the light and tuning the relative sensitivity of the two resist layers to obtain wider positive pattern region depending on the intended design. Regarding claim 21, Hu discloses wherein after forming the negative photoresist layer and before forming the positive photoresist layer, forming a interlayer (23) between the negative photoresist layer and the positive photoresist layer (para 0069, 0071). Regarding claim 22, Hu discloses wherein developing the interlayer with developer for interlayer, or etching the interlayer with a pattern of the developed positive photoresist layer as an anti-etching mask, so that the pattern of the interlayer matches pattern of the developed positive photoresist layer (para 0072, 0073). Regarding claims 23 and 31, Hu discloses wherein under an exposure source, the positive photoresist layer and the negative photoresist layer are exposed by using a lithographic mask (20, Fig. 8) with a template pattern or by focused direct writing, thereby forming a positive pattern region on the positive photoresist layer and a negative pattern region on the negative photoresist layer (para 0070). Regarding claims 24 and 32, although Hu does not explicitly disclose forming a pattern on the substrate through material deposition technology or etching technology, deposition or etching to form patterns in a substrate material is a routine step in semiconductor manufacturing art. Therefore, it would have been obvious to one of ordinary skill in the art to perform material deposition or etching to form patterns in a substrate material to building layers of circuits or electrical pathways. Regarding claims 25 and 33, Hu discloses wherein the wavelength of the exposure source is 1 to 500 nm (para 0005). Although Hu does not disclose wherein the temperature for the drying after the exposure is 30 to 300 °C, the typical temperature for drying and post exposure bake is 90-200 °C, and it would have been obvious to one of ordinary skill in the art to provide the claimed temperature range for drying depending on equipment design, air flow and materials since it has been held that discovering the optimum or workable ranges involves only routine skill in the art. Regarding claims 27 and 35, Hu discloses wherein the positive photoresist and the negative photoresist respond differently to exposure flux at specific wavelengths (para 0070). Regarding claims 28 and 36, although Hu does not explicitly disclose wherein the material of the substrate includes semiconductor, metal, insulator, polymer or composite material, the claimed material are well known conventional substrate materials and it would have been obvious to one of ordinary skill in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. Regarding claim 29 and 37, Hu discloses wherein the interlayer comprises an inorganic substance, a polymer, or a composite material (para 0013, 0016, 0046). Claim(s) 26 and 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (Hu) (CN 103365094 in IDS, translation provide in the Office Action, the paragraph number in the rejection refers the translation) as applied to claim 20 above, and further in view of Ishibashi et al. (Ishibashi) (2009/0159950). Regarding claims 26 and 34, although Hu does not disclose a chromium film, a gold film and a step of thermally evaporating a chromium film at a rate of 1 Å/s and thermally evaporating a gold film at a rate of 0.5 Å/s, wherein the chromium film is used as an adhesion layer for the gold film, using a gold film for a stable electrical conductor and a chromium film as an adhesion layer is well known in the art as disclosed in Ishibashi and evaporating the film (para 0265). Therefore, it would have been obvious to one of ordinary skill in the art to provide a gold film and a chromium film to the invention of Hu and evaporate the film in order to form a conductor pattern as taught by Ishibashi and to adjust the temperature and air flow during evaporation process to obtain the claimed evaporation rate. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Choi et al. (Choi) (KR 2003-0038142, translation provided with Office Action) discloses forming a negative photoresist layer, performing exposure using a reticle, developing the negative photoresist. Forming a positive photoresist layer on the resultant structure, performing exposure and developing the resultant structure (abstract). Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER B KIM whose telephone number is (571)272-2120. The examiner can normally be reached M-F 8:00 AM - 4:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Toan Ton can be reached at (571) 272-2303. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PETER B KIM/ Primary Examiner, Art Unit 2882 September 26, 2026
Read full office action

Prosecution Timeline

Feb 03, 2025
Application Filed
Sep 30, 2026
Non-Final Rejection mailed — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12769216
PROJECTION EXPOSURE APPARATUS FOR SEMICONDUCTOR LITHOGRAPHY HAVING A CONNECTING ELEMENT
2y 8m to grant Granted Oct 20, 2026
Patent 12761567
LITHOGRAPHIC PERFORMANCE QUALIFICATION AND ASSOCIATED APPARATUSES
2y 3m to grant Granted Oct 13, 2026
Patent 12761568
ENHANCING LITHOGRAPHY OPERATION FOR MANUFACTURING SEMICONDUCTOR DEVICES
2y 2m to grant Granted Oct 13, 2026
Patent 12743022
PROJECTION LENS, PROJECTION EXPOSURE APPARATUS AND PROJECTION EXPOSURE METHOD
2y 2m to grant Granted Sep 22, 2026
Patent 12730388
METROLOGY METHOD AND APPARATUS
2y 6m to grant Granted Sep 08, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
92%
With Interview (+9.4%)
2y 6m (~10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 975 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month