DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 02/05/2025. Claims 1-15 are pending in the Application, of which Claims 1 and 14 are independent.
Continuity Priority information
The present Application 19101328 filed 02/05/2025 is a National Stage entry of PCT/JP2023/028833, International Filing Date: 08/07/2023 which Claims Priority from Provisional Application 63395552, filed 08/05/2022.
Information Disclosure Statement
The information disclosure statement (IDS), submitted on 02/05/2025, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Barnes et al. (Pub. No. US 20220247386) Pub. Date: 2022-08-04.
Regarding independent Claims 1 and 14, Barnes discloses noise mitigation circuitry and method for quantum computers, comprising:
a bi-chromatic recovery drive generator in communication with a quantum material, that sends a waveform to the quantum material.
Exemplary Noise Mitigation Circuitry. [0055] FIG. 4 illustrates an exemplary noise mitigation circuitry 400. In various embodiments, controller 30 may control one or more signal generators 410 to cause signals (e.g., voltage signals) to be generated and applied to electrical circuitry (e.g., noise mitigation circuitry 400) before being applied to electrical components (e.g., electrodes 440) of a system configured to perform multiple functions that have differing tolerances and/or requirements.
[0045] For example, controller 30 may cause a controlled evolution of quantum states of one or more atomic objects within the confinement apparatus to execute a quantum circuit and/or algorithm. In various embodiments, the atomic objects confined within the confinement apparatus are used as qubits corresponding to “quantum material” of the quantum computer 110.
[0056] As described above, the application of the signals to the electrodes 440 causes a potential field to be generated that may cause one or more functions to be performed on atomic objects, corresponding to “quantum material” i.e. qubit, captured within an ion trap 70. In an example embodiment, a signal generator 410 includes one or more waveform generators, which may be, for example, an arbitrary waveform generator (AWG) or a digital-to-analog converter (DAC).
Regarding Claims 2, 3, 9, 10, 12, 15, Barnes discloses the quantum material comprises multi-level spins, wherein the spins are qubits.
[0013] In various embodiments, the ion trap is configured to have a plurality of ions trapped therein, and wherein at least some of the plurality of the ions trapped therein are used as qubits of the quantum computer. [0044] FIG. 1. For example, the voltage sources 50 may comprise one or more signal generators, such as, for example, signal generator 410 of FIG. 4. The voltage sources 50 may be electrically coupled to the corresponding potential generating elements of the confinement apparatus (e.g., ion trap 70) via, for example, one or more stages of electrical circuitry (e.g., gain stage, a filter stage, and/or a sample stage), which may be in series or parallel to other stages. The gain stage and/or the filter stage may shape the signal(s) being applied to the electrodes of an ion trap that traps atomic objects used as the qubits of the quantum computer 110.
[0055] FIG. 4 In various other embodiments, noise mitigation circuitry 400 may provide a signal to multiple electrodes 440 of a quantum computer 110 (not depicted). The noise mitigation circuitry 400 may be configured to shape and/or condition a signal applied to one or more electrodes 440 of the ion trap 70.
Regarding Claims 4-6, Barnes discloses electromagnetic fields; [0003] For example, an ion trap can use a combination of electrical and magnetic fields to capture a plurality of ions in a potential well. Various functions may be performed to cause the ions to move in particular ways through portions of the ion trap and/or be contained in a particular portion of the ion trap. These various functions may have differing noise tolerances in the signals used to generate the combination of electrical and magnetic fields and/or heat tolerances for the electrical components. [0056] As described above, the application of the signals to the electrodes 440 causes a potential field to be generated that may cause one or more functions to be performed on atomic objects captured within an ion trap 70.
Regarding Claims 7, 8, 11, 13, Barnes discloses wherein the noise is either static spatially inhomogeneous noise, and wherein the waveform corrects for static noise.
[0071] In the embodiment depicted in FIG. 10, the exemplary noise mitigation circuitry including feedback circuitry 1000 may be comprised of additional switches (e.g., switch 1010 and switch 1020) and a converter 1030. In an exemplary embodiment, converter 1030 is an analog-to-digital converter. The use of switches allows for one or more portions of the noise mitigation circuitry to be isolated, which may be used in calibrating, characterizing, or diagnosing the noise mitigation circuitry. This may be done by the output of the switches, as depicted in FIG. 10, being input to a converter 1030. The signal input into converter 1030 may be converted from an analog signal to a digital signal in order to, for example, determine characteristics about the noise mitigation circuitry that allows for the calibration of signals output by signal generator 410 or diagnosing the noise mitigation circuitry.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: July 16, 2026
Non-Final Rejection 20260715
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
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