DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the application 19/104526 filed on 02/18/2025.
Claims 1-15 have been examined and are pending in this application.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. PCT/EP2023/072880, filed on 08/21/2023, and claims priority to European Patent Application No. 22191189.4, filed on 08/19/2022.
Information Disclosure Statement
The information disclosure statement (IDS), submitted on 12/18/2025, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawing Objections
The drawings are objected to because they are not informative. Block diagrams, illustrated in figures 1-4, should include texts described names/labels for each block/box. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1 and 11-14 are objected to because of the following informalities:
Regarding claims 3 and 11; claims 3 and 11 recite the limitations "RISC-V," "R-type," and "Funct7". The acronym RISC-V, R-type, and Funct7 are recited without spelling out in full at its first occurrence. The examiner notes for acronym RISC-V, R-type, and Funct7 should be spelled out with its first occurrence. Appropriate correction is required.
Regarding claims 5, 8, 13 and 15; claims 5, 8, 13 and 15 recite the limitation "DRAM". The acronym DRAM is recited without spelling out in full at its first occurrence. The examiner notes for acronym DRAM should be spelled out with its first occurrence. Appropriate correction is required.
Regarding claim 6; claim 6 recites the limitation "XOR". The acronym XOR is recited without spelling out in full at its first occurrence. The examiner notes for acronym XOR should be spelled out with its first occurrence. Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 10-15 are rejected under 35 USC 101 as being directed to an abstract idea without being integrated into a practical application or being significantly more.
Regarding claim 10, the claim recites the limitations “receiving an application code …” and “assembling the digital key from the at least two key parts;” Broadly interpreted, the aforementioned steps are directed to mental processes as said steps could be performed in the human mind. Therefore, the claims recite an abstract idea.
Said abstract idea and/or judicial exception is not integrated into a practical application as the claim does not recite any other active steps that could be considered that the abstract idea is being integrated into a practical application. It’s noted that the claim recites the operations “receiving an application code.” However, said operations are not sufficient to consider that the abstract idea is being interpreted into a practical application. Said operations are recited at a high level of generality of data gathering/processing/storing, which are a form of insignificant extra-solution activity.
It’s also noted that the claims recite additional limitation/elements (i.e., processor unit, computer system etc.,). However, said additional elements are recited at a high-level of generality (i.e., as a generic computing device performing a generic computer functions) such that it amounts no more than mere instructions to apply the exception or abstract idea using generic computer components. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea.
The claims do not include additional elements/limitations/embodiments that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as an ordered combination do not amount to significantly more than the abstract idea. As mentioned above, although the claims recite additional elements, said elements taken individually or as a combination, do not result in the claim amounting to significantly more than the abstract idea because as the additional elements perform generic computer content distributing functions routinely used in information technology field. As discussed above, the additional elements recited at a high-level of generality such that they amount no more than mere instructions to apply the exception using a generic computer component. Therefore, the claim is directed to non-statutory subject matter.
Regarding claims 11-15, claims 11-15 are also rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter for the same reasons addressed above as the claims recite an abstract idea and the claims do not positively recite any other operations that could be considered as the abstract idea is being integrated into a practical application or significantly more. It’s noted that claim 12 recites the limitations: “calculating a first key ….” Said steps are either directed to mental processes and/or in a form of insignificant extra-solution activities; The aforementioned steps are not sufficient to consider that the abstract idea is being integrated into a practical application or significantly more. Therefore, claims 11-15 are also rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Kipnis et al. (“Kipnis,” US 2013/0272521) in view of Myles (US 2009/0113553).
Regarding claim 1: Kipnis discloses a method for providing a digital key to a processor unit using a computer system, the digital key being provided within an application code, and a sequence of instructions being stored in the application code, the method comprising the following steps:
- generating a digital key to be provided by a computer system (Kipnis: par. 0030 the meta-secret is used both to generate multiple cryptographic keys and to generate multiple sets of secret-shares);
- splitting the digital key into at least two key parts (Kipnis: par. 0032 the sets of secret-shares typically (although not necessarily) with two secret-shares in each set-are distributed).
Kipnis does not explicitly disclose embedding the key parts in at least two instructions of the application code and transmitting the application code from the computer system to the processor unit.
However, Myles discloses embedding the key parts in at least two instructions of the application code (Myles: par. 0039 a secret message 208 is received by a message encoder 210, which converts the message into a form that is suitable for insertion into the executable code 202); and
- transmitting the application code from the computer system to the processor unit (Myles: par. 0039 the encoded message is then received by the message embedder 204 where an insertion module 212 inserts the encoded message into the executable code).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Myles with the system/method of Kipnis to include embedding the key parts in at least two instructions of the application code. One would have been motivated to provide computer implemented steganographic and watermarking techniques for encoding secret information in arbitrary program binaries (Myles: par. 0001).
Regarding claim 2: Kipnis in Myles discloses the method according to claim 1.
Myles further discloses wherein embedding the key parts in at least two instructions of the application code comprises embedding the key portions in specific fields of the instructions that typically remain unused (Myles: par. 0030 hides information in arbitrary program binaries. This is done by identifying stalls in the instruction processing pipeline. Instead of filling these stalls with no operation (nop) instructions the stalls are filled with instructions which will not adversely alter the functionality of the program, but which encode a hidden message).
The motivation is the same that of claim 1 above.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kipnis et al. (“Kipnis,” US 2013/0272521) in view of Myles (US 2009/0113553) and LUO (“Luo,” US 2023/0267079).
Regarding claim 3: Kipnis in Myles discloses the method according to claim 1.
Kipnis in Myles does not explicitly disclose wherein the application code is designed as a RISC-V application code, the instructions being designed in particular as R-type instructions and the embedding of the key parts being preferably carried out in Funct7 fields.
However, Luo discloses wherein the application code is designed as a RISC-V application code, the instructions being designed in particular as R-type instructions and the embedding of the key parts being preferably carried out in Funct7 fields (Luo: par. 0036 the instructions output by the coprocessor may be R-type instructions in an RISC-V instruction set. The domain of the R-type instruction is 32 bits, including [] 7-bit func7).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Luo with the system/method of Kipnis and Myles to include the application code is designed as a RISC-V application code, the instructions being designed in particular as R-type instructions. One would have been motivated to providing executing data processing on a plurality of channels or fields (Luo: par. 0002).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kipnis et al. (“Kipnis,” US 2013/0272521) in view of Myles (US 2009/0113553) and ZEH et al. (“Zeh,” US 2021/0075606).
Regarding claim 4: Kipnis in Myles discloses the method according to claim 1.
Kipnis further discloses wherein generating the digital key to be provided by the computer system comprises the following steps:
- generating a first key containing secret information to be transmitted to the processor unit (Kipnis: par. 0018 the processors are configured to cooperate in using all the secret-shares together with any one of the key identifiers to generate the associated cryptographic key, so as to enable a cryptographic operation to be performed using the cryptographic key).
Kipnis in view of Myles does not explicitly disclose reading a hardware identifier, the hardware identifier comprising a unique identifier of the processor unit and calculating the digital key to be provided from the first key and the hardware identifier.
However, Zeh discloses reading a hardware identifier, the hardware identifier comprising a unique identifier of the processor unit (Zeh: par. 0054 a hardware identifier (e.g., a chip-unique ID or serial number)); and
- calculating the digital key to be provided from the first key and the hardware identifier (Zeh: par. 0054 the hardware identifier is integrated in the calculation of the key thereby “binding” a given key to a certain hardware device, such as a microcontroller).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Zeh with the system/method of Kipnis and Myles to include calculating the digital key to be provided from the first key and the hardware identifier. One would have been motivated to perform authenticity validation check on the unique ID and microcontroller using the external public key (Zeh: par. 0008).
Claims 5 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kipnis et al. (“Kipnis,” US 2013/0272521) in view of Myles (US 2009/0113553), ZEH et al. (“Zeh,” US 2021/0075606) and LUO (“Luo,” US 2023/0267079).
Regarding claim 5: Kipnis in Myles and Zeh discloses the method according to claim 4.
Kipnis in Myles and Zeh does not explicitly disclose wherein the hardware identifier comprises specific information of a DRAM memory element of the processor unit.
However, Luo discloses wherein the hardware identifier comprises specific information of a DRAM memory element of the processor unit (Luo: par. 0062 the AXI request, may read the data to be moved from the SRAM and perform data moving, or may read the data to be moved from the DRAM and perform data moving).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Luo with the system/method of Kipnis, Myles and Zeh to include the hardware identifier comprises specific information of a DRAM memory element of the processor unit. One would have been motivated to providing executing data processing on a plurality of channels or fields (Luo: par. 0002).
Regarding claim 8: Kipnis in Myles and Zeh discloses the method according to claim 7.
Kipnis in Myles and Zeh does not explicitly disclose wherein the hardware identifier comprises information about the specific charging time of the capacitors of the DRAM memory element or information about the latency times of the DRAM memory element.
However, Luo discloses wherein the hardware identifier comprises information about the specific charging time of the capacitors of the DRAM memory element or information about the latency times of the DRAM memory element (Luo: par. 0059 the size of available space of the storage region in the instruction virtual channel storage circuit may be reflected in real time by dynamically adjusting the numerical value of the credit number counter).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Luo with the system/method of Kipnis, Myles and Zeh to include information about the specific charging time of the capacitors of the DRAM memory element. One would have been motivated to providing executing data processing on a plurality of channels or fields (Luo: par. 0002).
Regarding claim 9: Kipnis in Myles and Zeh discloses the method according to claim 4.
Kipnis in Myles and Zeh does not explicitly disclose wherein the hardware identifier is determined by a machine learning-based method.
However, Luo discloses wherein the hardware identifier is determined by a machine learning-based method (Luo: par. 0034 a Neural-network Processing Unit (NPU, or a neural-network Processor) system of a complex row stationary data flow).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Luo with the system/method of Kipnis, Myles and Zeh to include the hardware identifier is determined by a machine learning-based method. One would have been motivated to providing executing data processing on a plurality of channels or fields (Luo: par. 0002).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kipnis et al. (“Kipnis,” US 2013/0272521) in view of Myles (US 2009/0113553), ZEH et al. (“Zeh,” US 2021/0075606) and Yang (US 2020/0322793).
Regarding claim 6: Kipnis in Myles and Zeh discloses the method according to claim 4.
Kipnis in Myles and Zeh does not explicitly disclose wherein calculating the digital key to be provided from the first key and the hardware identifier comprises applying an XOR operation to the first key and the hardware identifier.
However, Yang discloses wherein calculating the digital key to be provided from the first key and the hardware identifier comprises applying an XOR operation to the first key and the hardware identifier (Yang: par. 0040 the device 102 may generate the dynamic encryption key using the pair device identifiers and a bitwise XOR function).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Yang with the system/method of Kipnis, Myles and Zeh to include applying an XOR operation to the first key and the hardware identifier. One would have been motivated to generating a dynamic encryption key for exchanging the encrypted device identifiers between devices to set up a multi-factor dynamic key (Yang: par. 0008).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kipnis et al. (“Kipnis,” US 2013/0272521) in view of Myles (US 2009/0113553) and ZEH et al. (“Zeh,” US 2021/0075606).
Regarding claim 7: Kipnis in Myles and Zeh discloses the method according to claim 4.
Zeh further discloses wherein the hardware identifier is designed as a temperature-dependent hardware identifier (Zeh: par. 0098 steps may be executed by (or using) a hardware apparatus, like for example, [] an electronic circuit).
The motivation is the same that of claim 4 above.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Myles (US 2009/0113553) in view of Kipnis et al. (“Kipnis,” US 2013/0272521).
Regarding claim 10: Myles discloses a method for reconstructing a digital key by a processor unit, comprising the following steps:
- receiving an application code from a computer system (Myles: par. 0038 executable code 202 is received by a message embedder 204); a sequence of instructions and a digital key being stored in the application code (Myles: par. 0039 a secret message 208 is received by a message encoder 210, which converts the message into a form that is suitable for insertion into the executable code 202).
Myles does not explicitly disclose the digital key comprising at least two key parts that are not contiguously stored in the application code and assembling the digital key from the at least two key parts.
However, Kipnis discloses the digital key comprising at least two key parts that are not contiguously stored in the application code (Kipnis: par. 0030 the meta-secret is used both to generate multiple cryptographic keys and to generate multiple sets of secret-shares; par. 0032 the sets of secret-shares typically (although not necessarily) with two secret-shares in each set-are distributed); and
- assembling the digital key from the at least two key parts (Kipnis: par. 0028 assemble multiple secret-shares in order to generate the desired key).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Kipnis with the system/method of Myles to include assembling the digital key from the at least two key parts. One would have been motivated to providing digital communications for secure transmission and reception of digital information (Kipnis: par. 0001).
Claims 11, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Myles (US 2009/0113553) in view of Kipnis et al. (“Kipnis,” US 2013/0272521) and LUO (“Luo,” US 2023/0267079).
Regarding claim 11 (claim 3): Myles in view of Kipnis discloses the method according to claim 10.
Myles in view of Kipnis does not explicitly disclose wherein the application code is designed as a RISC-V application code, the instructions being designed in particular as R-type instructions and the embedding of the key parts being preferably carried out in Funct7 fields.
However, Luo discloses wherein the application code is designed as a RISC-V application code, the instructions being designed in particular as R-type instructions and the embedding of the key parts being preferably carried out in Funct7 fields (Luo: par. 0036 the instructions output by the coprocessor may be R-type instructions in an RISC-V instruction set. The domain of the R-type instruction is 32 bits, including [] 7-bit func7).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Luo with the system/method of Myles and Kipnis to include the application code is designed as a RISC-V application code, the instructions being designed in particular as R-type instructions. One would have been motivated to providing executing data processing on a plurality of channels or fields (Luo: par. 0002).
Regarding claim 13 (claim 5): Myles in view of Kipnis discloses the method according to claim 10.
Myles in view of Kipnis does not explicitly disclose wherein the hardware identifier comprises specific information of a DRAM memory element of the processor unit.
However, Luo discloses wherein the hardware identifier comprises specific information of a DRAM memory element of the processor unit (Luo: par. 0062 the AXI request, may read the data to be moved from the SRAM and perform data moving, or may read the data to be moved from the DRAM and perform data moving).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Luo with the system/method of Myles and Kipnis to include the hardware identifier comprises specific information of a DRAM memory element of the processor unit. One would have been motivated to providing executing data processing on a plurality of channels or fields (Luo: par. 0002).
Regarding claim 15 (claim 8): Myles in view of Kipnis discloses the method according to claim 10.
Myles in view of Kipnis does not explicitly disclose wherein the hardware identifier comprises information about the specific charging time of the capacitors of the DRAM memory element or information about the latency times of the DRAM memory element.
However, Luo discloses wherein the hardware identifier comprises information about the specific charging time of the capacitors of the DRAM memory element or information about the latency times of the DRAM memory element (Luo: par. 0059 the size of available space of the storage region in the instruction virtual channel storage circuit may be reflected in real time by dynamically adjusting the numerical value of the credit number counter).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Luo with the system/method of Myles and Kipnis to include information about the specific charging time of the capacitors of the DRAM memory element. One would have been motivated to providing executing data processing on a plurality of channels or fields (Luo: par. 0002).
Claims 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Myles (US 2009/0113553) in view of Kipnis et al. (“Kipnis,” US 2013/0272521) and ZEH et al. (“Zeh,” US 2021/0075606).
Regarding claim 12: Myles in view of Kipnis discloses the method according to claim 10.
Myles in view of Kipnis does not explicitly disclose wherein the method further comprises the following step: calculating a first key containing secret information from the digital key received from the computer system and a hardware identifier of the processor unit.
However, Zeh discloses wherein the method further comprises the following step:
- calculating a first key containing secret information from the digital key received from the computer system and a hardware identifier of the processor unit (Zeh: par. 0008 a microcontroller having a unique identifier (ID) and a first key pair including a microcontroller secret key and a microcontroller public key; par. 0054 the hardware identifier is integrated in the calculation of the key thereby “binding” a given key to a certain hardware device, such as a microcontroller).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Zeh with the system/method of Myles and Kipnis to include calculating a first key containing secret information from the digital key received from the computer system and a hardware identifier of the processor unit. One would have been motivated to perform authenticity validation check on the unique ID and microcontroller using the external public key (Zeh: par. 0008).
Regarding claim 14 (claim 7): Myles in view of Kipnis discloses the method according to claim 10.
Myles in view of Kipnis does not explicitly disclose wherein the hardware identifier is designed as a temperature-dependent hardware identifier.
However, Zeh discloses wherein the hardware identifier is designed as a temperature-dependent hardware identifier (Zeh: par. 0098 steps may be executed by (or using) a hardware apparatus, like for example, [] an electronic circuit).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Zeh with the system/method of Myles and Kipnis to include the hardware identifier is designed as a temperature-dependent hardware identifier. One would have been motivated to perform authenticity validation check on the unique ID and microcontroller using the external public key (Zeh: par. 0008).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Fahimeh Mohammadi whose telephone number is (571)270-7857. The examiner can normally be reached Monday - Friday 9:00 - 5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Luu Pham can be reached at 5712705002. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FAHIMEH MOHAMMADI/ Examiner, Art Unit 2439
/LUU T PHAM/Supervisory Patent Examiner, Art Unit 2439
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