DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-7, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Richter (U.S. Publication 2020/0379936), hereinafter Richter in view of Hollis (U.S. Publication 2019/0287584), hereinafter Hollis.
Referring to claim 1, Richter teaches, as claimed, a memory component, comprising:
a plurality of command/address (CA) interfaces (see Fig. 4A and 6B); and
a plurality of data (DQ) interfaces ((DQ) channels, see Paragraph 43) each comprising a plurality of DQ signal groups (data channels 190… coupled with a memory array 170; see Paragraph 43 and see Fig. 1, 170-a, 170-b, … 170-N), the memory component configurable to operate at least two CA interfaces (see Fig. 4A, CA_A and CA_B) in association with respective sets of DQ signal groups (N groups) that are non-overlapping sets of DQ signal groups (Note 170-a not overlapping with 170-b), to form respective memory channels, wherein at least two of the memory channels have
Richter does not disclose expressly different DQ signal widths.
Hollis does disclose different DQ signal widths (a first width and second width; see Abstract).
At the time of the invention it would have been obvious to a person of ordinary skill in the art to incorporate Hollis width modulation schemes in each Richter’s memory channels.
The suggestion/motivation for doing so would have been to establish compatibility with multiple memory types (memory stack may be utilized for different memory configurations; see Paragraph 17).
As to claim 5, the modification teaches the memory component of claim 1, wherein at least two of the respective memory channels are configurable to be operated at different clock frequencies (the clock signal may be a different signal; see Paragraph 42).
As to claim 6, the modification teaches the memory component of claim 1, wherein at least two of the respective memory channels are configurable to be operated using different data block sizes (depend on size of the memory array, see Paragraph 58).
As to claim 7, the modification teaches the memory component of claim 1, wherein at least two of the respective memory channels are configurable to be operated using different numbers of unit intervals (32 pins or 16 pins, see Paragraph 53) to communicate data bursts (outputs data in bursts, see Paragraph 53).
As to claim 16, it is directed to a method to implement the device as set forth in claim 1. Therefore, it is rejected on the same basis as set forth hereinabove.
As to claim 17, the modification teaches the method of claim 16, further comprising:
accessing, via the first memory channel (see Richter Fig. 4A, Channel A) and using the first set of DQ interface signals (see Richter Fig. 4A, Data A), a first set of memory arrays (see Richter Fig. 4A, Memory Array Channel A); and
accessing, via the second memory channel (see Richter Fig. 4A, Channel B) and using the second set of DQ interface signals (see Richter Fig. 4A, Data B), a second set of memory arrays (see Richter Fig. 4A, Memory Array Channel B).
As to claim 18, the modification teaches the method of claim 17, wherein the first set of memory arrays and the second set of memory arrays are non-overlapping sets (see Richter Fig. 4A; Note, no overlapping are illustrated).
As to claim 19, the modification teaches the method of claim 18, wherein the first set of memory arrays and the second set of memory arrays are disposed on different integrated circuit die (multiple die sizes, see Paragraph 50).
As to claim 20, the modification teaches the method of claim 16, further comprising: configuring the first set of DQ interface signals to operate as part of the second memory channel (alternatively, see Paragraph 65).
Allowable Subject Matter
Claims 2-4 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 8-15 are allowed.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hyun Nam whose telephone number is (571) 270-1725 and fax number is (571) 270-2725. The examiner can normally be reached on Monday through Friday 8:30 AM to 5:00 PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HYUN NAM/Primary Examiner, Art Unit 2183
Prosecution Insights