DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-4, 8, 15, 17, and 18 have been amended.
Claims 1-11 and 15-21 have been examined.
The specification, drawing, and claim objections in the previous Office Action have been addressed and are withdrawn.
The § 112 rejections in the previous Office Action have been addressed and are withdrawn.
Information Disclosure Statement
The applicant's submission of the Information Disclosure Statement dated June 24, 2026 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. A copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-11, 15-17, and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 10,747,535 by Reddy et al. (hereinafter referred to as “Reddy”) in view of US Patent No. 5,987,561 by Witt et al. (hereinafter referred to as “Witt”).
Regarding claims 1 and 15, taking claim 1 as representative, Reddy discloses:
an instruction control apparatus, comprising: an instruction decoder configured to decode a memory access instruction, wherein the memory access instruction is configured to read data from a source end storage circuit and write the data into a destination end storage circuit, and wherein a dependency between the memory access instruction and a preceding instruction comprises …a destination end dependency on the destination end storage circuit (Reddy discloses, at Figure 2 and related description, a processor, which discloses an instruction control apparatus, that includes a decoder, which discloses decoding instructions. As disclosed at Figure 1 and related description, the instructions include loads and stores, i.e., memory access instructions configured to read data from a source and write the data into a destination. Reddy also discloses, at Figure 2 and related description, dependencies between loads and earlier stores with regard to the targets, i.e. destination end.);
an instruction cache unit configured to cache the decoded memory access instruction (Reddy discloses, at Figure 2 and related description, a reorder buffer that stores instructions and data associated with loads and stores.); and
an instruction transmission controller configured to transmit the memory access instruction in the instruction cache unit to read the data from the source end storage circuit and cache the data to a data cache in response to… existence of the destination end dependency, send, to the data cache a blocking signal to cause the data cache to block the data read by the memory access instruction to the data cache from returning to the destination end storage circuit (Reddy discloses, at Figure 2 and related description, a load store unit that transmits loads and stores, i.e., memory access instructions, to read data from a source. The load store unit stores the data associated with speculatively executed instructions in the reorder buffer until the instructions become non-speculative, which discloses sending a blocking signal. Then the data is written to its destination when the instruction is retired, or committed. Dependencies between destinations of successive memory access instructions is one example of conditions that must resolve prior to an instruction becoming non-speculative. See, e.g., col. 10, line62-col. 11, line 4.).
Reddy does not explicitly disclose a source end dependency on the source end storage circuit and release of the source end dependency.
However, in the same field of endeavor (e.g., processors) Witt discloses:
checking source and destination dependencies (Witt discloses, at col. 136, lines 54-66, checking source and destination dependencies, which discloses releasing the source end dependency.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Reddy to include Witt’s checking of both ends for dependencies in order to ensure correct operation in the presence of different kinds of dependencies.
Regarding claims 2 and 16, taking claim 2 as representative, Reddy discloses the elements of claim 1, as discussed above. Reddy also discloses:
a dependency recording circuit configured to record dependency relationship of a storage resource of the memory access instruction (Reddy discloses, at Figure 2 and related description, the LSU checks dependencies, which discloses recording the dependency relationships of a storage resource of a memory access instruction.); and
the instruction transmission controller further configured to send a release signal for releasing the data read by the memory access instruction to the data cache when it is determined that the dependency on the destination end storage circuit has been released based on the dependency relationship recorded by the dependency recording unit (Reddy discloses, at Figure 2 and related description, the LSU commits the instructions that were speculatively executed once their dependencies are resolved.).
Regarding claims 3 and 17, taking claim 3 as representative, Reddy discloses the elements of claim 2, as discussed above. Reddy also discloses:
the instruction transmission controller is further configured to determine whether… the destination end dependency exists based on the dependency relationship recorded by the dependency recording circuit (Reddy discloses, at Figure 2 and related description, the LSU checks dependencies on sources and destinations, which discloses the instruction transmission controller is further configured to determine whether only dependency on a destination end storage circuit exists between the memory access instruction and the preceding instruction based on the dependency relationship record of the dependency recording unit.).
Reddy does not explicitly disclose a source end dependency having been released.
However, in the same field of endeavor (e.g., processors) Witt discloses:
checking source and destination dependencies (Witt discloses, at col. 136, lines 54-66, checking source and destination dependencies, which discloses releasing the source end dependency.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Reddy to include Witt’s checking of both ends for dependencies in order to ensure correct operation in the presence of different kinds of dependencies.
Regarding claims 5 and 19, taking claim 5 as representative, Reddy discloses the elements of claim 1, as discussed above. Reddy does not explicitly disclose the instruction decoder is further configured to: suspend decoding of subsequent instructions in response to receiving a signal indicating that the data cache space is insufficient.
However, in the same field of endeavor (e.g., processors) Witt discloses:
stalling decoding based on a buffer being full (Witt discloses, a col. 85, lines 29-34, stalling decoding if a buffer is full.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Reddy to include stalling decoding in response to a buffer filling up in order to improve performance by ensuring correct operation and preventing overflow.
Regarding claims 6 and 20, taking claim 6 as representative, Reddy discloses the elements of claim 1, as discussed above. Reddy also discloses:
the preceding instruction and the memory access instruction are in the same instruction queue or in different instruction queue (Reddy discloses, at Figure 2 and related description, load and store instructions stored in load and store queues, which discloses the preceding instruction and the memory access instruction are in the same instruction queue or in different instruction queue.).
Regarding claims 7 and 21, taking claim 7 as representative, Reddy discloses the elements of claim 1, as discussed above. Reddy also discloses:
the data cache is a reordering cache (Reddy discloses, at Figure 2 and related description, storing the data in a reorder buffer.).
Regarding claim 8, Reddy discloses:
a data cache configured to: cache data read by a memory access instruction (Reddy discloses, at Figure 2 and related description, storing data read by a load instruction in a reorder buffer.); and
in response to receiving a blocking signal to block the data read by the memory access instruction, block the data read by the memory access instruction from returning to a destination end storage circuit of the memory access instruction (Reddy discloses, at Figure 2 and related description, retaining data in the reorder buffer until dependencies are resolved.).
Regarding claim 9, Reddy discloses the elements of claim 8, as discussed above. Reddy also discloses:
in response to receiving a release signal to release the data read by the memory access instruction, return the data to the destination end storage circuit of the memory access instruction (Reddy discloses, at Figure 2 and related description, retaining data in the reorder buffer until dependencies are resolved.).
Regarding claim 10, Reddy discloses the elements of claim 8, as discussed above. Reddy does not explicitly disclose in response to the amount of data blocked in the data cache exceeding a predetermined threshold, send a signal indicating that the data cache space is insufficient to an instruction decoder to suspend decoding of subsequent instructions.
However, in the same field of endeavor (e.g., processors) Witt discloses:
stalling decoding based on a buffer being full (Witt discloses, a col. 85, lines 29-34, stalling decoding if a buffer is full.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Reddy to include stalling decoding in response to a buffer filling up in order to improve performance by ensuring correct operation and preventing overflow.
Regarding claim 11, Reddy discloses the elements of claim 8, as discussed above. Reddy also discloses:
the data cache is a reordering cache (Reddy discloses, at Figure 2 and related description, storing the data in a reorder buffer.).
Claims 4 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Reddy in view of Witt in view of US Publication No. 2014/0032828 by Khailany et al. (hereinafter referred to as “Khailany”).
Regarding claims 4 and 18, taking claim 4 as representative, Reddy discloses the elements of claim 3, as discussed above. Reddy also discloses:
the dependency recording circuit is further configured to update the dependency relationship of the source end storage circuit in response to receiving a dependency release signal for the source end storage circuit, wherein the dependency release signal is a synchronization release signal for the source end storage circuit, the synchronization release signal is based on storage range accessible by an instruction stream of each consumption end…, and the synchronization release signal released separately for a production end according to the storage range (Reddy discloses, at Figure 2 and related description, checking dependencies for each source and destination, which encompasses doing so for producer and consumer instructions in an instruction stream, and releasing consumer instructions when associated producer instructions are committed, which discloses the dependency recording unit is further configured to update the dependency relationship of the source end storage circuit in response to receiving a dependency release signal for the source end storage circuit, wherein the dependency release signal is a synchronization release signal for the source end storage circuit, and the synchronization release signal is based on storage range accessible by an instruction stream of each consumption end…, and is released separately for a production end according to the storage range.).
Reddy does not explicitly disclose a synchronization instruction.
However, in the same field of endeavor (e.g., copying data) Khailany discloses:
synchronization instructions (Khailany discloses, at ¶ [0041], synchronization instructions.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Reddy to include synchronization instructions, as disclosed by Khailany, in order to improve performance by avoiding race conditions. See Khailany, ¶ [0019].
Response to Arguments
On pages 11-16 of the response filed June 29, 2026 (“response”), the Applicant presents arguments related to drawing objections, specification objections, claim objections, claim interpretation under § 112(f), and § 112 rejections.
These remarks have been fully considered and, in light of the claim amendments presented in the response, are deemed persuasive. Therefore, the objections, interpretation, and rejections are withdrawn.
On page 18 of the response the Applicant argues, “Reddy does not disclose that a dependency between the memory access instruction and the preceding instruction comprises a source end dependency on the source end storage circuit and a destination end dependency on the destination end storage circuit, nor does Reddy disclose transmitting the memory access instruction in response to release of the source end dependency and existence of the destination end dependency. In Reddy, a load instruction is speculatively executed without distinguishing between a dependency on a source end storage circuit and a dependency on a destination end storage circuit. Reddy does not condition execution of the load instruction on the source end dependency having been released while the destination end dependency still exists. Reddy therefore does not disclose this feature.”
These remarks have been fully considered and, in light of the claim amendments presented in the response, are deemed persuasive. Please see above for new grounds of rejection of the amended claims. Witt discloses, as discussed above, checking dependencies on both the source and destination ends.
On page 18 of the response the Applicant argues, “Reddy does not disclose sending, to the data cache, a blocking signal to cause the data cache to block the data read by the memory access instruction from returning to the destination end storage circuit. In Reddy, the data of a speculatively executed load instruction is retained in the reorder buffer, and the load instruction is flushed and replayed if an ordering violation occurs. Reddy does not send a blocking signal to a data cache, and Reddy does not block data read by an instruction from returning to a destination end storage circuit. Retaining data in a reorder buffer and replaying a flushed instruction is different from blocking, in a data cache, the data read by the memory access instruction from returning to the destination end storage circuit. Reddy therefore does not disclose this feature.”
Though fully considered, the Examiner respectfully disagrees. The Examiner maintains that storing the data in the reorder buffer, where the data is retained until it is determined there is no ordering violation, discloses the claimed limitation. The ROB is prevented from releasing the data, which discloses sending a blocking signal. And the ROB temporarily stores data, which discloses a cache. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On page 19 of the response the Applicant argues, “Claim 2 recites sending a release signal for releasing the data read by the memory access instruction to the data cache when it is determined that the dependency on the destination end storage circuit has been released. Claim 3 recites determining whether the source end dependency has been released and the destination end dependency exists based on the dependency relationship recorded by the dependency recording circuit. Claims 16 and 17 recite corresponding features. Reddy does not disclose these features for at least the reasons discussed above, because Reddy commits an entire instruction once its dependencies are resolved rather than sending a release signal to return blocked data from a data cache to a destination end storage circuit, and because Reddy does not determine whether a source end dependency has been released while a destination end dependency exists.”
Though fully considered, the Examiner respectfully disagrees. The reasons set forth in the remarks and rejections presented above are applicable to these claims.
On pages 20-21of the response the Applicant argues, “The Office Action cites Khailany at paragraph [0041] for synchronization instructions and reasons that it would have been obvious to modify Reddy to include synchronization instructions in order to improve performance by avoiding race conditions. Khailany discloses synchronization instructions in a general sense. Khailany does not disclose that a synchronization release signal is based on a storage range accessible by an instruction stream of each consumption end in a synchronization instruction. Khailany also does not disclose that a synchronization release signal is released separately for a production end according to the storage range. By releasing a dependency separately according to the storage range, the source end dependency and the destination end dependency are released separately, so that the read operation can be executed when the source end dependency is released while the destination end dependency still exists. Adding a general synchronization instruction of Khailany to Reddy does not result in releasing a synchronization release signal separately for a production end according to a storage range accessible by an instruction stream of each consumption end.”
Though fully considered, the Examiner respectfully disagrees. The Examiner cites Reddy as disclosing the features argued above, i.e., the synchronization release being based on a storage range and releasing for each production end separately. Khailany is only cited as teaching that the synchronization release is in response to a synchronization instruction. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On pages 20-21of the response the Applicant argues, “Claim 10 recites that, in response to the amount of data blocked in the data cache exceeding a predetermined threshold, a signal indicating that the data cache space is insufficient is sent to an instruction decoder to suspend decoding of subsequent instructions. Claims 5 and 19 recite suspending decoding of subsequent instructions in response to receiving a signal indicating that the data cache space is insufficient. The Office Action cites Witt for stalling decoding when a buffer is full. Witt discloses stalling decoding based on a buffer being full in a general sense. Witt does not disclose that decoding is suspended in response to the amount of data blocked in a data cache exceeding a predetermined threshold. The signal in claims 5, 10, and 19 results from blocking the data read by the memory access instruction in the data cache, which is not disclosed by Reddy or Witt. A buffer being full in Witt is not the same as the amount of blocked data in a data cache exceeding a predetermined threshold.”
Though fully considered, the Examiner respectfully disagrees. The Applicant argues that Witt discloses Witt discloses stalling based on a buffer being full in a general sense. However, there is a general principle applicable that if storage space is full and processing is not stalled, data will be lost. Stalling based on a buffer being full encompasses an amount of data exceeding a predetermined threshold, whether the size of the buffer, which is predetermined, of some other predetermined threshold. Accordingly, the Applicant’s arguments are deemed unpersuasive.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure.
US 20140068230 by Madduri discloses destination and source dependencies.
US 5832297 by Ramagopal discloses destination and source dependencies.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183
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