DETAILED ACTION
This action is responsive to the preliminary amendments filed on 3/3/2025 and 4/1/2025. Claims 1-15 are pending and have been examined. Claims 3, 5, 8, 11, 13 and 15 have been amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 1-15 are objected to because of the following informalities:
In regard to claim 1, last line amend “associated to the integrated circuit” to “associated with [[to]] the integrated circuit” as to improve grammar.
In regard to claim 8, last line amend “associated to the integrated circuit” to “associated with [[to]] the integrated circuit” as to improve grammar.
In regard to claim 9, last line amend “associated to the integrated circuit” to “associated with [[to]] the integrated circuit” as to improve grammar
In regard to claim 15, last line amend “associated to the integrated circuit” to “associated with [[to]] the integrated circuit” as to improve grammar
Claims 2-7 and 10-14 are dependent upon one of the claims above and therefore are similarly objected to for including the deficiencies of one of the claims above.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “the first sub-block is configured to transmit” and “at least a first sub-block of the plurality of interconnected sub-blocks is configured to transmit” in claims 8-9, 11, 13 and 15. The examiner interprets each sub-block to be a hardware device of an integrated circuit/SoC as disclosed in paragraph [0031].
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
7. Claims 1 and 8 recite the following contingent limitations: “…transmitting a message from a first sub-block to at least one sub-block of the plurality of interconnected sub-blocks, in response to an event on the integrated circuit” and “wherein, in response to an event on the integrated circuit, the first sub-block is configured to transmit a message to the second sub-block”
The contingent limitations use the language “in response to” and are contingent because they precede steps that are only required to be performed in response to (i.e. if) a condition is met. For example, the steps of “transmitting a message” are only required to be performed in response to (e.g. “if”) an event occurring on the integrated circuit. However, if the event does not occur (e.g. a specific event never occurs) the steps of “transmitting a message” are not required to occur based on the broadest reasonable interpretation given to contingent limitations in method claims (See MPEP 2111.04(II) See Ex parte Schulhauser, Appeal 2013-007847 (PTAB April 28, 2016)).
The examiner suggests amending the claim to remove the contingent limitations stating, “in response to” and to positively recite each step of the method claim. For example, the limitation could be amended to state “…transmitting an event message from a first sub-block to at least one sub-block of the plurality of interconnected sub-blocksn event message to the second sub-block”.
Double Patenting
8. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
9. Claims 8 and 15 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7-8 and 14 of copending Application No. 19/108,309 in view of Berenbaum, PGPUB No. 2008/0005379. Although the claims at issue are not identical, they are not patentably distinct from each other because each of the above claims of the instant application is an obvious variant of a corresponding claim of reference application 19/108,309. (Note: This is a provisional nonstatutory double patenting rejection.)
However, claims 1 and 7 of reference application 19/108,309 do not disclose “…wherein, in response to an event on the integrated circuit, the first sub-block is configured to transmit a message to the second sub-block, and wherein the first signal comprises information identifying a class of the event based on a classification of events associated to the integrated circuit into one or more classes”.
Berenbaum discloses wherein, in response to an event on the integrated circuit, the first sub-block is configured to transmit a message to the second sub-block ([0056-0059 and 0062-0064]: wherein a slave device transmits a message/packet to a master device in response to an event. Also, a master device may forward (transmit) message/packet to CPU (See Fig. 5)) and wherein the first signal comprises information identifying a class of the event based on a classification of events associated to the integrated circuit into one or more classes. ([0048, 0051, 0056-0057, 0062-0063]: wherein a signal (a bit or subset of bits) of event information is transmitted to a master device from slave device; or from master device to CPU. Wherein the signal comprises information identifying a type (class) of asynchronous event associated with multiple types (classes) of asynchronous events (see [0046-0047))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the first signal indicating information of an event message of reference application 19/108,309 to include event type information of events as taught in Berenbaum. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (a first signal comprising event type information as taught in Berenbaum) for another (first signal comprising event transmission information) to yield predictable results (a first signal comprising information identifying event type/class of an event) (MPEP 2143, Example B).
Claim Rejections - 35 USC § 102
10. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
11. Claim(s) 1-7 and 9-14 is/are rejected under 35 U.S.C. 102(a)(1)as being anticipated by Berenbaum, PGPUB No. 2008/0005379 (cited on IDS filed on 3/3/2025).
In regard to claim 1, Berenbaum discloses A method for an integrated circuit comprising a plurality of interconnected sub-blocks in a System-on-Chip (SoC) arrangement ([0032, 0034 and 0042]: wherein a system on a chip comprises interconnected master device, a slave device, and a CPU(See Figs. 3-4))
the method comprising: transmitting a message from a first sub-block to at least one sub-block of the plurality of interconnected sub-blocks, in response to an event on the integrated circuit ([0056-0059 and 0062-0064]: wherein a slave device transmits a message/packet to a master device in response to an event. Also, a master device may forward (transmit) message/packet to CPU (See Fig. 5))
and transmitting a signal from the first sub-block to the at least one sub-block of the plurality of interconnected sub-blocks, wherein the signal comprises information identifying a class of the event based on a classification of events associated to the integrated circuit into one or more classes. ([0048, 0051, 0056-0057, 0062-0063]: wherein a signal (a bit or subset of bits) of event information is transmitted to a master device from slave device; or from master device to CPU. Wherein the signal comprises information identifying a type (class) of asynchronous event associated with multiple types (classes) of asynchronous events (see [0046-0047))
Claim 9 is similarly rejected on the same basis as claim 1 above.
In regard to claim 2, Berenbaum discloses The method of claim 1 (see rejection of claim 1 above) wherein the event is a local event in a subsystem of one or more sub-blocks of the plurality of interconnected sub-blocks in the integrated circuit. ([0034, 0048 and 0056-0057]: wherein an event is a local event to a subsystem (combination of a master device and a slave device) of the integrated circuit of the SoC)
Claim 10 is similarly rejected on the same basis as claim 2 above.
In regard to claim 3, Berenbaum discloses The method of claim 2 (see rejection of claim 2 above) wherein the transmitting of the message and the transmitting of the signal to the at least one sub-block of the plurality of interconnected sub-blocks comprises transmitting the message and transmitting the signal to every sub-block of the plurality of interconnected sub-blocks in the subsystem. ([0033-0034 and 0057-0058]: wherein Fig. 3 can include any number of slave devices, and examiner interprets the integrated circuit of Fig. 3 to include a single slave device. Thus, when an interrupt event for an embedded processor is detected the message and included subset of bits are transmitted from the slave device to the master device. Thus, the message and signal are transmitted to every sub-block interconnected in the subsystem consisting of a master and slave device)
Claim 11 is similarly rejected on the same basis as claim 3 above.
In regard to claim 4, Berenbaum discloses The method of claim 1 (see rejection of claim 1 above) wherein the event is a global event ([0059-0060]: wherein a SIRQ or DMA event is a global event as it must be processed by an external device (e.g. CPU). Thus, the event triggers passing information from slave device to master device then to CPU, and thus the event is global as it relates to the whole of the system of Fig. 3)
Claim 12 is similarly rejected on the same basis as claim 4 above.
In regard to claim 5, Berenbaum discloses The method of claim 4 (see rejection of claim 4 above) wherein the transmitting of the message and the transmitting of the signal to the at least one sub-block of the plurality of interconnected sub-blocks comprises transmitting the message and transmitting the signal to every sub-block of the plurality of interconnected sub-blocks in the integrated circuit. ([0033-0034 and 0057-0060]: wherein Fig. 3 can include any number of slave device, and examiner interprets the integrated circuit of Fig. 3 to include a single slave device. Thus, when an event message includes an SIRQ event or DMA event the message and included subsets of bits are transmitted from the slave device to the master device and then to a CPU. Thus, the message and signal are transmitted to every sub-block interconnected in the integrated circuit of the SoC)
Claim 13 is similarly rejected on the same basis as claim 5 above.
In regard to claim 6, Berenbaum discloses The method of claim 1 (see rejection of claim 1 above) wherein the information identifying the class of the event comprises an encoding of the class of the event in one or more data bits for transmission in the signal. ([0057 and 0062-0063]: wherein one or more bits identify the type (class) of event for transmission)
Claim 14 is similarly rejected on the same basis as claim 6 above.
In regard to claim 7, Berenbaum discloses The method of claim 1 (see rejection of claim 1 above) wherein the signal is a signal in a communication protocol between the first sub-block and the at least one sub-block of the plurality of interconnected sub-blocks. ([0033, 0053-0054, 0056-0057 and 0062-0063]: wherein signal is a signal communicated with use of a bus protocol used to communicate between slave and master devices)
Claim Rejections - 35 USC § 103
12. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
13. Claim(s) 8 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Berenbaum, and further in view of Jeong, PGPUB No. 2014/0208071 (cited on IDS filed on 3/3/2025).
In regard to claim 8, Berenbaum discloses A method for an integrated circuit comprising at least two interconnected sub-blocks in a System-on-Chip (SoC) arrangement (See Fig. 3 and [0032 and 0042]) the method comprising: transmitting, from a first sub-block to a second sub-block of the at least two interconnected sub-blocks, a first signal ([0048, 0051, 0056-0057, 0062-0063]: wherein a signal (a bit or subset of bits) of event information is transmitted to a master device from slave device) and transmitting data via a third signal from the first sub-block to the second sub-block ([0056-0057, 0064 and 0071]: wherein data (one or more bits) of one or more packets are transmitted from a slave device to a master device) wherein, in response to an event on the integrated circuit, the first sub-block is configured to transmit a message to the second sub-block ([0056-0059 and 0062-0064]: wherein a slave device transmits a message/packet to a master device in response to an event (See Fig. 5)) and wherein a first signal comprises information identifying a class of the event based on a classification of events associated to the integrated circuit into one or more classes. ([0048, 0051, 0056-0057, 0062-0063]: wherein a signal (a bit or subset of bits) of event information is transmitted to a master device from slave device. Wherein the signal comprises information identifying a type (class) of asynchronous event associated with multiple types (classes) of asynchronous events (see [0046-0047))
Berenbaum does not disclose transmitting, from a first sub-block to a second sub-block of the at least two interconnected sub-blocks, a first signal asserting that the first sub-block is ready to transmit data to the second sub-block; receiving, at the first sub-block from the second sub-block, at the first sub-block, a second signal, the second signal asserting that the second sub-block is ready to receive data from the first sub-block.
Jeong discloses transmitting, from a first sub-block to a second sub-block of the at least two interconnected sub-blocks, a first signal asserting that the first sub-block is ready to transmit data to the second sub-block ([0105-0108]: wherein a device asserts a valid signal to indicate it is ready to transmit data to another device)receiving, at the first sub-block from the second sub-block, at the first sub-block, a second signal, the second signal asserting that the second sub-block is ready to receive data from the first sub-block. ([0105-0108]: wherein a ready signal is asserted by the other device to indicate it is ready to receive data from the first device)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the communication between interconnected devices on the SoC of Berenbaum to use an AXI handshaking protocol as the interconnected devices of the SoC of Jeong. It would have been obvious to one of ordinary skill in the art because it allows for flexible flow between devices that avoids a fixed timing relationship (e.g. transfers only happen when both valid and ready are high, and neither device must lock into a rigid clock cycle count) and provides a simple communication design.
Claim 15 is similarly rejected on the same basis as claim 8 above.
Conclusion
14. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Nore, PGPUB No. 2021/0034442 for teaching communicating event signals between two subsystems of an integrated circuit device
Robbins, PGPUB No. 2018/0004706 for teaching communicating event messages between a processor subsystem and a hardware logic subsystem of a SoC
Horst, USPAT No. 6,157,967 for teaching communicating messages within and between sub-processor systems
15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COURTNEY P SPANN/ Primary Examiner, Art Unit 2183
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