Prosecution Insights
Last updated: September 26, 2026
Application No. 19/109,119

X-RAY DETECTOR

Non-Final OA §103
Filed
Mar 05, 2025
Priority
Sep 06, 2022 — RE 10-2022-0112736 +1 more
Examiner
MALEVIC, DJURA
Art Unit
2884
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
VATECH EWOO Holdings Co., Ltd.
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
1y 1m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
645 granted / 827 resolved
+10.0% vs TC avg
Moderate +10% lift
Without
With
+9.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
42 currently pending
Career history
870
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
70.2%
+30.2% vs TC avg
§102
18.8%
-21.2% vs TC avg
§112
6.6%
-33.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 827 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 03/05/2025 and 04/01/2025 was considered by the examiner. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 5, 6, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 2018/0310896 A1) in view of Lee et al. (US 2017/0299734 A1), Lu et al. (US 2018/0329079 A1), and Griesmer et al. (US 6,472,668 B1). With regard to claim 1, Jeon teaches an X-ray detector with a sensor panel including photoelectric transducers on a substrate and a separate printed circuit board 130 at the rear of the sensor assembly, Jeon [0043], [0047]–[0051], [0066]. Jeon identifies the back surface as the surface where the transducers are not formed [0049] and expressly identifies it as opposite the transducer-bearing surface [0139]. Jeon permits a direct-conversion panel, [0049], [0050], [0140]. Jeon teaches electrical communication through a flexible printed circuit film between the rear PCB and sensor panel, including transmission of a drive signal, Jeon [0066], [0149]. The PCB may occupy a central portion or an area as large as the sensor assembly, [0069]; the panel, optional bending-control member, and PCB may be arranged along the X-ray travel direction, [0136]. The selected arrangement retains a PCB behind the panel. No direct PCB-to-substrate surface contact is alleged. Jeon does not expressly teach the particular bias-pad and conductive-sheet path recited in claim 1. Its drive-signal disclosure is not treated as an express cathode-bias disclosure. Lee teaches a conversion element PC on substrate 110, a lower electrode 120, photoconductive layer 140, and upper electrode 150 over the active sensor region, with bias applied to that upper electrode with a selected material is CdZnTe , Lee [0031]–[0040], Figure 2. Lu teaches a flexible conductive strip 300 with conductive layer 310, electrically coupled to the cathode through conductive tape 100, and connected to a common high-voltage supply through a connection pad on a PCB carrier, Lu [0022]–[0025], Figures 3–6. Lu supplies the bias-pad and strip-fed cathode functions missing from Jeon. Lu’s Figure 6 does not, by itself, resolve the complete strip-to-pad contact geometry. Griesmer teaches a removable distribution sheet having conductive strips 80 on flexible sheet 81 contacting detector arrays and board contacts 94, with busbar 82 contacting terminals 96, Griesmer, col. 5, lines 11–20, Figures 3, 5–6. This supplies a concrete physical sheet-to-board contact arrangement. In view of the utility of a flexible, detachable bias connection in a compact direct-conversion detector, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to implement Lee’s conversion stack in Jeon’s panel and use Lu’s pad-fed conductive strip with Griesmer’s sheet-to-board contact. Extending the strip over the panel, around its nonactive perimeter, and onto the rear PCB pad would provide an accessible bias connection while retaining the rear-board arrangement along with an enhanced detector. With regards to claim 5, Jeon supplies the inherited panel/PCB architecture as modified for claim 1. Lee supplies the first electrode on the substrate, photoconductive layer on that electrode, and second electrode on that layer, Lee [0034], [0037]–[0038], Figure 2. Lu’s inherited strip connection is applied to that second electrode. These are the same stack and connection already selected for claim 1, so no additional structural modification is required as the combination that covers claim 1, also covers claim 5. With regards to claim 6, refer to the rejection of claim 1. The inherited combination selects CdZnTe, expressly listed by Lee [0037] and used in Lu [0018]. That satisfies one of the claimed material alternatives. With regards to claim 7, Jeon modified teaches the claimed invention according to claim 1 but does not expressly place the claimed bias pad in an edge-side area of the PCB. As already noted above, Lu teaches a flexible conductive strip 300 with conductive layer 310, electrically coupled to the cathode through conductive tape 100, and connected to a common high-voltage supply through a connection pad on a PCB carrier, Lu [0022]–[0025], Figures 3–6. The inherited combination provides Lu’s bias pad. Griesmer’s contacts 94 and 96 occupy accessible detector-facing edge regions, Griesmer, Figures 3 and 5, col. 5, lines 11–20. In view of the utility of an accessible, short bias connection, it would have been obvious to a person of ordinary skill in the art to modify Jeon to position the pad at the rear PCB’s edge-side area, following Griesmer’s accessible board contacts, thereby limiting strip routing across the populated board. Claims 2 and 3 are rejected under 35 U.S.C. §103 as being unpatentable over Jeon (US 2018/0310896 A1) in view of Lee et al. (US 2017/0299734 A1), Lu et al. (US 2018/0329079 A1), and Griesmer et al. (US 6,472,668 B1), as applied to claim 1 above, and further in view of Verbakel et al. (WO 2016/078930 A1). With regards to claim 2, Jeon supplies the inherited structure as modified for claim 1. Jeon’s molded outer housing, [0101]–[0103], is not treated as express disclosure of an encapsulation film surrounding the modified panel, PCB, and conductive-sheet assembly. Verbakel teaches encapsulating assembled detector connections and associated electronics, including whole or partial encapsulation, printed p. 7, lines 20–35 and p. 8, lines 12–27, Figures 3B–4B. In view of the utility of protecting the detector and its connections against environmental ingress, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to apply Verbakel’s encapsulation after assembly to exposed portions of the modified panel, conductive sheet, and PCB. This preserves the established electrical contacts while protecting their exterior, although servicing may require removing and renewing the film. With regards to claim 3, Jeon discloses the claimed invention according to claim 2 and further the coating for the encapsulant is selected as parylene, expressly identified by Verbakel, p. 9, lines 9–17 and p. 10, lines 1–11. The selection implements the encapsulation modification already explained for claim 2. Claim 4 is rejected under 35 U.S.C. §103 as being unpatentable over Jeon (US 2018/0310896 A1) in view of Lee et al. (US 2017/0299734 A1), Lu et al. (US 2018/0329079 A1), Griesmer et al. (US 6,472,668 B1), and Verbakel et al. (WO 2016/078930 A1), as applied to claim 2 above, and further in view of Sit (WO 2009/120951 A2). With regards to claim 4, Jeon teaches a rear board connected to an external signal cable, [0067], [0095]. Jeon does not expressly teach the combination of a rear-surface connector and an encapsulation film covering the conductive sheet and rear board surface while excluding that connector. Sit teaches connectors on populated PCBs and masking connector interfaces to keep coating from impairing electrical connectivity, Sit [0003]–[0004], [0008], [00027], Figure 3. Sit’s background masking discussion is relied upon as a stated known coating practice; it is not mislabeled as a newly invented X-ray-detector arrangement. In view of the utility of accessible external connection without coating the mating interface, it would have been obvious to a person of ordinary skill in the art before the effective filing date to place Sit’s connector on the modified PCB’s outward rear face and mask it during encapsulation. The sensor occupies the opposite side, leaving the rear face accessible and its exposed surface protected by the film. Claim 8 is rejected under 35 U.S.C. §103 as being unpatentable over Jeon (US 2018/0310896 A1) in view of Lee et al. (US 2017/0299734 A1), Lu et al. (US 2018/0329079 A1), and Griesmer et al. (US 6,472,668 B1), as applied to claim 1 above, and further in view of Hirose et al. (US 2001/0042637 A1). With regard to claim 8, Jeon discloses the claim invention according to claim 1, but does not expressly teach that “the conductive sheet contains a metal foil or grid made of gold (Au), platinum (Pt), or an alloy thereof.” Lu supplies a flexible bias strip with metal layer 310, optional insulating backing 320, and gold finishing, Lu [0019], [0022]–[0025], Figures 3–6; that finishing is not relied upon as an express gold-foil disclosure. Hirose teaches conductive foil 709 used in the conductor structure of a printed circuit board and expressly identifies gold foil and platinum foil as alternatives to copper foil, Hirose [0671], [0674]–[0675], [0694], Figures 51–53. Its foil and plated layers may also employ different metals, [0698]. This supplies the added material and foil form as a gold foil is the selected alternative. Hirose is reasonably pertinent to selecting the thin conductive layer of PCB-based bias connections; Lu expressly permits a flexible PCB strip, [0019], [0022]. Notice that the proposed change concerns that conductor layer, while the inherited combination supplies detector coverage and routing. In view of the utility of a thin foil conductor for electrical continuity in a PCB connection, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to implement Lu’s conductive layer 310 in the modified Jeon detector using Hirose’s gold-foil alternative. Retaining Lu’s flexible backing and conductive contacts would predictably preserve the strip’s bias-delivery function. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Djura Malevic whose telephone number is 571.272-5975. The examiner can normally be reached M-F (9-5). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uzma Alam can be reached at 571.272.3995 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DJURA MALEVIC/Examiner, Art Unit 2884 /UZMA ALAM/Supervisory Patent Examiner, Art Unit 2884
Read full office action

Prosecution Timeline

Mar 05, 2025
Application Filed
Sep 17, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
88%
With Interview (+9.5%)
2y 8m (~1y 1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 827 resolved cases by this examiner. Grant probability derived from career allowance rate.

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