DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/06/2025,11/12/2025 considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Obata et al. US 2006/0022679 A1 (hereinafter referred to as Obata) in view of Parikh US 2016/0248517 A1.
Claim 1, Obata discloses an inverter pulse insulation test device, comprising: a pulse generation circuit (fig. 1A, surge generator 1, par. [0051]), having a first output end, and outputting (fig. 1A, output, 27, par. [0051]), from the first output end (fig. 1A, output, 27, par. [0051]), a voltage having a simulated drive voltage waveform comprising intermittent pulses (see fig. 1B, surge voltage, par. [0052]); and a surge voltage generation circuit (fig. 1A, surge voltage waveform regulator 4, par. [0051]), having an input end (see fig. 1A) electrically connected to the first output end of the pulse generation circuit and a second output end connected to a test object (fig. 1A, test motor 2 winding, par. [0051],[0056]), changing the drive voltage waveform by generating a surge voltage at a rise and a fall of each pulse of the drive voltage waveform input from the input end, and outputting, from the second output end, a voltage having the drive voltage wave form that is changed (fig. 11, par. [0052]-[0060]), wherein the surge voltage generation circuit comprises: a resistor and a inductor connected in series with each other; and a capacitance capacitor (fig. 13, par. [0053]), an end of a serial circuit of the resistor and the inductor form the input end of the surge voltage generation circuit, an other end of the serial circuit is connected to the second output end of the surge voltage generation circuit (see fig. 1A), an end of the capacitance capacitor is connected to a node between the other end of the serial circuit and the second output end, and an other end of the capacitance variable capacitor is connected to a constant potential line (see fig. 13, LCR filter, par. [0053]).
Obata does not disclose variable resistor and a variable inductor connected in series with each other and a capacitance variable.
Parikh discloses a variable inductor connected in series with each other and a capacitance variable (see fig. 1-2, par. [0018] and [0020]- [0023])
Obata discloses that the output waveform of the surge voltage waveform adjustment circuit can be adjusted in accordance with the value of square root (LC) and the value of R of the LCR filter but does not indicate that the LCR filter is composed of a variable resistor, a variable inductor, and a variable capacitance capacitor. However, by way of example, Parikh (see fig. 1-2, par. [0018] and [0020]-[0023]) discloses a filtering circuit may then filter data signal producing a filtered data signal, by including a variable resistor, a variable capacitor, and a variable inductor in the filtering circuit may adjust the ringing frequency and transient decay created by the RLC components allowing for more accurate pre-emphasis of data signal. It is, thus, a well-known technique to use variable inductance, variable resistor and a variable capacitance capacitor in order to adjust the circuit coefficient. It would have been obvious to one of ordinary skill in the art before the effective filing date to improve the LCR filter disclosed in Obata by applying the well-known technique to use variable inductance, variable resistor and variable capacitor filtering circuit to adjust the ringing frequency and transient decay created by the RLC components allowing for more accurate pre-emphasis of data signal.
Claim 3, Obata and Parikh discloses the inverter pulse insulation test device as claimed in claim 1, Obata discloses wherein the pulse generation circuit (fig. 1A, surge generator 1, par. [0051]) has: a plurality of semiconductor switches (fig. 1A, switches 14 and 15 may be high-speed switches such as IGBT or MOS-FET devices, par. [0052]) for forming the drive voltage waveform; and a first control part (fig. 1 elm. 30, par. [0052]), generating a plurality of optical trigger signals respectively controlling the semiconductor switches (par. [0052]), and the first control part provides the respective optical trigger signals to the respective semiconductor switches (par. [0052]).
Claim 7, Obata and Parikh discloses the inverter pulse insulation test device as claimed in claim 3, Obata discloses wherein the pulse generation circuit (fig. 1A, surge generator 1, par. [0051]) has: a plurality of semiconductor switches (fig. 1A, switches 14 and 15 may be high-speed switches such as IGBT or MOS-FET devices, par. [0052]) for forming the drive voltage waveform (fig. 1, output, 27, par. [0052]); and a first control part (fig. 1 elm. 30, par. [0052]), generating a plurality of optical trigger signals respectively controlling the semiconductor switches (par. [0052]), and the first control part provides the respective optical trigger signals to the respective semiconductor (par. [0052]).
Claim(s) 4-5 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Obata in view of Parikh as applied to claim 1 above, and further in view of Sakurai et al. US 2015/0015303 A1 (hereinafter referred to as Sakurai).
Claim 4, Obata and Parikh discloses the inverter pulse insulation test device as claimed in claim 1, Obata and Parikh do not disclose further comprising: a second control part, controlling the drive voltage waveform in the pulse generation circuit; and an input operation part, receiving an input operation relating to a number of the intermittent pulses, and providing information relating to the number of the intermittent pulses input through the input operation to the second control part, wherein the second control part determines the number of the intermittent pulses in accordance with the information.
Sakurai discloses further comprising: a second control part (fig. 1, measurement device 5, par. [0038]), controlling the drive voltage waveform in the pulse generation circuit (fig. 1, impulse voltage generator 3, par. [0038]); and an input operation part (fig. 1, partial discharge detector 4, par. [0053]), receiving an input operation relating to a (fig. 3, par. [0059]) number of the intermittent pulses and providing information relating to the number of the intermittent pulses input through the input operation to the second control part, wherein the second control part determines the number of the intermittent pulses in accordance with the information (fig. 2-3, par. [0045]-[0072]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a partial discharge measurement system and a partial discharge measurement method using a repetitive impulse voltage, as taught in Sakurai in modifying the apparatus of Obata and Parikh. The motivation would be the user can be enabled to set arbitrary impulse voltages and the user's work can be reduced efficiently. (see Sakurai: abs.).
Claim 5, Obata and Parikh discloses the inverter pulse insulation test device as claimed in claim 1, Obata discloses a second control part controlling the drive voltage waveform (fig. 1, output, 27, par. [0052]) in the pulse generation circuit (fig. 1, impulse voltage generator 3, par. [0038]); and an input operation part (fig. 1A, keyboard), receiving an input operation relating to the drive voltage waveform and providing, to the second control part, information relating to the drive voltage waveform (fig. 1, output, 27, par. [0052]) in input through the input operation; information relating to whether the intermittent pulses are formed by positive pulses only, negative pulses only, or both of the positive pulses and the negative pulses (fig. 1B, 15B, 16B, par. [0052], [0097], [0100])
Obata and Parikh do not disclose wherein the second control part determines the drive voltage waveform in accordance with the information, and the information relating to the drive voltage waveform comprises at least one of: information relating to whether the intermittent pulses are permanently output until a test ends or output in bursts within a period set in advance; information relating to an amplitude of the intermittent pulses; information relating to a frequency of the intermittent pulses; and information relating to a time width of each pulse forming the intermittent pulses.
Sakurai discloses the second control part determines the drive voltage waveform in accordance with the information, and the information relating to the drive voltage waveform comprises at least one of: information relating to whether the intermittent pulses are permanently output until a test ends or output in bursts within a period set in advance; information relating to an amplitude of the intermittent pulses; information relating to a frequency of the intermittent pulses; and information relating to a time width of each pulse forming the intermittent pulses (fig. 2-3, par. [0053], [0060], [0064], [0080], [0088], [0093]).
The references are combined for the same reason already applied in the rejection of claim 4.
Claim 9, Obata, Parikh and Sakurai discloses the inverter pulse insulation test device as claimed in claim 3, Obata discloses a second control part controlling the drive voltage waveform (fig. 1, output, 27, par. [0052]) in the pulse generation circuit (fig. 1, impulse voltage generator 3, par. [0038]); and an input operation part (fig. 1A, keyboard), receiving an input operation relating to the drive voltage waveform and providing, to the second control part, information relating to the drive voltage waveform (fig. 1, output, 27, par. [0052]) in input through the input operation; information relating to whether the intermittent pulses are formed by positive pulses only, negative pulses only, or both of the positive pulses and the negative pulses (fig. 1B, 15B, 16B, par. [0052], [0097], [0100])
Obata and Parikh do not disclose wherein the second control part determines the drive voltage waveform in accordance with the information, and the information relating to the drive voltage waveform comprises at least one of: information relating to whether the intermittent pulses are permanently output until a test ends or output in bursts within a period set in advance; information relating to an amplitude of the intermittent pulses; information relating to a frequency of the intermittent pulses; and information relating to a time width of each pulse forming the intermittent pulses.
Sakurai discloses the second control part determines the drive voltage waveform in accordance with the information, and the information relating to the drive voltage waveform comprises at least one of: information relating to whether the intermittent pulses are permanently output until a test ends or output in bursts within a period set in advance; information relating to an amplitude of the intermittent pulses; information relating to a frequency of the intermittent pulses; and information relating to a time width of each pulse forming the intermittent pulses (fig. 2-3, par. [0053], [0060], [0064], [0080], [0088], [0093]).
The references are combined for the same reason already applied in the rejection of claim 4.
Allowable Subject Matter
Claims 2, 6 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 2, the prior art of record does not teach alone or in combination pulse a generation circuit outputs a voltage having a two-level or three-level inverter drive waveform as the drive voltage waveform, and the pulse generation circuit comprises: a first semiconductor switch, wherein an end is connected to a positive voltage terminal, and the other end is connected to the first output end; a second semiconductor switch, wherein an end is connected to a negative voltage terminal, and the other end is connected to the first output end; a bridge full-wave rectifier, having two input ends and two output ends, wherein one of the two input ends is connected to a reference potential line, and one of the two output ends is connected to the first output end; and a third semiconductor switch, wherein an end is connected to other one of the input ends of the bridge full-wave rectifier in combination with all other elements in claim 2.
Regarding claims 6 and 8 are considered to be allowable due to their dependencies on allowable claim 2.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure (Kimura et al. JP 2021189120 A).
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/COURTNEY G MCDONNOUGH/Examiner, Art Unit 2858
/FARHANA A HOQUE/Primary Examiner, Art Unit 2858
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