Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
The examiner acknowledges amendments to claims 1, 4-6, 10-11, and 13 in the reply dated 27 July 2026. Claims 16-21 have been added. Claim 15 was previously cancelled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 8, 16, and 18-21 are rejected under 35 U.S.C. 103 as being unpatentable over Hiyoshi (US 20160086799 A1, hereinafter “Hiyoshi”), in view of Torregrosa et al (Frank Torregrosa et al, “Advantages and Challenges of Plasma Immersion Ion Implantation for Power Devices Manufacturing on Si, SiC, and GaN Using PULSION Tool”, HAL Open Science, 14 December 2018, https://laas.hal.science/hal-01955688v1, accessed 1 May 2026, hereinafter “Torregrosa”), and further in view of Tsuchida et al (US 20090047772 A1, hereinafter “Tsuchida”), and further in view of Hu et al (CN 103219236 B, hereinafter “Hu”).
Regarding Claim 1 - Hiyoshi discloses a method for producing a semiconductor body, comprising providing an n-doped substrate made of SiC (10 [0059] and Fig. 25), epitaxially growing a first semiconductor layer of SiC directly on the substrate (S1 [0092] and Fig. 2), the first semiconductor layer is n-doped (n-type impurity added during growth [0083]) and an average and/or maximum doping concentration in the first semiconductor layer is smaller than an average and/or minimum doping concentration in the substrate ([0125] and Fig. 26), introducing carbon into the first semiconductor layer (S2 [0096] and Fig. 2), so that at least a portion of the first semiconductor layer becomes at least one C-rich region (6 [0100] and Fig. 10), epitaxially growing a second semiconductor layer of SiC on the first semiconductor layer comprising the at least one C-rich region ([0096] and Fig. 2), the second semiconductor layer is n-doped (n-type impurity added during growth [0083]), and performing a further implantation process in which p-doped p-wells are formed in the second semiconductor layer (22 [0125] and Fig. 25).
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Hiyoshi fails to explicitly disclose using plasma ion immersion implantation, PIII, and a minimum and/or average concentration of C-atoms or C-ions, respectively, at interstitial sites is at least 100-times greater than a maximum and/or average concentration in the first semiconductor layer before the step of introducing carbon has been performed, and in the C-rich region, the average concentration of C-atoms or C-ions at interstitial sites is at least 1017 cm-3, and a thickness of the C-rich region is at least 15 nm and at most 50 nm, forming at least one buffer region of the second semiconductor layer adjoining the C-rich region and being n-doped with an average and/or maximum doping concentration being greater than the average and/or maximum doping concentration in the first semiconductor layer, the at least one buffer region is a buffer layer extending contiguously without interruptions over a whole lateral extent of the second semiconductor layer.
However, Torregrosa discloses plasma ion immersion implantation (Torregrosa Page 2, Column 1).
Torregrosa discloses plasms ion immersion implantation as a method of doping compatible with the structure of Hiyoshi. Torregrosa teaches widespread usage of plasma ion immersion implantation for the benefits of introducing high doses at reduced depth compared to conventional ion implantation with high throughput and low cost of ownership (Torregrosa Page 2, Column 1 and Page 5, Column 2). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the teachings of Hiyoshi and Torrregrosa to use plasma ion immersion implantation for the benefits of high throughput and low cost of ownership.
Furthermore, Tsuchida discloses a minimum and/or average concentration of C-atoms or C-ions, respectively, at interstitial sites is at least 100-times greater than a maximum and/or average concentration in the first semiconductor layer before the step of introducing carbon has been performed (by introducing carbon at 1.5E17 cm-3 (Tsuchida [0245]) to a region with only 4E13 cm-3 maximum defect sites, then driving them to zero (Tsuchida Fig. 16), it is clear more than 100 fold interstitial carbon atoms were introduced compared to the material before implantation because the existing interstitials would have filled the defects has they been available (Hiyoshi [0093])), and in the C-rich region, the average concentration of C-atoms or C-ions at interstitial sites is at least 1017 cm-3 (1.5E17 cm-3, Tsuchida [0245]). Furthermore, Tsuchida discloses a thickness of the C-rich region is 100-2000 nm (Tsuchida [0070]), which is a close range to 15-50 nm, presenting a prima facie case of obviousness in light of the use of shallower implantation method, PIII, in the instant application as discussed above, compared with Tsuchida’s use of conventional ion implantation (Tsuchida [0082]). See MPEP 2144.05(I).
Additionally, in light of Torregrosa’s teaching of PIII, implantation depth is a matter of routine optimization. See MPEP 2144.05(II). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to set the depth of the carbon-rich region by routine optimization.
Tsuchida discloses an analogous SiC layer stack for power devices to Hiyoshi. Tsuchida teaches carbon interstitials are implanted in a SiC power device at an energy greater than 1E17 cm-3 in a range 100-2000nm from the surface for the benefit of effectively reducing point defects (Tsuchida [0072]). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teachings of Hiyoshi and Tsuchida to implant interstitial carbon into silicon carbide and energy greater than 1E17 cm-3 for the benefit of effectively reducing point defects.
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Furthermore, Hu discloses forming at least one buffer region of the second semiconductor layer (7 is 5E17 to 5E18 cm-3, Hu [0014], [0043] and Fig. 2(e-2)) adjoining the C-rich region (Region 2, Hu [0013] and Fig. 2(e-2)) and being n-doped with an average and/or maximum doping concentration being greater than the average and/or maximum doping concentration in the first semiconductor layer (1E16 to 1E17 cm-3, Hu [0014]), the at least one buffer region is a buffer layer extending contiguously without interruptions over a whole lateral extent of the second semiconductor layer (Hu Fig. 2(e-2)).
Hu discloses an epitaxial SiC stack for power devices, similar to Hiyoshi. Hu teaches placing a buffer layer to optimize the tradeoff between conduction characteristics and turn-off speed (Hu [0005]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Hiyoshi and Hu to incorporate a contiguous buffer layer adjoining the C-rich region with a concentration greater than the doping concentration of the first semiconductor layer to optimize the tradeoff between conduction characteristics and turn-off speed.
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Regarding Claim 2 - Hiyoshi modified by Torregrosa, Tsuchida, and Hu discloses all the limitations of claim 1.
The combination of Hiyoshi, Torregrosa, Tsuchida, and Hu further discloses the method according to claim 1, wherein- the C-rich region is formed at an exposed side of the first semiconductor layer and such that, after epitaxially growing the second semiconductor layer, the C- rich region lies between the second semiconductor layer and a remaining portion of the first semiconductor layer which has not become C-rich (Each epitaxial layer has carbon introduced at the surface, Hiyoshi [0050] and Fig. 2).
Regarding Claim 3 - Hiyoshi modified by Torregrosa, Tsuchida, and Hu discloses all the limitations of claim 1.
The combination of Hiyoshi, Torregrosa, Tsuchida, and Hu further discloses the thickness of the C-rich region is at least 15 nm and at most 50 nm (100-2000 nm, which is an approaching range, and a prima facie case of obviousness. See MPEP2144.05(I).)
Regarding Claim 4 - Hiyoshi modified by Torregrosa, Tsuchida, and Hu discloses all the limitations of claim 1.
The combination of Hiyoshi, Torregrosa, Tsuchida, and Hu further discloses implanting first-type dopants into a semiconductor layer sequence, said semiconductor layer sequence comprising the first and second semiconductor layer (22, Hiyoshi [0125] and Fig. 25).
Regarding Claim 6 - Hiyoshi modified by Torregrosa, Tsuchida, and Hu discloses all the limitations of claim 4.
The combination of Hiyoshi, Torregrosa, Tsuchida, and Hu further discloses implantation is done with an energy of the C-ions in a range between 1 keV inclusive and 50 keV inclusive (10-300keV, Hiyoshi [0101], which is an overlapping range, presenting a prima facie case of obviousness. See MPEP 2144.05(I)).
Regarding Claim 8 - Hiyoshi modified by Torregrosa, Tsuchida, and Hu discloses all the limitations of claim 1.
The combination of Hiyoshi, Torregrosa, Tsuchida, and Hu further discloses introducing carbon into the second semiconductor layer so that at least a portion of the second semiconductor layer becomes at least one C-rich region, and growing a third semiconductor layer of SiC on the second semiconductor layer (Hiyoshi [0105] and Fig. 2).
Regarding Claim 16 - The method according to claim 1, wherein the C-rich region has its maximum concentration of C-atoms or C-ions at interstitial sites at an interface between the first semiconductor layer and the second semiconductor layer (at the local minimum of Z1/2 center density at an interface of first and second epi layers, Hiyoshi [0062] and Fig. 23).
Regarding Claim 18 - Hiyoshi modified by Torregrosa, Tsuchida, and Hu discloses all the limitations of claim 1.
The combination of Hiyoshi, Torregrosa, Tsuchida, and Hu further discloses a maximum concentration of C- atoms or C-ions at interstitial sites in the C-rich region is at most 1021 cm-3 (e.g. around 1.5E17 cm-3, Tsuchida [0245]).
Regarding Claim 19 - Hiyoshi modified by Torregrosa, Tsuchida, and Hu discloses all the limitations of claim 1.
The combination of Hiyoshi, Torregrosa, Tsuchida, and Hu further discloses a minimum and/or average concentration of n-type dopants in the at least one buffer region is at least 1016 cm-3 (7 is 5E17 to 5E18 cm-3, Hu [0014], [0043] and Fig. 2(e-2)).
Regarding Claim 20 - Hiyoshi modified by Torregrosa, Tsuchida, and Hu discloses all the limitations of claim 1.
The combination of Hiyoshi, Torregrosa, Tsuchida, and Hu further discloses heating a semiconductor layer sequence to a temperature of at least 1500°C wherein the heating releases carbon at the interstitial sites of the C-rich region, and released carbon recombines with carbon vacancies (Hiyoshi [0103]).
Regarding Claim 21 - Hiyoshi modified by Torregrosa, Tsuchida, and Hu discloses all the limitations of claim 1.
The combination of Hiyoshi, Torregrosa, Tsuchida, and Hu further discloses the plasma ion immersion implantation produces a shallow implantation region detectable by secondary ion mass spectrometry (SIMS) due to a characteristic implantation profile shape generated by PIII and presence of extra species from precursors used in the PIII process (PIII implanted region detectable by SIMS, Torregrosa Fig. 9).
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Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Hiyoshi (US 20160086799 A1, hereinafter “Hiyoshi”), in view of Torregrosa et al (Frank Torregrosa et al, “Advantages and Challenges of Plasma Immersion Ion Implantation for Power Devices Manufacturing on Si, SiC, and GaN Using PULSION Tool”, HAL Open Science, 14 December 2018, https://laas.hal.science/hal-01955688v1, accessed 1 May 2026, hereinafter “Torregrosa”), and further in view of Tsuchida et al (US 20090047772 A1, hereinafter “Tsuchida”), and further in view of Hu et al (CN 103219236 B, hereinafter “Hu”), and further in view of the following argument.
Regarding Claim 17 - Hiyoshi modified by Torregrosa, Tsuchida, and Hu discloses all the limitations of claim 1.
The combination of Hiyoshi, Torregrosa, Tsuchida, and Hu fails to expressly disclose a concentration profile of C-atoms or C-ions at interstitial sites in a direction perpendicular to a main extension plane of the first semiconductor layer is asymmetric with respect to the interface between the first and the second semiconductor layer, and wherein a distance from the interface at which the concentration falls below 0.01 times the maximum concentration is at least two orders of magnitude greater in the first semiconductor layer than in the second semiconductor layer.
However, since the initial implanted carbon concentration versus depth profile is solely in the first semiconductor layer, and the carbon concentration versus depth profile in the second semiconductor layer adjacent to the interface between first and second semiconductor layers results solely from diffusion, it follows that the distance of a concentration away from the interface in the final profile in the second semiconductor starts at zero and can approach but not exceed the depth of that same concentration in the first semiconductor layer with added diffusion time and temperature, including the thermal budget of the second semiconductor layer growth itself. Therefore, setting a distance from the interface at which the concentration falls below 0.01 times the maximum concentration where that distance is at least two orders of magnitude greater in the first semiconductor layer than in the second semiconductor layer is a matter of routine optimization. See MPEP 2144.05(II). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider setting a distance from the interface at which the concentration falls below 0.01 times the maximum concentration at least two orders of magnitude greater in the first semiconductor layer than in the second semiconductor layer as a matter of routine optimization.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Hiyoshi (US 20160086799 A1, hereinafter “Hiyoshi”), in view of Torregrosa et al (US 20180031319 A1, hereinafter “Torregrosa”), and further in view of Tsuchida et al (US 20090047772 A1, hereinafter “Tsuchida”), and further in view of Hu et al (CN 103219236 B, hereinafter “Hu”), and further in view of Miyazaki et al (US 20130045592 A1, hereinafter “Miyazaki”).
Regarding Claim 5 - Hiyoshi modified by Torregrosa, Tsuchida, and Hu discloses all the limitations of claim 4.
The combination of Hiyoshi, Torregrosa, Tsuchida, and Hu fails to explicitly disclose activating first type-dopants at a temperature of at least 1500 °C.
However, Miyazaki discloses activating first type dopants at a temperature of at least 1500 °C (1700°C, Miyazaki [0102]).
Miyazaki discloses an analogous SiC power device to Hiyoshi. Miyazaki teaches implanting, then annealing, a p-well at 1700°C to activate the p-type dopants, causing them to occupy substitutional sites in the crystal lattice (Miyazaki [0102]). therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to activate the first type dopants at a temperature of at least 1500°C for the benefit of causing them to occupy substitutional sites in the crystal lattice. Furthermore, this is a well-known process in the semiconductor industry, presenting a prima facie case of obviousness by routine optimization. See MPEP 2144.05(II).
Claims 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Hiyoshi (US 20160086799 A1, hereinafter “Hiyoshi”), in view of Torregrosa et al (US 20180031319 A1, hereinafter “Torregrosa”), and further in view of Tsuchida et al (US 20090047772 A1, hereinafter “Tsuchida”), and further in view of Hu et al (CN 103219236 B, hereinafter “Hu”), and further in view of Draghici et al (US 20170309484 A1, hereinafter “Draghici”).
Regarding Claim 7 - Hiyoshi modified by Torregrosa, Tsuchida, and Hu discloses all the limitations of claim 1.
The combination of Hiyoshi, Torregrosa, Tsuchida, and Hu fail to disclose a plurality of C-rich regions which are laterally spaced from each other is formed in the first semiconductor layer.
However, Draghici discloses a plurality of C-rich regions which are laterally spaced from each other is formed in the first semiconductor layer (304, Draghici [0026] and Fig. 3E).
Draghici discloses a SiC power device analogous to Hiyoshi. Draghici teaches patterning C-rich regions for the benefit of providing carrier lifetime enhancement only where high current gain is needed (Draghici [0026]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Hiyoshi and Draghici to pattern C-rich regions for the benefit of providing carrier lifetime enhancement only where high current gain is needed.
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Regarding Claim 9 - Hiyoshi modified by Torregrosa, Tsuchida, and Hu discloses all the limitations of claim 8.
The combination of Hiyoshi, Torregrosa, Tsuchida, and Hu fails to disclose a plurality of C-rich regions which are laterally spaced from each other is formed in the first semiconductor layer, and the C-rich regions in the first semiconductor layer and the C-rich regions in the second semiconductor layer are arranged in a staggered configuration.
However, Draghici discloses a plurality of C-rich regions which are laterally spaced from each other is formed in the first semiconductor layer, and the C-rich regions in the first semiconductor layer and the C-rich regions in the second semiconductor layer are arranged in a staggered configuration (304, Draghici [0026] and Fig. 3E).
Draghici discloses a SiC power device analogous to Hiyoshi. Draghici teaches patterning C-rich regions for the benefit of providing carrier lifetime enhancement only where high current gain is needed (Draghici [0026]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Hiyoshi and Draghici to pattern C-rich regions for the benefit of providing carrier lifetime enhancement only where high current gain is needed.
The combination of Hiyoshi, Torregrosa, Tsuchida, Hu, and Draghici fails to disclose a plurality of C-rich regions which are laterally spaced from each other is formed in the second semiconductor layer.
However, a plurality of C-rich regions which are laterally spaced from each other formed in the second semiconductor layer represents a duplication and rearrangement of parts and is prima facie obvious. See MPEP 2144.04(VI)(B&C).
Claims 10-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Hiyoshi (US 20160086799 A1, hereinafter “Hiyoshi”), in view of Hu et al (CN 103219236 B, hereinafter “Hu”), and further in view of Tsuchida et al (US 20090047772 A1, hereinafter “Tsuchida”), and further in view of
Regarding Claim 10 - Hiyoshi discloses a semiconductor body comprising an n-doped substrate made of SiC (10 [0059] and Fig. 25), a first semiconductor layer of SiC directly on the substrate (13A [0062] and Fig. 25), the first semiconductor layer is n-doped (n-type impurity added during growth [0083]) and an average and/or maximum doping concentration in the first semiconductor layer is smaller than an average and/or minimum doping concentration in the substrate ([0125] and Fig. 26), a second semiconductor layer of SiC directly on the first semiconductor layer (13C [0062] and Fig. 25), the second semiconductor layer is n-doped (n-type impurity added during growth [0083]), at least one C-rich region in the first semiconductor layer (6 [0100] and Fig. 10), and p-doped p-wells in the second semiconductor layer (22 [0125] and Fig. 25), wherein the at least one C-rich region adjoins the second semiconductor layer ([0096] and Fig. 2).
Hiyoshi fails to disclose at least one buffer region of the second semiconductor layer adjoining the C-rich region and being n-doped with an average and/or maximum doping concentration being greater than the average and/or maximum doping concentration in the first semiconductor layer, the at least one buffer region is a buffer layer extending contiguously without interruptions over a whole lateral extent of the second semiconductor layer, and in the C-rich region, the average concentration of C-atoms or C-ions at interstitial sites is at least 1017 cm-3, and a thickness of the C-rich region is at least 15 nm and at most 50 nm.
However, Hu discloses at least one buffer region of the second semiconductor layer (7 , Hu [0043] and Fig. 2(e-2)) adjoining the C-rich region (Region 2, Hu [0013] and Fig. 2(e-2)) and being n-doped with an average and/or maximum doping concentration (5E17 to 5E18 cm-3, Hu [0014]) being greater than the average and/or maximum doping concentration in the first semiconductor layer (1E16 to 1E17 cm-3, Hu [0014]), the at least one buffer region is a buffer layer extending contiguously without interruptions over a whole lateral extent of the second semiconductor layer (Hu Fig. 2(e-2)).
Hu discloses an epitaxial SiC stack for power devices, similar to Hiyoshi. Hu teaches placing a buffer layer to optimize the tradeoff between conduction characteristics and turn-off speed (Hu [0005]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Hiyoshi and Hu to incorporate a contiguous buffer layer adjoining the C-rich region with a concentration greater than the doping concentration of the first semiconductor layer, to optimize the tradeoff between conduction characteristics and turn-off speed.
Furthermore, Tsuchida discloses in the C-rich region, the average concentration of C-atoms or C-ions at interstitial sites is at least 1017 cm-3 (1.5E17 cm-3, Tsuchida [0245]), and a thickness of the C-rich region is 100-2000 nm (Tsuchida [0070]), which is a close range to 15-50 nm, presenting a prima facie case of obviousness in light of the use of shallower implantation method, PIII, in the instant application (see below), compared with Tsuchida’s use of conventional ion implantation (Tsuchida [0082]). See MPEP 2144.05(I).
Tsuchida discloses an analogous SiC layer stack for power devices to Hiyoshi. Tsuchida teaches carbon interstitials are implanted in a SiC power device at an energy greater than 1E17 cm-3 in a range 100-2000nm from the surface for the benefit of effectively reducing point defects (Tsuchida [0072]). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teachings of Hiyoshi and Tsuchida to implant interstitial carbon into silicon carbide and energy greater than 1E17 cm-3 in a range of 100-2000nm from the surface for the benefit of effectively reducing point defects. Furthermore, implant energy and depth are a matter of routine optimization, and a prima facie case of obviousness. See MPEP 2144.05(II).
Furthermore, Torregrosa discloses plasma ion immersion implantation (Torregrosa Page 2, Column 1).
Torregrosa discloses plasms ion immersion implantation as a method of doping compatible with the structure of Hiyoshi. Torregrosa teaches widespread usage of plasma ion immersion implantation for the benefits of introducing high doses at reduced depth compared to conventional ion implantation with high throughput and low cost of ownership (Torregrosa Page 2, Column 1 and Page 5, Column 2). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the teachings of Hiyoshi and Torrregrosa to use plasma ion immersion implantation for the benefits of high throughput and low cost of ownership.
Regarding Claim 11 - Hiyoshi modified by Hu, Tsuchida, and Torregrosa discloses all the limitations of claim 10.
The combination of Hiyoshi, Hu, Tsuchida, and Torregrosa further discloses the at least one C-rich region has its maximum concentration of C-atoms or C-ions at interstitial sites at the interface to the second semiconductor layer (at the local minimum of Z1/2 center density at an interface of first and second epi layers, Hiyoshi [0062] and Fig. 23).
Regarding Claim 12 - Hiyoshi modified by Hu, Tsuchida, and Torregrosa discloses all the limitations of claim 10.
The combination of Hiyoshi, Hu, Tsuchida, and Torregrosa further discloses the average concentration of C-vacancies in the second semiconductor layer is at most 1012 cm-3 (Pz defect density a measure of vacancies. Maximum Pz not more than 5E11cm-3, Hiyoshi [0063]).
Regarding Claim 14 - Hiyoshi modified by Hu, Tsuchida, and Torregrosa discloses all the limitations of claim 10.
The combination of Hiyoshi, Hu, Tsuchida, and Torregrosa further discloses a power semiconductor device, comprising a semiconductor body according to claim 10, and electrodes in electrical contact with the semiconductor body (32 and 34, Hiyoshi [0124] and Fig. 25).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Hiyoshi (US 20160086799 A1, hereinafter “Hiyoshi”), in view of Hu et al (CN 103219236 B, hereinafter “Hu”), and further in view of Tsuchida et al (US 20090047772 A1, hereinafter “Tsuchida”), and further in view of Schaffer et al (W. J. Schaffer, G. H. Negley, K. G. Irvine and J. W. Palmour, “Conductivity anisotropy in epitaxial 6 H and 4 H SiC,” in Mat. Res. Soc. Symp. Proc., pp. 595–600, vol. 339, 1994, hereinafter “Schaffer”).
Regarding Claim 13 - Hiyoshi modified by Hu and Tsuchida discloses all the limitations of claim 10.
The combination of Hiyoshi, Hu, and Tsuchida fails to disclose an average mobility for charge carriers in the second semiconductor layer is at least 100 cm2/Vs at room temperature.
However, Schaffer discloses an average mobility for charge carriers in the second semiconductor layer is at least 100 cm2/Vs at room temperature (up to 947 cm2/Vs at 300K in n-type SiC, Schaffer Table I).
Schaffer discloses characterization data for SiC layers similar in polarity (n-type) and doping level (1E17-1E18 cm-3) to those in the claimed invention (Schaffer Abstract and Table I), demonstrating 100 cm2/Vs is easily exceeded. Although the combination of Hiyoshi, Hu, and Tsuchida fails to disclose the mobility at least 100 cm2/Vs, it is an inherent characteristic of the material. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention that a mobility of 100 cm2/Vs could be met or exceeded in the semiconductor body of Hiyoshi as an inherent characteristic. See MPEP 2112(II).
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Response to Arguments
Applicant's arguments filed 27 July 2026 have been fully considered but they are not persuasive.
The applicant argues the carbon-rich region implanted to a depth of 15-50 nm is below and not overlapping 100-2000 nm of Tsuchida, and characteristic of PIII. As explained above, the range of 15-50 nm is close to 100-2000 nm, and the use of PIII instead of conventional ion implantation causes the difference in the range. Three profile example are given in Torregrosa Fig. 9, wherein all three example profiles drop to the background level of counterdoping (Mg) within the 15-50 nm range claimed. PIII is a known implantation method, and therefore the range is a matter of routine optimization.
The applicant argues Draghici teaches depositing a carbon-rich layer rather than by PIII. However, the relevance of Draghici is the patterning of carbon-rich regions, as explained above, independent of doping method.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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