DETAILED ACTION
This non final action is responsive to communications: RCE filed 12/11/2025.
Applicant amended claims 1, 13, and 17; cancelled claims 4-10, and 18-19. No new claims are added. Claims 1-3, 11-17 are pending. Claims 1, 13, and 17 are independent.
Continued Examination under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/11/2025 has been entered.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. D) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 102
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
6. Claims 1-3, and 11-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Watanabe et al. (US 6418067 B1).
Regarding independent claim 1, Watanabe teaches a method for implementing an embedded dynamic memory (operation method of Fig. 1: “DRAM built-in system LSI”. See employed Fig. 1-Fig. 18 circuitry and functionality), wherein
the memory comprises at least one bank each (Fig. 4: one bank. See also Fig. 1 Banks “BA”) of which comprises at least one sub-bank (see Fig. 4: MCB’s);
each of the at least one sub-bank (Fig. 5: MCB. See also Fig. 4: MCB) comprises a storage cell array (col. 15, line 55: memory cell block MCB) and a group of sense amplifiers (Fig. 5 in context of col. 15, lines 52-62: 16 sense amplifier circuits above, below MCB),
each sense amplifier (Fig. 6 circuitry; see also Fig. 5: each SA and associated connected circuitry) comprising an independent read control unit (Fig. 6: RG) and an independent write control unit (Fig. 6: WG);
the independent read control unit (Fig. 6: RG) comprises a set of read control signal lines (see Fig. 6: CSLR and IORL, /IORL),
the independent write control unit (Fig. 6: WG) comprises a set of write control signal lines (see Fig. 6: CSLW and IOWL, /IOWL),
and the set of read control signal lines and the set of write control signal lines are independently separated for signal transmission (Fig. 6 signal lines in context of col. 16, lines 36-51); and
control of various operation modes of the memory is achieved through the read control unit and the write control unit (Fig. 6 in context of col. 20, lines 8-15: operations associated with data read mode and data write mode are controlled by RG, WG, and associated signals).
Regarding claim 2, Watanabe teaches the method according to claim 1, wherein the memory further comprises an input/output control module (Fig. 7 circuitry. See also Fig. 1 data path circuitry) which comprises a plurality of read control modules (Fig. 7: RDL0…RDL31 and associated circuitry) and a plurality of write control modules (Fig. 7: WDL0…WDL31 and associated circuitry).
Regarding claim 3, Watanabe teaches the method according to claim 2, wherein the plurality of sense amplifiers (Fig. 5-Fig. 7: SAG and SA’s) are coupled to one corresponding independent read control module (Fig. 7: RDL0 with column line coupling are independent) and one corresponding independent write control module (Fig. 7: WDL0 with column line coupling are independent).
Regarding claim 11, Watanabe teaches the method according to claim 1, wherein the memory comprises at least two banks (Fig. 1: BA’s) each of which comprises at least two sub-banks (See Fig. 4: MCB’s).
Regarding claim 12, Watanabe teaches the method according to claim 1, wherein each sense amplifier further comprises an amplifying unit and a pre-charging unit that are coupled to a bit line and a reference bit line;
the read control unit comprises a first transistor and a second transistor;
gates of the first transistor and the second transistor are coupled with each other and coupled to a read control signal;
one terminal of the first transistor is coupled to the bit line, and another terminal of the first transistor is coupled to a read control module;
one terminal of the second transistor is coupled to the reference bit line, and another terminal of the second transistor is coupled to the readout control module;
the write control unit comprises a third transistor and a fourth transistor;
gates of the third transistor and the fourth transistor are coupled with each other and coupled to a write control signal;
one terminal of the third transistor is coupled to the bit line, and another terminal of the third transistor is coupled to a write control module; and
one terminal of the fourth transistor is coupled to the reference bit line, and another terminal of the fourth transistor is coupled to the write control module.
(This claim is drafted in method format and is identical to the functionality and limitations of apparatus claim 16 and is rejected for the same reason. See claim 16 rejection analysis)
Regarding independent claim 13, Watanabe teaches an embedded dynamic memory (Fig. 1: “DRAM built-in system LSI” employing Fig. 1-Fig. 18 circuitry and functionality), comprising:
at least one bank each (Fig. 4: one bank. See also Fig. 1 Banks “BA”) of which comprises at least one sub-bank (see Fig. 4: MCB’s);
wherein each of the at least one sub-bank (Fig. 5: MCB. See also Fig. 4: MCB) comprises a storage cell array (col. 15, line 55: memory cell block MCB) and a group of sense amplifiers (Fig. 5 in context of col. 15, lines 52-62: 16 sense amplifier circuits above, below MCB), and
each sense amplifier (Fig. 6 circuitry; see also Fig. 5: each SA and associated connected circuitry) comprises an independent read control unit (Fig. 6: RG) and an independent write control unit (Fig. 6: WG);
wherein the independent read control unit (Fig. 6: RG) comprises a set of read control signal lines (see Fig. 6: CSLR and IORL, /IORL),
the independent write control unit (Fig. 6: WG) comprises a set of write control signal lines (see Fig. 6: CSLW and IOWL, /IOWL),
and the set of read control signal lines and the set of write control signal lines are independently separated for signal transmission (Fig. 6 in context of col. 16, lines 36-51).
Regarding claim 14, Watanabe teaches the embedded dynamic memory according to claim 13 further comprising
an input/output control module (Fig. 7 circuitry. See also Fig. 1 data path circuitry) which comprises
a plurality of read control modules (Fig. 7: RDL0…RDL31 and associated circuitry) and a plurality of write control modules (Fig. 7: WDL0…WDL31 and associated circuitry).,
wherein the plurality of sense amplifiers (Fig. 5-Fig. 7: SA group) are coupled to one corresponding independent read control module (Fig. 7: RDL0) and one corresponding independent write control module (Fig. 7: WDL0).
Regarding claim 15, Watanabe teaches the embedded dynamic memory according to claim 14 comprising at least two banks (Fig. 1: BA) each of which comprises at least two sub-banks (see Fig. 4: bank comprises MCB’s).
Regarding claim 16, Watanabe teaches the embedded dynamic memory according to claim 15, wherein each sense amplifier (Fig. 6 circuitry) further comprises an amplifying unit (Fig. 6: SA) and a pre-charging unit (Fig. 6: P/E) that are coupled to a bit line and a reference bit line (Fig. 6: BLU, /BLU);
the read control unit (Fig. 6: RG) comprises a first transistor and a second transistor (Fig. 6: TGc, TGd);
gates of the first transistor and the second transistor (Fig. 2: 44, 45) are coupled with each other (see gates of Fig. 6: TGc, TGd) and coupled to a read control signal (Fig. 6: CSLR);
one terminal (Fig. 6: bottom terminal) of the first transistor (Fig. 6: TGc) is coupled to the bit line (Fig. 6: BLU via TGe), and another terminal of the first transistor (Fig. 6: top terminal) is coupled to the read control module (Fig. 6: via /IORL);
one terminal (Fig. 6: bottom terminal) of the second transistor (Fig. 6: TGd) is coupled to the reference bit line (Fig. 6: /BLU via TGd), and another terminal (Fig. 6: top terminal) of the second transistor is coupled to the readout control module (Fig. 6: via IORL);
the write control unit (Fig. 6: WG) comprises a third transistor (Fig. 6: TGa) and a fourth transistor (Fig. 6: TGb);
gates of the third transistor and the fourth transistor (see Fig. 6) are coupled with each other (see Fig. 6) and coupled to a write control signal (Fig. 6: CSLW);
one terminal (Fig. 6: top terminal) of the third transistor (Fig. 6: TGa) is coupled to the bit line (Fig. 6: BLU), and another terminal (Fig. 6: bottom terminal) of the third transistor is coupled to the write control module (via Fig. 6: IOWL); and
one terminal (Fig. 6: top terminal) of the fourth transistor (Fig. 6: TGb) is coupled to the reference bit line (Fig. 6: /BLU), and another terminal of the fourth transistor (Fig. bottom terminal) is coupled to the write control module (via Fig. 6: /IOWL).
Regarding independent claim 17, Watanabe teaches an integrated circuit, comprising an embedded dynamic memory, wherein the embedded dynamic memory (Fig. 1: “DRAM built-in system LSI” employing Fig. 1-Fig. 18 circuitry and functionality) comprises:
at least one bank each (Fig. 4: one bank. See also Fig. 1 Banks) of which comprises at least one sub-bank (see Fig. 4: MCB’s);
wherein each of the at least one sub-bank (Fig. 5: MCB. See also Fig. 4: MCB) comprises a storage cell array (col. 15, line 55: memory cell block MCB) and a group of sense amplifiers (Fig. 5 in context of col. 15, lines 52-62: 16 sense amplifier circuits above, below MCB), and
each sense amplifier (Fig. 6 circuitry; see also Fig. 5: each SA and associated connected circuitry) comprises an independent read control unit (Fig. 6: RG) and an independent write control unit (Fig. 6: WG);
wherein the independent read control unit (Fig. 6: RG) comprises a set of read control signal lines (see Fig. 6: CSLR and IORL, /IORL),
the independent write control unit (Fig. 6: WG) comprises a set of write control signal lines (see Fig. 6: CSLW and IOWL, /IOWL), and
the set of read control signal lines and the set of write control signal lines are independently separated for signal transmission (Fig. 6 in context of col. 16, lines 36-51).
Response to Arguments
Applicant’s arguments 12/11/2025 with respect to claim(s) 1, 13, and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. New grounds of rejection added based on newly found reference.
Previous drawing objections and 112b rejections are withdrawn based on claim cancellations and amendments.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
HSU (US 2008/0117698 A1): Fig. 1-Fig. 11 disclosure applicable for all claims.
Bellows et al. (US 2007/0214335 A1): Fig. 1-Fig. 14; para [0024]-para [0025] disclosure applicable for all claims COX (US 2018 / 0254079 A1): Fig. 1-Fig. 8 disclosure applicable for all claims.
It is suggested that applicant consider all prior arts made of record.
Conclusion
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825