Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 23 September 2026 has been entered. Claims 1 and 9 are amended; claim 2 was previously canceled; claims 3–8 and 10 are unchanged; claims 11–20 remain withdrawn. Claims 1 and 3–10 are examined.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claim 9 is objected to because of the following informalities:
In the listing filed 23 September 2026, the dependency of claim 9 is printed as “claim [[1]]]3”, a third closing bracket, neither struck through nor underlined, standing between the deleted “[[1]]” and the inserted “3” (37 CFR 1.121(c)). The claim is examined as depending from claim 3.
Appropriate correction is required.
Claim Interpretation
The following readings are applied under the broadest reasonable interpretation consistent with the specification.
(a) A first time period beginning when the digital signal is output from the latch circuit is a period that begins at the time the digital signal output from the latch circuit takes effect at the digital-to-analog converting circuit: the specification describes the latch circuit as outputting the digital signal at each horizontal time and the digital signal as then transmitted to the digital-to-analog converting circuit [e.g., Instant Specification Paragraph 59: The latch circuit 210 may output pixel image data stored in the latch circuit 210 in the form of a digital signal at each horizontal time according to the latch output signal (LT). Then, this digital signal may be transmitted to the digital-to-analog converting circuit 220], describes the switches of that circuit as changing their on/off state at the time when the digital signal is output, and gives the time of that change and the time of the latch output as alternative statements of the same start of the first time [e.g., Instant Specification Paragraph 70: at the time when the digital signal is output, the switches 222 of the digital-to-analog converting circuit 220 change their on/off state; Instant Specification Paragraph 70: from the time when the switches 222 of the digital-to-analog converting circuit 220 change their on/off state; Instant Specification Paragraph 70: from the time when the digital signal is output from the latch circuit 210]; the transmission from the latch circuit to the converting circuit is part of the arrangement the specification describes with those words.
(b) Noise generated in the digital-to-analog converting circuit is the noise that occurs at the output of that circuit when its switches change state [e.g., Instant Specification Paragraph 66: When a relatively large amount of power is consumed at the time when the multiple switches 222 change the on/off state, noise may occur in the output of the digital-to-analog converting circuit 222].
(c) The recited on/off timing of the input switch and the output switch is what the data driving device is configured to do; claim 9 recites a first mode in which the input switch is continuously turned on during the horizontal time [e.g., Instant Specification Paragraph 77: In this first mode, the input switch of the buffer circuit 230 may also be kept on continuously for the horizontal time; Instant Specification Paragraph 77: In this second mode, the input switch of the buffer circuit 230 may also be turned off for some time during the horizontal time].
(d) Gamma voltages are the voltages used for the digital-to-analog conversion, to which the gamma conversion is applied [e.g., Instant Specification Paragraph 43: the data driving device 110 may convert the digital signal into an analog signal using gamma voltages; Instant Specification Paragraph 44: the data drive device 110 may simultaneously apply digital-to-analog conversion and gamma conversion by using the voltages used for digital-to-analog conversion as voltages to which gamma conversion is applied—gamma voltages].
(e) The parasitic capacitor of claim 8 is the capacitance formed on the data line, which the data driving device sees as its load [e.g., Instant Specification Paragraph 26: A parasitic capacitor may be formed on the data line. The parasitic capacitor may be formed between the data line and the common electrode or between the data line and the pixel electrode. From the standpoint of the data driving device 110 that supplies the data voltage, the parasitic capacitor may be recognized as a load].
(f) The input/output of the buffer circuit of claim 10 are the input terminal of the buffer circuit’s amplifier and the buffer-circuit-side terminal of the output switch [e.g., Instant Specification Paragraph 109: the other input terminal of the amplifier 510 may be maintained at the same voltage as the voltage formed on the data line without floating; Instant Specification Paragraph 115: the buffer circuit side terminal of the output switch may maintain a stable state without floating].
(g) A plurality of switches each connected to a plurality of gamma voltages (claim 6) is read as the specification uses those words of its switches 222, which control the connection between each gamma voltage line and the output of the digital-to-analog converting circuit [e.g., Instant Specification Paragraph 62: a plurality of switches 222 each connected to a plurality of gamma voltages (Vgm); Instant Specification Paragraph 62: The plurality of switches 222 may control the connection between each gamma voltage line 221 and the output of the digital-to-analog converting circuit 220]: a plurality of switches connected to the plurality of gamma voltages, each switch controlling the connection of at least one of them to the output; the claim does not require every switch to be tied directly to more than one gamma voltage.
Claim Rejections - 35 USC § 102 / 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were effectively filed absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned at the time a later invention was effectively filed in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 5 and 8 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Tsuchi (US 2012/0127138 A1; hereinafter Tsuchi ’138); or, in the alternative, under 35 U.S.C. § 103 as being unpatentable over Tsuchi ’138 in view of Umeda et al. (US 2008/0122820 A1).
Regarding claim 1, Tsuchi ’138 discloses a data driving device [e.g., Paragraph 216: the data driver includes a shift register 801, a data register/latch 802, a level shifter group 803, a reference voltage generator circuit 804, a decoder circuit group 805, an output circuit group 806, and a switch control signal generator circuit 807; Fig. 16: 801, 802, 803, 804, 805, 806, 807] comprising:
a latch circuit configured to store pixel image data [e.g., Paragraph 218: latches data every given output number, and outputs the data to the level shifter circuit group 803 according to the control signal; Fig. 16: 802];
a digital-to-analog converting circuit configured to convert a digital signal corresponding to the pixel image data into an analog signal [e.g., Paragraph 218: The decoder circuit group 805 selects one or plural reference voltages corresponding to the input digital data signal from a reference voltage group generated by the reference voltage generator circuit 804 for each output; Paragraph 18: a positive DAC (digital-to-analog converter); Fig. 16: 804, 805];
a buffer circuit [e.g., Paragraph 24: The differential stages 14, 24, and the output stages 13, 23 form an amplifier circuit by the switch circuits 3, 4, 5, and 6; Paragraph 60: the operation of voltage follower; Fig. 8: 100G, 14, 13]
including an input switch [e.g., Paragraph 18: The switch circuit 4 includes switches SW41 to SW44, and controls the respective couplings between terminals 41, 42, and input terminals 12, 22 of the differential stages 14, 24. The terminal 41 receives a positive voltage INP (positive DAC signal) from a positive DAC (digital-to-analog converter) not shown; Paragraph 127: for the purpose of preventing transition noise of a selection signal of a digital to analog converter (DAC) that outputs the input signal VI to the input terminal 101 in FIG. 1 from being input to the output circuit, an input switch is disposed between the output of the DAC and the input terminal 101; Fig. 8: SW41]
controlling connection with the digital-to-analog converting circuit and configured to transmit the analog signal to a pixel [e.g., Paragraph 218: The output circuit group 806 receives the one or plural reference voltages selected by the corresponding decoder of the decoder circuit group 805, and amplifies and outputs a gradation signal corresponding to the input reference voltage. The output terminal group of the output circuit group 806 is coupled to the data lines of the display device; Fig. 16: 806]; and
an output switch configured to control connection between a data line connected to the pixel and the buffer circuit [e.g., Paragraph 23: The switch circuit 3 includes switches SW31 to SW34, and controls the respective couplings between the output terminals 11, 21 of the output stages 13, 23, and an odd terminal 31, an even terminal 32. The odd terminal 31 and the even terminal 32 are coupled to respective drain lines (data lines) on an LCD panel; Fig. 8: SW31, 11, 31],
wherein the input switch is turned off for a first time period [e.g., Paragraph 46: The input switch SW41 (similarly, SW42, SW43, and SW44) is turned off for a given period immediately after switching the output period in which the selected voltage of the DAC is changed (input switch control signal=low), a transition noise of the DAC selected voltage is prevented from being input to the output circuit. Thereafter, the input switch SW41 is turned on (input switch control signal=high), and the selected voltage (positive input voltage) of the positive DAC is input to the differential stage 14; Paragraph 188: the input cutoff period (period t0 to t0a) immediately after start of one output period; Paragraph 204: immediately after start of the output period every one output period (1H); Fig. 9: S1:SW41, t2–t2a]
beginning when the digital signal is output from the latch circuit [e.g., Paragraph 218: latches data every given output number, and outputs the data to the level shifter circuit group 803 according to the control signal; Paragraph 218: The decoder circuit group 805 selects one or plural reference voltages corresponding to the input digital data signal from a reference voltage group generated by the reference voltage generator circuit 804 for each output; Paragraph 46: immediately after switching the output period in which the selected voltage of the DAC is changed],
thereby delaying input of the analog signal to the buffer circuit by the first time period [e.g., Paragraph 46: Thereafter, the input switch SW41 is turned on (input switch control signal=high), and the selected voltage (positive input voltage) of the positive DAC is input to the differential stage 14],
wherein the input switch, while turned off during the first time period, blocks propagation of noise generated in the digital-to-analog converting circuit to the buffer circuit by controlling the electrical connection between the digital-to-analog converting circuit and the buffer circuit [e.g., Paragraph 127: for the purpose of preventing transition noise of a selection signal of a digital to analog converter (DAC) that outputs the input signal VI to the input terminal 101 in FIG. 1 from being input to the output circuit, an input switch is disposed between the output of the DAC and the input terminal 101; Paragraph 172: the switch circuit 4 (SW41 to SW44) that conducts the input control of the positive DAC/negative DAC signal to the output circuit 100F is controlled so that the input of the positive DAC/negative DAC signal to the output circuit 100 is temporarily cut off for each output period for the purpose of preventing signal shorting from occurring between the positive DAC and the negative DAC signal, and also for the purpose of preventing the transition noise of the DAC selection signal from being input to the output circuit; Paragraph 46: The input switch SW41 (similarly, SW42, SW43, and SW44) is turned off for a given period immediately after switching the output period in which the selected voltage of the DAC is changed (input switch control signal=low), a transition noise of the DAC selected voltage is prevented from being input to the output circuit. Thereafter, the input switch SW41 is turned on (input switch control signal=high), and the selected voltage (positive input voltage) of the positive DAC is input to the differential stage 14], and
wherein the output switch is turned off during the first time period to release the connection between the data line and the buffer circuit [e.g., Paragraph 192: the off period of the switch circuit 3 (SW31 to SW34) that switches the coupling between the output terminals 11, 21 of the output circuit 100G in FIG. 8 and the data lines (odd, even) is preferably set to include the off period of the switch circuit 4 (SW41 to SW44); Paragraph 173: The switch circuit 3 is controlled to temporarily cut off the output from the output nodes (11, 21) to the data lines for each output period; Paragraph 127: an output switch is disposed between the output circuit and a data line load. In this case, the given period during which the switch 162 is kept on may be identical with a period during which the output switch is kept off at the time of switching the output period; Paragraph 193: a period in which the switches SW31 and SW33 are off includes duration of the period in which the switches SW41 and SW43 are off; Fig. 9: SW31, SW33] (e.g., see Paragraphs 17–24, 43–46, 127, 171–194 and 216–218; Figs. 8, 9 and 16).
The output circuit relied on is the seventh embodiment (FIG. 8, output circuit 100G; timing chart FIG. 9),
which Tsuchi ’138 describes as the related-art output circuit of its FIGS. 18 and 19 with the control circuits 160A and 170A added [e.g., Paragraph 177: FIG. 8 illustrates a configuration (160A, 170A) in which the control circuits 160 and 170 according to the first and second embodiments are applied to the positive dedicated output stage 13 and the negative dedicated output stage 23 in the related art of FIGS. 18 and 19, respectively],
as the sixth embodiment is with the control circuits 160 and 170 [e.g., Paragraph 171: this embodiment has a configuration (output circuit 100F) in which the control circuits 160 and 170 according to the first and second embodiments are applied to the positive dedicated output stage 13 and the negative dedicated output stage 23 in the related art illustrated in FIGS. 18 and 19, respectively];
the switch circuits 3 (SW31 to SW34) and 4 (SW41 to SW44) are parts of the amplifier circuit that the differential stages, the output stages and the switch circuits form [e.g., Paragraph 24: The differential stages 14, 24, and the output stages 13, 23 form an amplifier circuit by the switch circuits 3, 4, 5, and 6] and are drawn in FIG. 8, and
the tenth embodiment places the output circuits in the data driver [e.g., Paragraph 217: the output circuits 100A to 100I; Fig. 16: 806].
One channel in one output period carries every element: terminal 41 → SW41 → differential stage 14 → output stage 13 → output terminal 11 → SW31 → odd terminal 31 → data line, SW41 being off in the input cutoff period at the start of the output period [e.g., Paragraph 189: When the polarity inverting signal (POL) is high, in the input cutoff period (periods t1 to t1a, t2 to t3, t3a to t4) immediately after start of one output period, the control signals S1 and S3 are high and low, respectively, the switches SW41 and SW43 are off] and the off period of SW31 including it [e.g., Paragraph 193: a period in which the switches SW31 and SW33 are off includes duration of the period in which the switches SW41 and SW43 are off; Fig. 9: SW31, SW33; S1:SW41].
As to the first time period beginning when the digital signal is output from the latch circuit (Claim Interpretation, item (a)): in Tsuchi ’138 the data register/latch 802 outputs the digital data according to the control signal, the level shifter group 803 converts it in level and passes it to the decoder circuit group 805, and the decoder’s selected voltage changes accordingly [e.g., Tsuchi ’138, Paragraph 218: latches data every given output number, and outputs the data to the level shifter circuit group 803 according to the control signal; Paragraph 218: The level shifter group 803 converts the digital data signal of each output unit output from the data register/latch 802 from a low-amplitude signal to a high-amplitude signal in level, and outputs the signal to the decoder circuit group 805; Paragraph 218: The decoder circuit group 805 selects one or plural reference voltages corresponding to the input digital data signal from a reference voltage group generated by the reference voltage generator circuit 804 for each output];
the output period switches with that change, and the input cutoff period begins immediately after the switching of the output period in which the selected voltage of the DAC is changed [e.g., Tsuchi ’138, Paragraph 46: The input switch SW41 (similarly, SW42, SW43, and SW44) is turned off for a given period immediately after switching the output period in which the selected voltage of the DAC is changed (input switch control signal=low), a transition noise of the DAC selected voltage is prevented from being input to the output circuit. Thereafter, the input switch SW41 is turned on (input switch control signal=high), and the selected voltage (positive input voltage) of the positive DAC is input to the differential stage 14].
The cutoff period therefore begins when the digital signal output from the latch circuit takes effect at the digital-to-analog converting circuit, which is what the specification itself describes as the time when the digital signal is output: its own latch circuit outputs the digital signal, which is then transmitted to the converting circuit [e.g., Instant Specification Paragraph 59: The latch circuit 210 may output pixel image data stored in the latch circuit 210 in the form of a digital signal at each horizontal time according to the latch output signal (LT). Then, this digital signal may be transmitted to the digital-to-analog converting circuit 220], and
it states the time of the switch change and the time of the latch output as the same start [e.g., Instant Specification Paragraph 70: at the time when the digital signal is output, the switches 222 of the digital-to-analog converting circuit 220 change their on/off state; Instant Specification Paragraph 70: from the time when the switches 222 of the digital-to-analog converting circuit 220 change their on/off state; Instant Specification Paragraph 70: from the time when the digital signal is output from the latch circuit 210] — a period beginning when the digital signal is output from the latch circuit under item (a).
Should it be shown that Tsuchi ’138 discloses the input switch being turned off for a first time period beginning when the digital signal is output from the latch circuit with insufficient specificity:
Umeda discloses a data driver whose latch circuit 11 stores the digital gradation data and outputs it to the decoding circuit 13 [e.g., Umeda, Paragraph 31: This parallel data D00 to D05 is input and stored sequentially in the latch circuit 11 provided for every output unit and output to the decoding circuit 13 all at once at a predetermined timing; Paragraph 32: On and off of the switching devices are controlled by the digital gradation data D00 to D05 sent from the latch circuit 11; Fig. 2: 11, 13, 15, SWout1–SWout720],
that a signal noise is generated in the decoding circuit when the data switches for every data output period, and that the output switches are turned off from the start of the data output period so that the data lines are separated from the voltage followers while that noise is present [e.g., Umeda, Paragraph 33: when data switches for every data output period, a signal noise is generated in the decoding circuit 13 or the like; Paragraph 33: In order to prevent from outputting this signal noise to the data lines 16, the output switches SWout1 to SWout720 are turned off from the start of the data output period to the predetermined period and the data lines 16 and the voltage followers 15 are separated];
the switching operations of each data output period, which is one selection period and is repeated for each gate line, are keyed to the timing at which the digital gradation data is output from the latch circuit to the decoding circuit [e.g., Umeda, Paragraph 41: Immediately before turning on the switches SW1 to SW4, the output switches SWout1 to SWout720 are turned off; Paragraph 41: at the timing when the digital gradation data D00 to D05 is output from the latch circuit 11 to the decoding circuit 13, the switches SW1 to SW4 are turned on; Paragraph 41: one selection period; Paragraph 42: These operations are performed for each gate line; Fig. 5], and
the output-switch off period may be made to coincide with the period that begins at that timing [e.g., Umeda, Paragraph 42: the first period to turn off the output switches SWout1 to SWout720 may be conformed to the period to turn on the switches SW1 to SW4].
In Umeda’s illustrated timing the output switches open immediately before the switches SW1 to SW4 turn on at the latch-output timing, and in the variant just cited the two periods coincide; the event Umeda uses as the timing reference of the data output period is the latch output.
Tsuchi ’138 and Umeda are analogous art: each is a data driver for a display panel that keeps the transition noise arising when the decoder’s selected voltage changes at the start of an output period away from the data line, the problem the applicant addresses.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to begin the input cutoff period of Tsuchi ’138 at the timing at which the data register/latch 802 outputs the digital data to the decoder circuit group 805, as Umeda keys the noise-guard switching of each data output period to the timing at which its latch circuit outputs the digital gradation data to the decoding circuit [e.g., Umeda, Paragraph 41: at the timing when the digital gradation data D00 to D05 is output from the latch circuit 11 to the decoding circuit 13, the switches SW1 to SW4 are turned on],
because Umeda teaches that the decoding circuit’s noise arises when the data switches for every data output period [e.g., Umeda, Paragraph 33: when data switches for every data output period, a signal noise is generated in the decoding circuit 13 or the like] and
Tsuchi ’138 places its cutoff at that very change [e.g., Tsuchi ’138, Paragraph 46: immediately after switching the output period in which the selected voltage of the DAC is changed]:
the latch output is the event that produces the change, so timing the cutoff from it is the use of a known timing reference for its known purpose, with the predictable result of a cutoff that begins when the transition noise begins; the off period of switch circuit 3 is set, as Tsuchi ’138 prescribes, to include the input cutoff period so timed [e.g., Tsuchi ’138, Paragraph 192: the off period of the switch circuit 3 (SW31 to SW34) that switches the coupling between the output terminals 11, 21 of the output circuit 100G in FIG. 8 and the data lines (odd, even) is preferably set to include the off period of the switch circuit 4 (SW41 to SW44)],
so that the output switch remains off during the first time period as in FIG. 9.
KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007); Graham v. John Deere Co., 383 U.S. 1 (1966).
Umeda is relied on for the timing of the period only; the input switch, its cutoff and its purpose are Tsuchi ’138’s, and Umeda’s own use of the interval to charge its follower inputs is not borrowed:
Tsuchi ’138 accepts the delayed input as the price of the isolation [e.g., Tsuchi ’138, Paragraph 46: Thereafter, the input switch SW41 is turned on (input switch control signal=high), and the selected voltage (positive input voltage) of the positive DAC is input to the differential stage 14].
Regarding claim 5, Tsuchi ’138 discloses the input switch and the output switch operate in synchronization [e.g., Paragraph 217: The switch control signal generator circuit 807 generates a signal for controlling the on/off operation of the switch 162, 172, 164, 174, the switches SW31, SW33, SW41, SW43; Paragraph 184: S1 to S4; Paragraph 192: the off period of the switch circuit 3 (SW31 to SW34) that switches the coupling between the output terminals 11, 21 of the output circuit 100G in FIG. 8 and the data lines (odd, even) is preferably set to include the off period of the switch circuit 4 (SW41 to SW44); Paragraph 185: in synchronism with the inversion of the polarity inverting signal; Fig. 9: SW31, SW33; S1:SW41 — the SW31/SW33 off window brackets the S1 pulse].
The alternative branch changes nothing for claim 5: Umeda is not relied on for it.
Regarding claim 8, Tsuchi ’138 discloses a parasitic capacitor is formed on the data line [e.g., Paragraph 45: data line load (wiring equivalent circuit configured by multistage of resistors and capacitors) with a total capacity of 200 pF],
wherein the output switch, when turned off, is configured to release a connection between the parasitic capacitor formed on the data line and the buffer circuit [e.g., Paragraph 173: The switch circuit 3 is controlled to temporarily cut off the output from the output nodes (11, 21) to the data lines for each output period; Paragraph 127: an output switch is disposed between the output circuit and a data line load. In this case, the given period during which the switch 162 is kept on may be identical with a period during which the output switch is kept off at the time of switching the output period; Fig. 8: SW31, 11, 31].
The data line load of Tsuchi ’138 — the wiring equivalent circuit of resistors and capacitors with a total capacity of 200 pF — is the capacitance formed on the data line (Claim Interpretation, item (e)).
The alternative branch changes nothing for claim 8: Umeda is not relied on for it.
Claim Rejections - 35 USC § 103
Claims 3 and 4 are rejected under 35 U.S.C. § 103 as being unpatentable over Tsuchi ’138 in view of Kong et al. (US 2018/0315390 A1);
or, in the alternative, under 35 U.S.C. § 103 as being unpatentable over Tsuchi ’138 in view of Umeda as applied to claim 1 above, and further in view of Kong.
The base for claims 3 and 4 is Tsuchi ’138 as applied to claim 1:
in the first branch Tsuchi ’138 alone, anticipating claim 1;
in the alternative branch Tsuchi ’138 in view of Umeda,
Umeda supplying the latch-output timing of the first time period as stated for claim 1.
In the claim-3 and claim-4 blocks below every bracket names its reference; the brackets to Umeda belong to the alternative branch, and in the first branch the brackets to Tsuchi ’138 stand alone.
Please note: stricken-through text marks claim subject matter not taught by the named reference.
Regarding claim 3, Tsuchi ’138 discloses
wherein the digital signal is output from the latch circuit according to the latch output signal [e.g., Tsuchi ’138, Paragraph 218: latches data every given output number, and outputs the data to the level shifter circuit group 803 according to the control signal] [e.g., Umeda, Paragraph 31: output to the decoding circuit 13 all at once at a predetermined timing; Paragraph 41: at the timing when the digital gradation data D00 to D05 is output from the latch circuit 11 to the decoding circuit 13, the switches SW1 to SW4 are turned on],
wherein the input switch is turned off for the first time period from the time when the digital signal is output [e.g., Tsuchi ’138, Paragraph 46: The input switch SW41 (similarly, SW42, SW43, and SW44) is turned off for a given period immediately after switching the output period in which the selected voltage of the DAC is changed (input switch control signal=low), a transition noise of the DAC selected voltage is prevented from being input to the output circuit. Thereafter, the input switch SW41 is turned on (input switch control signal=high), and the selected voltage (positive input voltage) of the positive DAC is input to the differential stage 14; Paragraph 178: in the input cutoff period immediately after start of each output period by the switch circuit 4 (SW41 to SW44)] [e.g., Umeda, Paragraph 41: at the timing when the digital gradation data D00 to D05 is output from the latch circuit 11 to the decoding circuit 13, the switches SW1 to SW4 are turned on].
Tsuchi ’138 does not expressly disclose the timing control circuit — a circuit that generates, at each horizontal time, the signal on which the latch outputs the digital signal: it names the control signal on which its data register/latch 802 outputs the data, the display controller 950 that supplies the driver’s control signals and the switch control signal generator circuit 807 that generates the switch signals [e.g., Tsuchi ’138, Paragraph 218: latches data every given output number, and outputs the data to the level shifter circuit group 803 according to the control signal; Paragraph 5: Necessary clock CLK and control signals are supplied from the display controller 950 to the gate driver 970 and the data driver 980; Paragraph 204: immediately after start of the output period every one output period (1H); Paragraph 217: The switch control signal generator circuit 807 generates a signal for controlling the on/off operation of the switch 162, 172, 164, 174, the switches SW31, SW33, SW41, SW43], without describing the generation of that signal;
nor, in the alternative branch, does Umeda, which keys each data output period, repeated for each gate line, to the timing at which its latch outputs the data [e.g., Umeda, Paragraph 41: one selection period; Paragraph 42: These operations are performed for each gate line; Paragraph 41: at the timing when the digital gradation data D00 to D05 is output from the latch circuit 11 to the decoding circuit 13, the switches SW1 to SW4 are turned on] without naming the circuit.
Kong discloses a timing control circuit — the timing controller 200 with its control logic 210 — that receives the horizontal synchronization signal Hsync and generates the data driver control signal CTRL2 [e.g., Kong, Paragraph 49: the timing controller 200 may receive, from an external device (e.g., a host device (not illustrated)), image data RGB and timing signals (e.g., a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a clock signal DCLK, and a data enable signal DE) and may generate the scan driver control signal CTRL1 and the data driver control signal CTRL2; Paragraph 50: The control logic 210 may generate a control signal for controlling the operation of the data driver 300 based on the analysis result and may provide the data driver 300 with the generated control signal as the data driver control signal CTRL2; Fig. 1: 500 (display driving circuit), 200, 210, 300, CTRL2, Hsync], and
a data driver that outputs the pixel data of one line, at each horizontal driving period 1H, in synchronization with Hsync or with a timing signal generated based on Hsync [e.g., Kong, Paragraph 92: The shift register 350b may store the image data DATA, for example, pixel data of one line, which is provided by the timing controller 300 (of FIG. 1) and may output the pixel data of one line in synchronization with the synchronization signal Hsync (of FIG. 5) or a timing signal generated based on the horizontal synchronization signal Hsync; Paragraph 79: horizontal driving period 1H] —
a per-line timing signal, generated from the horizontal synchronization signal, on which the line data is output. (Kong’s Paragraph 92 refers to the timing controller as 300; its FIG. 1 numbers it 200.)
Tsuchi ’138, Umeda and Kong are analogous art, each being a data driving circuit for a display panel in which digital pixel data is latched, converted and driven onto the data lines line by line, the field of the claimed invention.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the data driver of Tsuchi ’138 (in the alternative branch, of Tsuchi ’138 and Umeda) with Kong’s timing controller as the circuit that generates, from Hsync at each horizontal time, the timing signal on which the data register/latch 802 outputs the digital data — the latch output signal — because Tsuchi ’138 requires its control signals to be supplied from a display controller [e.g., Tsuchi ’138, Paragraph 5: Necessary clock CLK and control signals are supplied from the display controller 950 to the gate driver 970 and the data driver 980],
Kong’s timing controller is the circuit that receives the horizontal synchronization signal and generates the data driver’s control signals [e.g., Kong, Paragraph 49: the timing controller 200 may receive, from an external device (e.g., a host device (not illustrated)), image data RGB and timing signals (e.g., a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a clock signal DCLK, and a data enable signal DE) and may generate the scan driver control signal CTRL1 and the data driver control signal CTRL2], and
the per-line output of the data on a timing signal generated based on Hsync that Kong describes [e.g., Kong, Paragraph 92: The shift register 350b may store the image data DATA, for example, pixel data of one line, which is provided by the timing controller 300 (of FIG. 1) and may output the pixel data of one line in synchronization with the synchronization signal Hsync (of FIG. 5) or a timing signal generated based on the horizontal synchronization signal Hsync] is the operation Tsuchi ’138’s latch already performs on its control signal [e.g., Tsuchi ’138, Paragraph 218: latches data every given output number, and outputs the data to the level shifter circuit group 803 according to the control signal], so that supplying the named circuit to generate that signal is the use of a known element for its known purpose with predictable results.
KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007); Graham v. John Deere Co., 383 U.S. 1 (1966).
Regarding claim 4, Tsuchi ’138 discloses
wherein the output switch is turned off for the first time period from the time when the digital signal is output [e.g., Tsuchi ’138, Paragraph 192: the off period of the switch circuit 3 (SW31 to SW34) that switches the coupling between the output terminals 11, 21 of the output circuit 100G in FIG. 8 and the data lines (odd, even) is preferably set to include the off period of the switch circuit 4 (SW41 to SW44); Paragraph 193: a period in which the switches SW31 and SW33 are off includes duration of the period in which the switches SW41 and SW43 are off; Paragraph 173: The switch circuit 3 is controlled to temporarily cut off the output from the output nodes (11, 21) to the data lines for each output period; Fig. 9: SW31, SW33 — off from before t2 until after t2a] [e.g., Umeda, Paragraph 33: In order to prevent from outputting this signal noise to the data lines 16, the output switches SWout1 to SWout720 are turned off from the start of the data output period to the predetermined period and the data lines 16 and the voltage followers 15 are separated; Paragraph 41: Immediately before turning on the switches SW1 to SW4, the output switches SWout1 to SWout720 are turned off; Paragraph 42: the first period to turn off the output switches SWout1 to SWout720 may be conformed to the period to turn on the switches SW1 to SW4]
Tsuchi ’138’s switch control signal generator circuit 807 generates the control signals of switch circuit 3 [e.g., Tsuchi ’138, Paragraph 217: The switch control signal generator circuit 807 generates a signal for controlling the on/off operation of the switch 162, 172, 164, 174, the switches SW31, SW33, SW41, SW43], and,
in the alternative branch, Umeda’s output switches are controlled by its control signal 2 [e.g., Umeda, Paragraph 33: on and off are controlled by the control signal 2];
neither expressly discloses the timing control circuit being further configured to generate the output enable signal that controls the output switch, the output switch being turned off according to it.
Kong discloses that its timing controller’s control logic generates, among the data driver control signals, the first and second output control signals OC1 and OC2, in response to which the output switches OSW1 and OSW2 between the amplifier output nodes and the output pads are turned on and off [e.g., Kong, Paragraph 66: the control signals may include the first enable signal EN1, the second enable signal EN2, the first output control signal OC1, the second output control signal OC2, and the connection control signal CON; Paragraph 65: The first output switch OSW1 may be connected between an output node the first amplifier SA1 and the first output pad OP1 and may be turned on in response to a first output control signal OC1; Paragraph 65: The second output switch OSW2 may be connected between an output node of the second amplifier SA2 and the second output pad OP2 and may be turned on in response to a second output control signal OC2] — the output enable signal, generated by the timing control circuit.
The division of labor is as for claim 3: Kong’s timing controller generates the output control signal by which the output switch is turned on and off; the waveform of that signal in the combination is Tsuchi ’138’s, whose switch circuit 3 is off over a window that includes the input cutoff period from the switching of the output period, and,
in the alternative branch, Umeda’s, whose output switches are turned off from the start of the data output period, the off period being conformable to the period that begins at the latch output. An output switch that is off throughout a window including the first time period is turned off for the first time period from the time the digital signal is output; the claim does not exclude the switch being off before that time as well.
The reason to combine is the one stated for claim 3, the output control signal being one of the control signals Kong’s timing controller generates for the data driver.
KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007); Graham v. John Deere Co., 383 U.S. 1 (1966).
Claim 6 is rejected under 35 U.S.C. § 103 as being unpatentable over Tsuchi ’138 in view of Hsueh et al. (US 2011/0090198 A1) and Texas Instruments, FPD33584 TFT-LCD Column Driver datasheet, SNOSA12A (May 2004, revised October 2011) (hereinafter the FPD33584 datasheet);
or, in the alternative, under 35 U.S.C. § 103 as being unpatentable over Tsuchi ’138 in view of Umeda as applied to claim 1 above, and further in view of Hsueh and the FPD33584 datasheet.
Regarding claim 6, Tsuchi ’138 discloses the digital-to-analog converting circuit [e.g., Paragraph 218: The decoder circuit group 805 selects one or plural reference voltages corresponding to the input digital data signal from a reference voltage group generated by the reference voltage generator circuit 804 for each output; Fig. 16: 804, 805]
wherein one of the plurality ofThe decoder circuit group 805 selects one or plural reference voltages corresponding to the input digital data signal from a reference voltage group generated by the reference voltage generator circuit 804 for each output; Paragraph 127: for the purpose of preventing transition noise of a selection signal of a digital to analog converter (DAC) that outputs the input signal VI to the input terminal 101 in FIG. 1 from being input to the output circuit, an input switch is disposed between the output of the DAC and the input terminal 101]
Tsuchi ’138’s decoder circuit group 805 selects one of the reference voltages generated by the reference voltage generator circuit 804 according to the input digital data, and its selection signal is what changes when the data changes;
Tsuchi ’138 does not expressly disclose the decoder as a plurality of switches each connected to a plurality of the reference voltages, whose on/off is determined according to the digital signal and whose on/off state determines the selected voltage, and does not expressly disclose that its reference voltages are gamma voltages, voltages to which the gamma conversion is applied (Claim Interpretation, item (d)).
In the alternative branch, Umeda discloses that each decoding unit circuit is formed by six switching devices in series, each input with the digital gradation data at a control end, the gradation potentials being supplied to the switching devices and the potential with all six switching devices on being output [e.g., Umeda, Paragraph 32: Each decoding unit circuit can be formed by 6 switching devices in series that are each input with the digital gradation data D00 to D05 to a control end; Paragraph 32: On and off of the switching devices are controlled by the digital gradation data D00 to D05 sent from the latch circuit 11; Fig. 3: 13];
Umeda does not expressly disclose each switch being connected to a plurality of the voltages.
Hsueh discloses a DAC decoder 600 that includes a plurality of transistors 602 arranged in a plurality of columns [e.g., Hsueh, Paragraph 24: the decoder 600 includes a plurality of transistors 602 arranged in a plurality of columns; Fig. 6: 600, 602, 604-1 to 604-6],
the decoder being formed of switches that decode the digital input code [e.g., Hsueh, Paragraph 5: they require a plurality of switches to decode the 10-bit input code],
each transistor of the first column being coupled to a conductive lead that provides a respective one of the voltage levels supplied from the resistor string [e.g., Hsueh, Paragraph 24: Each transistor 602 in a column 602-1 is coupled to a conductive lead that provides a respective voltage level from the six-bit DAC; Paragraph 22: 128 voltage levels each received on a separate conductor line; Fig. 6: FROM 6-BIT R-STRING],
the outputs of the transistors of each column being coupled in pairs and the outputs of one column being the inputs of the transistors of the next [e.g., Hsueh, Paragraph 24: The output of each transistor 602 in each of the columns 604 is coupled to the output of another transistor 602 in the same column; Paragraph 24: The outputs from one column e.g., column 604-1, are used as the inputs for the transistors in next column, e.g., column 604-2] —
so that each transistor of the second and later columns is connected, through the transistors of the preceding column, to a plurality of the voltage levels, and the transistors of the decoder are a plurality of switches each connected to a plurality of the voltages (Claim Interpretation, item (g)) —
wherein the turning on and off of each transistor in a column is controlled by the same bit of the multi-bit digital input code and the decoder outputs one voltage level in response [e.g., Hsueh, Paragraph 25: The turning on and off of each of the transistors 602 in a column is controlled by the same bit of the multi-bit digital input code; Paragraph 25: the DAC decoder 600 decodes a digital input code and outputs a voltage level in response; Fig. 6: B0–B5, OUTPUT];
Hsueh does not expressly disclose that its voltage levels are gamma voltages (its example spaces them uniformly [e.g., Hsueh, Paragraph 23: the voltage levels received by the MSB DAC decoder 402 differ by approximately 0.3 volts from each other]).
The FPD33584 datasheet discloses a TFT-LCD column driver whose digital-to-analog conversion selects, for each gray level command, an output voltage level from reference voltages set to the gamma characteristic of the display — gamma voltages [e.g., FPD33584 datasheet, page 1: Output voltages are gamma corrected to provide a direct mapping between digital video and LCD panel brightness; page 8: The output voltage levels corresponding to each of the 64 gray level commands can be externally adjusted to match the desired gamma characteristics of the display by means of two internal resistor-string DACs (RDACs); page 11: VGMA1–VGMA10—RDAC References (input) The reference voltages to the upper and lower RDACs used to control the inverse gamma transfer function of the driver; page 9: all of which have been carefully designed to accurately match the natural, inverse gamma of a twisted nematic (TN) display with a 2.2 gamma transfer characteristic].
Tsuchi ’138, Hsueh and the FPD33584 datasheet are analogous art, all being drivers for LCD panels whose decoders select an output voltage from a set of reference voltages according to the digital data.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the decoder circuit group 805 of Tsuchi ’138 with the transistor-column decoder of Hsueh, because Tsuchi ’138 assigns its decoder exactly the function Hsueh’s decoder performs — selecting the reference voltage designated by the bits of the digital data — and Hsueh’s transistor-column decoder is a known structure for that function, decoding the input code to output one voltage level and scaled in columns and transistors to the number of bits decoded [e.g., Hsueh, Paragraph 25: the DAC decoder 600 decodes a digital input code and outputs a voltage level in response; Paragraph 24: One skilled in the art will understand that the number of columns as well as the number of transistors in each column may be varied depending on the number of bits the DAC decoder 600 decodes], so that the substitution is the use of a known decoder structure for its known function with predictable results; and
it would have been obvious to set the reference voltage group of Tsuchi ’138’s reference voltage generator circuit 804, from which the decoder selects, to the gamma characteristic of the display as the FPD33584 datasheet does, because the datasheet states that purpose for a column driver’s reference voltages — matching the output voltage levels to the desired gamma characteristics of the display [e.g., FPD33584 datasheet, page 8: The output voltage levels corresponding to each of the 64 gray level commands can be externally adjusted to match the desired gamma characteristics of the display by means of two internal resistor-string DACs (RDACs)] — with the predictable result of a gradation signal mapped to the panel’s brightness.
KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007); Graham v. John Deere Co., 383 U.S. 1 (1966).
The same reasons apply in the alternative branch, whose base already selects by switching devices gated by the data bits (Umeda) and takes from Hsueh the structure by which the switches are each connected to a plurality of the reference voltages and from the FPD33584 datasheet the gamma-shaped reference set.
Claim 7 is rejected under 35 U.S.C. § 103 as being unpatentable over Tsuchi ’138 in view of the FPD33584 datasheet;
or, in the alternative, under 35 U.S.C. § 103 as being unpatentable over Tsuchi ’138 in view of Umeda as applied to claim 1 above, and further in view of the FPD33584 datasheet.
Regarding claim 7, Tsuchi ’138 discloses the latch circuit, the digital-to-analog converting circuit and the buffer circuit [e.g., Paragraph 218: are each configured by a logic circuit, generally have a low voltage (for example, 0V to 3.3V); Paragraph 218: The level shifter group 803, the decoder circuit group 805, and the output circuit group 806 each have a high voltage (for example, 0V to 18V); Paragraph 19: between a negative supply voltage VSS (for example, GND potential) and a positive supply voltage VDD]
Tsuchi ’138 discloses that its shift register and data register/latch are logic circuits at a low voltage (for example, 0 V to 3.3 V) while its level shifter group, decoder circuit group and output circuit group are at a high voltage (for example, 0 V to 18 V),
the differential stages operating between a negative supply voltage VSS, for example GND potential, and VDD; it does not expressly disclose that the latch circuit,
the digital-to-analog converting circuit and the buffer circuit share a ground, and
Umeda does not expressly disclose the supply arrangement of its latch circuit, decoding circuit and voltage followers.
The FPD33584 datasheet discloses a TFT-LCD column driver in which the digital video buffered by the shift register is copied into a second latch for conversion to analog [e.g., FPD33584 datasheet, page 10: The rising edge of CLK1 copies the digital video buffered by the shift register into a second latch for conversion to analog],
the digital logic functions of the driver being supplied from VDD1 and its analog functions — the resistor-string DACs and the output amplifiers — from VDD2 [e.g., FPD33584 datasheet, page 11: VDD1—Digital Voltage Supply (power) Positive supply voltage for the digital logic functions of the driver. Nominally 3.3V; page 11: VDD2—Analog Voltage Supply (power) Positive supply voltage for the analog functions of the driver; page 11: VGMA1–VGMA10—RDAC References (input) The reference voltages to the upper and lower RDACs used to control the inverse gamma transfer function of the driver], and
in which the digital ground VSS1 is typically tied to the analog ground VSS2, and VSS2 to VSS1, on the printed circuit board [e.g., FPD33584 datasheet, page 11: VSS1—Digital Ground (power) Digital ground reference voltage. Typically tied to VSS2 on the PCB; page 11: VSS2—Analog Ground (power) Analog ground reference voltage. Typically tied to VSS1 on the PCB] — the latch, the digital-to-analog conversion and the output amplifiers referenced to one shared ground.
Tsuchi ’138 and the FPD33584 datasheet are analogous art, both being column (data) drivers for TFT-LCD panels with a shift register, a latch, reference-voltage digital-to-analog conversion and output amplifiers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to reference the low-voltage logic domain and the high-voltage analog domain of Tsuchi ’138’s data driver to one shared ground as the FPD33584 datasheet describes as typical, because the datasheet states that tying the digital and analog ground references together is the typical arrangement for exactly this class of driver, and
Tsuchi ’138’s two domains both extend from 0 V [e.g., Tsuchi ’138, Paragraph 218: are each configured by a logic circuit, generally have a low voltage (for example, 0V to 3.3V); Paragraph 218: The level shifter group 803, the decoder circuit group 805, and the output circuit group 806 each have a high voltage (for example, 0V to 18V)],
so that a common ground reference for the latch, the decoder and the output circuit is the ordinary board practice applied to a driver ready for it, with predictable results.
KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007); Graham v. John Deere Co., 383 U.S. 1 (1966).
The same reason applies in the alternative branch, which adds nothing bearing on the ground of the circuits.
Claims 9 and 10 are rejected under 35 U.S.C. § 103 as being unpatentable over Tsuchi ’138 in view of Kong as applied to claim 3 above, and further in view of Kawagoshi (US 2011/0018853 A1);
or, in the alternative, under 35 U.S.C. § 103 as being unpatentable over Tsuchi ’138 in view of Umeda and Kong as applied to claim 3 above, and further in view of Kawagoshi.
The base for claims 9 and 10 is the combination stated for claim 3, in either of its branches: Tsuchi ’138 in view of Kong, or Tsuchi ’138 in view of Umeda and Kong; Umeda’s contribution — the latch-output timing — is the same here, and nothing below depends on it.
Regarding claim 9, Tsuchi ’138 discloses the input switch is,The input switch SW41 (similarly, SW42, SW43, and SW44) is turned off for a given period immediately after switching the output period in which the selected voltage of the DAC is changed (input switch control signal=low), a transition noise of the DAC selected voltage is prevented from being input to the output circuit. Thereafter, the input switch SW41 is turned on (input switch control signal=high), and the selected voltage (positive input voltage) of the positive DAC is input to the differential stage 14; Paragraph 178: in the input cutoff period immediately after start of each output period by the switch circuit 4 (SW41 to SW44); Fig. 9: S1:SW41].
Tsuchi ’138 turns its input switch SW41 off for the input cutoff period at the start of each output period, the operation of the second mode; it does not expressly disclose a first mode in which the input switch is continuously turned on during the horizontal time.
In the alternative branch Umeda does not expressly disclose a switch between its decoding circuit and its voltage followers;
Kong’s normal and low-power operation modes are not relied on for this limitation, the express teaching of Kawagoshi being relied on in preference.
Kawagoshi discloses a signal line driving circuit in which the input switches SW16 and SW17 connect the amplifier inputs to the DA converter at the pre-stage [e.g., Kawagoshi, Paragraph 41: Upon turning on of the input switches SW16 and SW17, the inputs of the odd-numbered amplifier AMP 11 and the even-numbered amplifier AMP 12 are connected to a DA converter (not shown) which is provided at the pre-stage; Paragraph 29: A non-inverting input terminal of the odd-numbered amplifier AMP11 is connected to the input switch SW16; Fig. 1: SW16, AMP11] and
a voltage monitor circuit CIR31 controls those input switches according to the comparison results of the comparators COM31 and COM32 [e.g., Kawagoshi, Paragraph 50: controls the charge share switches SW12 and SW13 and the input switches SW16 and SW17 according to the comparison results of the comparators COM31 and COM32; Paragraph 44: Components in FIG. 3 that are identical to those of FIG. 1 are denoted by the same reference symbols; Fig. 3: CIR31, COM31, COM32, SW16, SW17]:
when the amplitude at the time of dot inversion is greater than a predetermined value, the input switches SW16 and SW17 are turned off during the charge sharing operation at the beginning of the horizontal period and are turned on at its end [e.g., Kawagoshi, Paragraph 50: when the amplitude at the time of dot inversion is greater than a predetermined value; Paragraph 51: during the charge sharing operation, the charge share switches SW12 and SW13 are turned on and the input switches SW16 and SW17 are turned off; Paragraph 37: the charge sharing operation period is provided at the beginning of one horizontal period; Paragraph 40: in response to the falling edge of the strobe signal STB, the charge share switches SW11, SW12, and SW13 are turned off, and at the same time, the output switches SW14 and SW15 and the input switches SW16 and SW17 are turned on] —
the second mode, in which the input switch is turned off during part of the horizontal time; when the amplitude is equal to or less than the predetermined value, the input switches SW16 and SW17 are turned on during the charge sharing operation and, being turned on after it, remain on for the horizontal period [e.g., Kawagoshi, Paragraph 52: when the amplitude at the time of dot inversion is equal to or less than the predetermined value; Paragraph 53: during the charge sharing operation, the charge share switches SW12 and SW13 are turned off and the input switches SW16 and SW17 are turned on; Paragraph 40: in response to the falling edge of the strobe signal STB, the charge share switches SW11, SW12, and SW13 are turned off, and at the same time, the output switches SW14 and SW15 and the input switches SW16 and SW17 are turned on] —
the first mode, in which the input switch is continuously turned on during the horizontal time; the function is turned on and off depending on the magnitude of the grayscale voltage [e.g., Kawagoshi, Paragraph 55: is turned on and off depending on the magnitude of the grayscale voltage, thereby enabling switching between the priority to countermeasures against power supply noise and the EMI and the priority to the driving performance].
Tsuchi ’138, Umeda, Kong and Kawagoshi are analogous art, each being a data-line (signal-line) driving circuit for a display panel with an amplifier fed from a DA converter through an input switch or driving the data line through an output switch.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to operate the input switch SW41 of Tsuchi ’138 in the two modes Kawagoshi teaches —
continuously on when the grayscale amplitude is small, and turned off for part of the horizontal period otherwise, the part being Tsuchi ’138’s own input cutoff period at the start of the output period —
because Kawagoshi gives the reason: when the amplitude is low at the time of dot inversion the GND current is small [e.g., Kawagoshi, Paragraph 54: when the amplitude is low at the time of dot inversion, the amount of the GND current is small], so the cutoff of the input switch is spent only when the disturbance warrants it and the driving performance is favored otherwise, and
Tsuchi ’138 itself already makes the per-period cutoff of its output switches conditional on the influence of the transition noise being other than small [e.g., Tsuchi ’138, Paragraph 194: in the case where an influence of the transition noise of the DAC selection signal is small];
applying the same choice to the input switch yields the predictable result of a driver that spends the input cutoff only when the disturbance at the switching of the output period warrants it —
the choice between the noise countermeasure and the driving performance that Kawagoshi states [e.g., Kawagoshi, Paragraph 55: is turned on and off depending on the magnitude of the grayscale voltage, thereby enabling switching between the priority to countermeasures against power supply noise and the EMI and the priority to the driving performance] and
that the applicant’s own first mode makes, keeping the input switch on for the whole horizontal time [e.g., Instant Specification Paragraph 77: In this first mode, the input switch of the buffer circuit 230 may also be kept on continuously for the horizontal time].
In the first mode the voltage monitor’s signal holds the input switch SW41 on across the switching of the output period and, as Tsuchi ’138’s own option where the influence of the transition noise is small, switch circuits 3, 5 and 6 are likewise not turned off at that switching within one polarity [e.g., Tsuchi ’138, Paragraph 194: in the case where an influence of the transition noise of the DAC selection signal is small, the switch circuit 3 (SW31 to SW34) in the column inversion drive can be controlled so as not to temporarily turn off every switching of one output period when a value of the polarity inverting signal POL is not changed; Paragraph 194: The same is applied to the switch circuit 5 (SW51 to SW58) and the switch circuit 6 (SW61 to SW64)],
so that the amplifier drives the data line without the interruption — the driving-performance priority; the control circuits 160A and 170A, whose switches are controlled by the signals S1 to S4 [e.g., Tsuchi ’138, Paragraph 182: Control signals S1 and S2 for controlling the on/off operation of the switches SW41 and SW42, respectively, are input to the gates of the NMOS transistors 172A and 172B, respectively; Paragraph 183: in the control circuits 160A and 170A, the controls signals S1 to S4 for controlling the on/off operation of the switch circuit 4 (SW41 to SW44) can be used as they are], continue their reset operation,
whose current Tsuchi ’138 states does not interfere with the operation of the output circuit [e.g., Tsuchi ’138, Paragraph 138: A current to be supplied by the control circuit 160 does not interfere with the operation of the output circuit 100A, but assists the output circuit 100A to switch from the charging operation of the load to the discharging operation with a change in the input signal VI];
the sharing of S1 to S4 by switch circuits 5 and 6 is an example [e.g., Tsuchi ’138, Paragraph 184: FIG. 9 illustrates an example in which the control signals of the switch circuit 5 (SW51 to SW58) and the switch circuit 6 (SW61 to SW64) share the control signals S1 to S4 of the switch circuit 4 (SW41 to SW44)].
In the second mode the timing of FIG. 9 operates unchanged. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007); Graham v. John Deere Co., 383 U.S. 1 (1966).
Regarding claim 10, the claim recites the buffer circuit further includes an output connection switch [e.g., Kawagoshi, Paragraph 33: The charge share switch SW12 is connected between a node between the output switch SW14 and the odd-numbered output terminal SKOUT11 and a node between the input switch SW16 and the non-inverting input terminal of the odd-numbered amplifier AMP11; Paragraph 27: includes an odd-numbered amplifier AMP11, an even-numbered amplifier AMP12, charge share switches SW11, SW12, and SW13, output switches SW14 and SW15, and input switches SW16 and SW17; Fig. 1: SW12, SW14, SW16, AMP11, SKOUT11]
that operates on/off in a manner opposite to the on/off of the input switch [e.g., Kawagoshi, Paragraph 38: During the charge sharing operation, the charge share switch SW11 is turned on and the charge share switches SW12 and SW13 are also turned on. At the same time, the output switches SW14 and SW15 and the input switches SW16 and SW17 are turned off; Paragraph 40: in response to the falling edge of the strobe signal STB, the charge share switches SW11, SW12, and SW13 are turned off, and at the same time, the output switches SW14 and SW15 and the input switches SW16 and SW17 are turned on],
wherein the output connection switch is configured to maintain the input/output of the buffer circuit at the voltage of the data line during the time when the input switch is turned off [e.g., Kawagoshi, Paragraph 38: allows the electric charge of the loads F11 and F12 to be fed back to the non-inverting input terminals; Paragraph 39: become substantially equal to each other; Fig. 1: AMP11 (inverting input coupled to the output node SK11)].
The combination as applied to claim 9, in which Kawagoshi is applied for its two modes only, does not expressly disclose the buffer circuit further including an output connection switch that operates on/off in a manner opposite to the on/off of the input switch and maintains the input/output of the buffer circuit at the voltage of the data line while the input switch is off:
Tsuchi ’138’s switches 162A, 162B, 172A and 172B, which are on while switch circuit 4 is off, preset the gate nodes of the output stages [e.g., Tsuchi ’138, Paragraph 190: In the input cutoff period (period t0 to t0a) when the polarity inverting signal (POL) is low and high, both of the switches 172A and 172B are on according to the control signals S1 and S2, and both of the switches 162A and 162B are on according to the control signals S3 and S4; Paragraph 191: the PMOS transistor 161 of the control circuit 160 is activated (turned on) as the diode coupling mode, and the falling of the output signal at the time of switching the output period of the output terminal 11 of the positive dedicated output stage 13 from the charging operation to the discharging operation is prevented from being delayed] and connect the amplifier to no data line;
in the alternative branch Umeda does not expressly disclose such a switch;
Kong does not expressly disclose it, as stated in the Office action mailed 28 July 2026.
Kawagoshi further discloses that its charge share switch SW12 is connected between the node between the input switch SW16 and the non-inverting input terminal of the amplifier AMP11 and the node between the output switch SW14 and the output terminal SKOUT11 — an output connection switch of the buffer circuit (Claim Interpretation, item (f));
it is turned on during the charge sharing operation, when the output switches and the input switches are turned off, and turned off at the end of that operation, when they are turned on — opposite to the input switch; and while it is on, the charge of the loads is fed back to the non-inverting input terminal, so that the amplifier, whose inverting input is coupled to its output node, follows it and the potentials at its output node and the output terminal become substantially equal to each other, the amplifier output voltage and the load voltage being set equal to each other during the charge sharing operation [e.g., Kawagoshi, Paragraph 63: the amplifier output voltages and the load voltage can be set equal to each other during the charge sharing operation] — the input and the output of the buffer circuit maintained at the voltage of the data line during the time when the input switch is turned off.
In the combination, SW12 is added between the input terminal 12 of Tsuchi ’138’s differential stage 14 and the odd terminal 31, turned on while SW41 and SW31 are off in the input cutoff period and off otherwise; and,
as in Kawagoshi’s amplifier AMP11, the amplifier is kept operating as a follower during that period: the switch circuit 5, which couples the differential stage to the output stage [e.g., Tsuchi ’138, Paragraph 20: The switches SW51 and SW53 control the respective couplings between the input stage output terminals 51, 52 of the differential stage 14 and output stage input terminals 61, 62 of the positive dedicated output stage 13], and
the switch circuit 6, which couples the output terminal back to the inverting input of the differential stage [e.g., Tsuchi ’138, Paragraph 22: controls the respective couplings between input terminals (-) of the differential stages 14 and 24 that function as inverting input terminals when functioning as a feedback amplifier circuit, and the output terminals 11 and 21; Paragraph 36: controls the coupling between the output terminal 11 and the differential stage 14], are held in their driving-state couplings during the cutoff period, so that the amplifier follows the data-line voltage presented at its input.
Tsuchi ’138 itself shows the amplifier operable with those couplings held across the switching of an output period: where the influence of the transition noise of the DAC selection signal is small, its switch circuit 3 in the column inversion drive, and likewise its switch circuits 5 and 6, need not be turned off at every switching of an output period within one polarity [e.g., Tsuchi ’138, Paragraph 194: in the case where an influence of the transition noise of the DAC selection signal is small, the switch circuit 3 (SW31 to SW34) in the column inversion drive can be controlled so as not to temporarily turn off every switching of one output period when a value of the polarity inverting signal POL is not changed; Paragraph 194: The same is applied to the switch circuit 5 (SW51 to SW58) and the switch circuit 6 (SW61 to SW64)];
the reason to hold them coupled during the cutoff is Kawagoshi’s, stated below.
Within one polarity the voltage held on the isolated data line lies in the range of the output stage coupled to it — the positive dedicated output stage 13 operating between VML and VDD and the negative dedicated output stage 23 between VSS and VMH [e.g., Tsuchi ’138, Paragraph 21: The positive dedicated output stage 13 operates in a voltage range (second voltage range) between a supply voltage VML and the positive supply voltage VDD, and the negative dedicated output stage 23 operates in a voltage range (third voltage range) between the negative supply voltage VSS and the supply voltage VMH] —
and Tsuchi ’138 also contemplates operation under the condition VML=VSS, in dot inversion drive [e.g., Tsuchi ’138, Paragraph 139: the configuration can be applied to the output circuit that conducts the gradation voltage output operation under the condition of VML=VSS; Paragraph 199: the dot inversion drive with the supply terminal voltage VML=VSS].
The line being isolated by SW31 during the period, the voltage SW12 presents to the input is the line’s held voltage, which the follower tracks throughout; Kawagoshi’s charge share switch SW11 between the two loads is not imported.
The control circuits 160A and 170A are retained, their reset operation returning the output-stage gate nodes to the vicinity of their stable-state voltage [e.g., Tsuchi ’138, Paragraph 123: the control circuit 160 conducts the operation (reset operation) of returning the gate voltage of the PMOS transistor 121 to the vicinity of the voltage in the state where the output is stable],
a current that Tsuchi ’138 states does not interfere with the operation of the output circuit [e.g., Tsuchi ’138, Paragraph 138: A current to be supplied by the control circuit 160 does not interfere with the operation of the output circuit 100A, but assists the output circuit 100A to switch from the charging operation of the load to the discharging operation with a change in the input signal VI].
This is a modification of the timing of switch circuits 5 and 6 during the cutoff period of Tsuchi ’138’s FIG. 9, which opens them there.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make it, because Kawagoshi teaches the result: a peak circuit current (GND current) flowing immediately after the charge sharing operation can be reduced [e.g., Kawagoshi, Paragraph 43: a peak circuit current (GND current) flowing immediately after the charge sharing operation can be reduced] when the amplifier’s input and output are held at the line voltage while the input is cut off, so that the amplifier does not slew from an undefined input at reconnection;
the timing of switch circuits 5 and 6 is set by Tsuchi ’138’s switch control signal generator circuit 807 [e.g., Tsuchi ’138, Paragraph 217: The switch control signal generator circuit 807 generates a signal for controlling the on/off operation of the switch 162, 172, 164, 174, the switches SW31, SW33, SW41, SW43, SW51, SW53, SW57, SW55, SW61, SW63, and the switches SW32, SW34, SW42, SW44, SW52, SW54, SW56, SW58, SW62, SW64], whose adaptation to hold the coupling closed during the cutoff period is within the ordinary skill, with predictable results.
KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007); Graham v. John Deere Co., 383 U.S. 1 (1966).
Claim 10 is additionally rejected under 35 U.S.C. § 103 as being unpatentable over Tsuchi ’138 in view of Kong and Kawagoshi as applied to claim 9 above, and further in view of Applicant’s admission on the record (election filed 19 February 2026, page 7);
or, in the alternative, under 35 U.S.C. § 103 as being unpatentable over Tsuchi ’138 in view of Umeda, Kong and Kawagoshi as applied to claim 9 above, and further in view of Applicant’s admission on the record (election filed 19 February 2026, page 7).
Regarding claim 10, the combination as applied to claim 9 does not expressly disclose the buffer circuit further including an output connection switch that operates on/off in a manner opposite to the on/off of the input switch and maintains the input/output of the buffer circuit at the voltage of the data line while the input switch is off, for the reasons stated in the preceding ground, in either of its branches.
The buffer circuit of the combination — an amplifier operated as a follower, with an input switch and no output connection switch — has the architecture of the applicant’s FIG. 5 buffer circuit (Species 1); the output connection switch recited in claim 10 is the output connection switch 730 of the applicant’s FIG. 7 buffer circuit (Species 2), the elected species.
The requirement for election of species mailed 23 December 2025 stated, in the words of the Manual, that where the applicant clearly admits on the record that the species are obvious variants, the admission may be used in a rejection under 35 U.S.C. 103 of the other species [e.g., MPEP 1893.03(d) (FP 18.22): Applicant may submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. Where such evidence or admission is provided by applicant, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103];
MPEP 803 provides that where there is an express admission that the claimed inventions would have been obvious over each other, restriction should not be required [e.g., MPEP 803, subsection II: If there is an express admission that the claimed inventions would have been obvious over each other within the meaning of 35 U.S.C. 103 , restriction should not be required].
In the reply filed 19 February 2026 the applicant admitted, at page 7, that the FIG. 5 and FIG. 7 buffer circuits are obvious variations of a common buffer architecture [e.g., Election of 19 February 2026, page 7: the embodiments represent obvious variations of a common buffer architecture and do not constitute independent and distinct inventions], and
the species requirement was withdrawn on that admission in the Office action mailed 11 March 2026. The applicant’s specification states the purpose of the variation [e.g., Instant Specification Paragraph 101: in the first example, the input of the amplifier may become unknown while the input switch is turned off. To prevent this state, the buffer circuit may further include an output connection switch].
Therefore, the buffer circuit with the output connection switch being, on the applicant’s own admission, an obvious variation of the buffer circuit without it, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the buffer circuit of the combination as applied to claim 9 with the output connection switch of the applicant’s FIG. 7 buffer circuit, operating opposite to the input switch so that the input of the amplifier does not become unknown while the input switch is turned off, with the predictable result the applicant describes [e.g., Instant Specification Paragraph 109: the other input terminal of the amplifier 510 may be maintained at the same voltage as the voltage formed on the data line without floating; Instant Specification Paragraph 115: the buffer circuit side terminal of the output switch may maintain a stable state without floating].
The variation the applicant admits is made to a buffer circuit whose amplifier follows its input; providing the buffer circuit of the combination with the output connection switch therefore carries with it the operation of its amplifier as a follower during the cutoff period stated in the preceding ground, the switch circuits 5 and 6 being held in their driving-state couplings, with which Tsuchi ’138 shows its amplifier operable across the switching of an output period [e.g., Tsuchi ’138, Paragraph 194: The same is applied to the switch circuit 5 (SW51 to SW58) and the switch circuit 6 (SW61 to SW64)], under the operating conditions stated there.
The applicant’s characterization of the admission in the remarks filed 23 September 2026 (page 11) as an allegedly Admitted Prior Art misdescribes the ground: the admission is not applied as prior art, but as the applicant’s own statement, made in response to the requirement’s invitation, that the two species are obvious variations of one another, which the Manual provides may be used in a rejection under 35 U.S.C. 103 of the other species. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007); Graham v. John Deere Co., 383 U.S. 1 (1966).
Response to Arguments
Applicant’s arguments, see page 8, filed 23 September 2026, with respect to the objection to claims 9 and 10 for the lack of antecedent basis of the horizontal time in claim 9 have been fully considered and are persuasive. The objection of claims 9 and 10 stated in the Office action mailed 28 July 2026 has been withdrawn.
The objection to claim 9 set forth above, directed to the markup of its dependency in the listing filed 23 September 2026, is new.
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The arguments (remarks, sections III–V, pages 9–11) are that Kong does not disclose blocking the propagation of noise during the first time period, does not address the technical problem, and is not cured by Hsueh or Kawagoshi, neither of which teaches turning off an input switch to block the noise generated in the digital-to-analog converting circuit or the coordinated operation of the input switch and the output switch during the first time period.
The rejections of claims 1, 3–5, 8 and 9 under 35 U.S.C. § 102(a)(1) over Kong and of claims 6, 7 and 10 under 35 U.S.C. § 103 over Kong in view of Hsueh, and of claim 10 over Kong in view of Kawagoshi and over Kong in view of the applicant’s admission, stated in the Office action mailed 28 July 2026, are not maintained on the amended claims:
Kong is not applied against claim 1, and neither Hsueh nor Kawagoshi is relied on for the input switch, its cutoff, the noise it blocks or the output switch’s operation during the first time period, each of which Tsuchi ’138 supplies as set out in the rejection of claim 1.
The Office action mailed 28 July 2026 quoted Paragraph 92 of Kong as reading m synchronization; the paragraph reads in synchronization with the synchronization signal Hsync, as quoted in the rejection of claim 3 above.
Applicant’s arguments filed 23 September 2026 have been fully considered but they are not persuasive.
The remarks (section VI, page 11) state that claims 3–5 recite the operation of the timing control circuit, the latch output signal, the output enable signal and the synchronized operation of the input and output switches, that claims 6–8 recite the gamma-voltage selection circuit, the shared ground and the release of the parasitic capacitance of the data line, and that claims 9 and 10 recite the operating modes and the output connection switch, and that these features further distinguish the claims from Kong, Hsueh and Kawagoshi; they do not state how the language of any dependent claim distinguishes over those references (37 CFR 1.111(b)).
As set out above: the timing control circuit that generates the latch output signal at each horizontal time and the output enable signal is supplied by Kong’s timing controller 200 with its control logic 210 in the combination stated for claims 3 and 4,
in which Tsuchi ’138 and Umeda supply the latch, the per-line timing and the waveforms of the two switches, and
the synchronized operation of the switches of claim 5 is Tsuchi ’138’s own;
the switch structure of the decoder recited in claim 6 is supplied by Hsueh’s transistor-column decoder and the gamma property of the reference voltages from which the decoder selects by the FPD33584 datasheet, a reference not applied in the prior action;
the shared ground of claim 7 and the parasitic capacitance of claim 8 are met by the FPD33584 datasheet and by Tsuchi ’138, neither applied in the prior action; and
the first mode of claim 9 (the input switch continuously on), the second mode being Tsuchi ’138’s own cutoff, and the output connection switch of claim 10 are supplied by Kawagoshi’s second embodiment — the voltage monitor circuit CIR31 that keeps the input switches on or turns them off during the charge sharing operation according to the grayscale amplitude, and the charge share switch SW12 that feeds the load voltage back to the amplifier’s non-inverting input while the input switch is off.
The remarks describe Kawagoshi as teaching charge-sharing feedback between amplifier nodes (page 10); that feedback switch, connected between the amplifier’s non-inverting input node and the output terminal on the load side of the output switch, is the output connection switch of claim 10, for the reasons stated in the rejections of claims 9 and 10.
Election/Restrictions
Claims 11–20 remain withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Applicant timely traversed the restriction (election) requirement in the reply filed on 19 February 2026.
Conclusion
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/Jeff Piziali/
Primary Examiner, Art Unit 2628
25 September 2026
