DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (WO 2022/118141 A1 – see USPN 2023/0411738A1 for English translation citations below) in view of Yamazaki et al. (JP 2018-055097 A).
As to claim 1, Yamazaki (WO) teaches an electronic device comprising:
a semiconductor device (see at least [0430] “an integrated circuit with a display portion (hereinafter, also referred to as a display IC) and electronic devices each of which includes a display device”; [0431] “FIG. 40A is a perspective view of a display IC 100 including the display device 10”; [0448] “FIG. 42A is a perspective view showing a portable information terminal 9101.” – note display IC is semiconductor device);
wherein the semiconductor device comprises a logic circuit portion provided in a plurality of element layers a display control portion, and a display portion (see at least driver circuit 40, display portion 60 and [0433] “FIG. 40B is a perspective view schematically illustrating the structures of the layer 20, the layer 30, and the light-emitting element 70 … the layer 30 in which the OS transistors are provided includes the backup circuit 82…”);
wherein the display portion comprises a plurality of display regions (see at least [0353] “The light-emitting elements 70R, the light-emitting elements 70G, and the light-emitting elements 70B are arranged in a matrix”; [0433] “pixel circuits 62R, 62G, and 62B in the region of the pixel 61.”);
wherein the display control portion comprises a plurality of driver circuit portions (see at least driver circuit 40);
wherein the plurality of display regions each comprise a pixel circuit that controls light emission of a light-emitting device (see at least [0356] “The light-emitting element 70R, the light-emitting element 70G, and the light-emitting element 70B are provided over a substrate 251 and each include the conductor 772 functioning as a pixel electrode ..”; [0433] “pixel circuits 62R, 62G, and 62B…”).
wherein the plurality of driver circuit portions each comprise a driver circuit that controls the pixel circuit (see at least driver circuit 40);
wherein the plurality of display regions are each provided at a position overlapping with a region where any one of the plurality of driver circuit portions is provided (see at least [0433] …layer 30… includes the backup circuit 82 in addition to the pixel circuits…” – note the logic, pixel, and control circuits are integrated within stacked semiconductor layers of the same display IC);
wherein the logic circuit portion comprises an arithmetic device (see at least [0434] “the functional circuit 50 or the CPU 51…” – note a CPU is an arithmetic device.
Yamazaki (WO) does not directly teach wherein the arithmetic device is configured to control, in accordance with whether or not image data is updated in each of the plurality of display regions, an operation state or a stop state of the driver circuit corresponding to the pixel circuit included in the display region.
Yamazaki (JP) teaches wherein the arithmetic device is configured to control, in accordance with whether or not image data is updated in each of the plurality of display regions (see at least [0033] “the above information is information displayed on each display unit having pixels. That is, it corresponds to image data input to each display unit. Further, updating information is to update information displayed on each display unit having pixels. That is, this corresponds to rewriting (refreshing) the image data input to each display unit.”; [0061] “it is possible to make the region unnecessary for updating information. On the other hand, the area … can be an area requiring updating of information …”; [0065] “the still image display units 47 and 51 … can be regions in which updating of information is unnecessary. …”),
an operation state or a stop state of the driver circuit corresponding to the pixel circuit included in the display region (see at least [0026] “setting the pulse signal output as the scanning signal to the L level signal is also referred to as stopping the output of the scanning signal.”; [0027] “setting the pulse signal output as the scanning signal output to an arbitrary row as the L level signal may stop the output of the scanning signal to the pixels of an arbitrary row …”; [0028] “The gate driver 20 is a circuit for giving a scanning signal … to the liquid crystal element LC of the pixel in the selected row. The gate driver 22 is a circuit for giving a scanning signal … to the light emitting element EL of the pixel in the selected row.”; [0038] “A scanning signal … is applied from the gate driver 20 …”; [0039] “A scanning signal … is applied from the gate driver 22 …”; [0068] “the video voltage written in the light emitting element EL is updated in the region where information needs to be updated so as to output a scanning signal. … so as not to output the scanning signal …”; [0070] “the gate driver 20 to stop the output of the scanning signal at regular intervals.”).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to apply Yamazaki (JP)’s region-based selective driving to Yamazaki (WO)’s multi-layer display IC in order to reduce power consumption in Yamazaki’s (WO)’s portable electronic devices (e.g., “[0448] portable information terminal”). Yamazaki (WO) emphasizes power reduction (see at least [0440] “power consumption… can be reduced…”. Yamazaki (JP) teaches a specific power-saving mechanism: different refresh rates per display region and temporary stopping of drive circuit. The modification requires only implementing refresh control logic in CPU 51 (already disclosed by Yamazaki (WO)) and does not change Yamazaki’s pixel structure and driver circuit structure. It only changes the control scheme. The combination is a predictable use of prior art elements according to their established functions (power-saving through selective refresh).
As to claim 2, the combination of Yamazaki (WO) and Yamazaki (JP) teach the electronic device according to claim 1 (see above rejection), further comprising:
a first element layer, a second element layer, and a third element layer (see at least Yamazaki (WO) [0433] “FIG. 40B is a perspective view schematically illustrating the structures of the layer 20, the layer 30, and the light-emitting element 70…”),
wherein the first element layer comprises a first transistor comprising a semiconductor layer comprising silicon in a channel formation region (see at least Yamazaki (WO) [0434] “the functional circuit 50 or the CPU 51…”),
wherein the second element layer comprises a second transistor comprising a semiconductor layer comprising a metal oxide in a channel formation region (see at least Yamazaki (WO) [0433] “the layer 30 in which the OS transistors are provided…”), and
wherein the third element layer comprises the light-emitting device (see at least Yamazaki (WO) [0433] “the light-emitting element 70…”).
As to claim 3, the combination of Yamazaki (WO) and Yamazaki (JP) teach the electronic device according to claim 2 (see above rejection), wherein the arithmetic device comprises a scan flip-flop and a backup circuit electrically connected to the scan flip-flop, wherein the scan flip-flop and the driver circuit portion are provided in the first element layer, and wherein the backup circuit and the pixel circuit are provided in the second element layer (see Yamazaki (WO) at least driver circuit 40 and [0433] “the layer 30 in which the OS transistors are provided includes the backup circuit 82 in addition to the pixel circuits…” – Note scan flip-flops are conventional components of driver circuits (shift registers driving scanning lines) – a scan flip-flop is inherently included in a scan driver.
As to claim 4, the combination of Yamazaki (WO) and Yamazaki (JP) teach the electronic device according to claim 3 (see above rejection), wherein the backup circuit, in a non-operation state of the arithmetic device, is configured to retain data retained in the scan flip-flop in a state where supply of power supply voltage is stopped (see Yamazaki (WO) at least [0433] “the layer 30 in which the OS transistors are provided includes the backup circuit 82 in addition to the pixel circuits”; [0440] “power consumption… can be reduced…” – note oxide semiconductor transistors are known for extremely low off-current and charge retention capability. The purpose of the backup circuit in Yamazaki (WO)’s OS layer is to retain state information when portions of circuitry are inactive. Given Yamazaki (WO)’s disclosure of power reduction and backup circuitry in the OS layer, retention in a non-operation state is necessarily implied).
As to claim 5, the combination of Yamazaki (WO) and Yamazaki (JP) teach the electronic device according to claim 2 (see above rejection), wherein the metal oxide comprises In, Ga, and Zn (see Yamazaki (WO) at least [0072] “a transistor including an oxide including at least one of indium, an element M (the element M is aluminum, gallium, yttrium, or tin), and zinc in a channel formation region is preferably used as the OS transistor.”; [0433] “OS transistors”).
As to claim 6, the combination of Yamazaki (WO) and Yamazaki (JP) teach the electronic device according to claim 1 (see above rejection),
wherein the image data is image data for displaying a second hand, an hour hand, and a minute hand (see Yamazaki (JP) at least [0060] “In the timepiece display section 50, configurations for showing time such as dial, long hand, short hand, and second hand are shown.”; [0074] “display the long hand, the short hand and the second hand 52.”),
wherein in the arithmetic device, the driver circuit corresponding to the pixel circuit included in the display region displaying the second hand, the hour hand, and the minute hand is in an operation state (see Yamazaki (JP) at least [0061] “the area where the pixel for displaying the clock display unit 50 is connected to the gate line can be an area requiring updating of information…”; [0068] “the video voltage written in the light emitting element EL is updated in the region where information needs to be updated so as to output a scanning signal.”), and
wherein the driver circuit corresponding to the pixel circuit included in the display region not displaying the second hand, the hour hand, and the minute hand is in a stop state (see Yamazaki (JP) at least [0027] “the scanning signal output to an arbitrary row … can be set to the L level…”; [0061] “it is possible to make the region unnecessary for updating information. …setting the pulse signal output as the scanning signal output to an arbitrary row as the L level signal may stop the output of the scanning signal to the pixels of an arbitrary row…”; [0068] “…so as not to output the scanning signal from the gate line GLEL [m-1] … [and] GLEL [m].”;[0122] “…it is possible to stop the output of the scanning signal for a predetermined row…” – note for rows/regions not requiring information update, the gate driver stops outputting scanning signals. Stopping the output of the scanning signal to those pixel circuits corresponds to the claimed “stop state” of the driver circuit for the display region not displaying the second, hour, and minute hands).
Conclusion
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/JENNIFER L ZUBAJLO/ Examiner, Art Unit 2627 2/13/2026