Prosecution Insights
Last updated: October 24, 2026
Application No. 19/139,012

PHASE ADJUSTMENT CIRCUIT

Non-Final OA §103
Filed
Jun 13, 2025
Priority
Dec 15, 2022 — nonprovisional of PCTJP2022046188
Examiner
CHEN, PATRICK C
Art Unit
2836
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Nippon Telegraph and Telephone Corporation
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
12m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
480 granted / 582 resolved
+14.5% vs TC avg
Moderate +10% lift
Without
With
+9.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
31 currently pending
Career history
621
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
44.7%
+4.7% vs TC avg
§102
29.8%
-10.2% vs TC avg
§112
20.6%
-19.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 582 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. In addressing the rejection ground, each claim may not have been separately discussed to the extent the claimed features are the same as or similar to the previously-discussed features; the previous discussion is construed to apply for the other claims in the same or similar way. In the office action, “/” should be read as and/or as generally understood. For example, “A/B” means A and B, or A or B. Claim Objections Claims 9-16 are objected to because of the following informalities: Claim 9 recites the clock signal in line 4. It should be recited as --the sine wave shaped clock signal--. Claims 10-16 are objected to based on the dependency from claim 9. Appropriate correction is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 9 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2022/0345093). Regarding claim 9, Yang discloses a phase adjustment circuit [e.g. fig. 5A] comprising: a clock generation circuit [e.g. the circuit that generates the input signal to 420] configured to generate a sine wave shaped clock signal [e.g. RF signal; clock signal is intentional used, the claim does not recite what the clock signal is for]; an amplifier circuit [e.g. 420] configured to amplify the clock signal output from the clock generation circuit; a transmission line including an input end [e.g. the line between 420 and the node above 442] connected to an output terminal of the amplifier circuit; a load circuit [e.g. 442] connected to a termination of the transmission line and having adjustable impedance; and an output circuit [e.g. 443/444] configured to receive a signal obtained by adding an output signal of the amplifier circuit and a return signal [the return signal from 442] from the transmission line at the output terminal of the amplifier circuit and output an output signal [e.g. the output signal of 443/440]. Yang does not explicitly disclose the RF signal is a sine wave signal. However, it’ swell-known to utilize a sine wave signal as an RF signal. The official notice of the foregoing fact is hereby taken. For example, Hanson discloses an RF signal is a sine wave signal [paras. 0056, 0072]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Yang to provide a well-known sine wave as the RF signal. Regarding claim 11, the combination discussed above discloses the phase adjustment circuit according to claim 9, wherein the load circuit includes a variable capacitor having adjustable impedance. Claims 10 and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2022/0345093) in view of Ma et al. (US 2020/0092957). Regarding claim 10, the combination discussed above discloses the phase adjustment circuit according to claim 9, except wherein the load circuit includes a variable resistor having adjustable impedance. However, this is a matter of design choice to adjust the impedance. It’s well-known that adjustable impedance can have variable capacitors, variable resistors, variable inductors and/or combinations thereof. For example, Ma discloses adjustable impedance can have variable capacitors, variable resistors, variable inductors and/or combinations thereof [paras. 0191, 0146, 0076, 0055]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Yang in accordance with the teaching of Ma regarding variable impedance in order to utilize a well-known variable resistor to achieve a certain feature. Regarding claim 12, the combination discussed above discloses the phase adjustment circuit according to claim 9, except wherein the load circuit includes a variable inductor having adjustable impedance. However, this is a matter of design choice to adjust the impedance. It’s well-known that adjustable impedance can have variable capacitors, variable resistors, variable inductors and/or combinations thereof. For example, Ma discloses adjustable impedance can have variable capacitors, variable resistors, variable inductors and/or combinations thereof [paras. 0191, 0146, 0076, 0055]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Yang in accordance with the teaching of Ma regarding variable impedance in order to utilize a well-known variable inductor to achieve a certain feature. Regarding claim 13, the combination discussed above discloses the phase adjustment circuit according to claim 9, except wherein the load circuit includes a combination of at least two of a variable resistor, a variable capacitor, and a variable inductor, respective impedance being adjustable. However, this is a matter of design choice to adjust the impedance. It’s well-known that adjustable impedance can have variable capacitors, variable resistors, variable inductors and/or combinations thereof. For example, Ma discloses adjustable impedance can have variable capacitors, variable resistors, variable inductors and/or combinations thereof [paras. 0191, 0146, 0076, 0055]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Yang in accordance with the teaching of Ma regarding variable impedance in order to utilize a well-known combination of at least two of a variable resistor, a variable capacitor, and a variable inductor to achieve a certain feature. Allowable Subject Matter Claims 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICK C CHEN whose telephone number is (571)270-7207. The examiner can normally be reached M-F Flexible 8:00-16:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICK C CHEN/Primary Examiner, Art Unit 2836
Read full office action

Prosecution Timeline

Jun 13, 2025
Application Filed
Aug 26, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
92%
With Interview (+9.9%)
2y 4m (~12m remaining)
Median Time to Grant
Low
PTA Risk
Based on 582 resolved cases by this examiner. Grant probability derived from career allowance rate.

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