DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Preliminary Amendment
Applicant’s preliminary amendment filed on July 8, 2025 has been entered. Claims 11 and 13-15 have been amended. Claims 1-15 are pending in this application.
Drawings
The drawings are objected to because Fig. 6 does not show “the subsequent emission control signal EM (i+X)” as described in specification. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1 and 14 are objected to because of the following informalities:
Regarding claims 1 and 14, the limitations “one of the power supply voltages” should be amended to read ---one of power supply voltages---.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
6. Claim(s) 1 and 14 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by IN et al. (US 2021/0134210).
Regarding claim 1, IN discloses a display device (Fig. 1; [0055], e.g., device 1000) comprising:
a display portion including a plurality of pixel circuits (e.g., display potion 100 comprises a plurality of PX);
a drive circuit configured to drive the plurality of pixel circuits (e.g., scan drivers 200, 300, and 400, an emission driver 500, a data driver 600); and
a display control circuit (e.g., timing controller 700) configured to control the drive circuit such that a drive period and a pause period alternately appear (Figs 3-4; [0072]-[0073], [0079]-[0081], [0144]-[0147], e.g., a drive period P1 and a pause period P2 alternately appear),
the drive period consisting of one or more refresh frame periods in which voltage of a plurality of data signals is written, as data voltage, to the plurality of pixel circuits ([0072]-[0073], e.g., the drive period P1 consist at least one refresh frame period in which a data signal corresponding to an image is written to the pixels PX), the pause period consisting of one or more non- refresh frame periods in which writing of data voltage to the plurality of pixel circuits is stopped ([0079]-[0081], [0147]-[0148], e.g., the pause period P2 consists one or more non-refresh frame periods in which the writing of the data signal is stopped),
wherein each of the plurality of pixel circuits includes a display element configured to be driven by a current (Fig. 2; [0094]-[0095], e.g., the light emitting device LD generates light with a predetermined luminance corresponding to an amount of current supplied from the first transistor M1), a drive transistor arranged in series with the display element and including a control terminal, a first conduction terminal, and a second conduction terminal ([0097], e.g., the drive transistor M1 includes a gate electrode, a first electrode and a second electrode), a holding capacitor having one terminal connected to the control terminal of the drive transistor and thus being configured to hold a voltage of the control terminal of the drive transistor ([0094], the storage capacitor Cst is configured to store a voltage of the gate electrode of the drive transistor M1), a write control transistor, as a switching element, having a first conduction terminal configured to receive a data voltage to be written to the holding capacitor and a second conduction terminal connected to the first conduction terminal of the drive transistor ([0098], [0134], e.g., the write control transistor M2 having a first electrode configured to receive a data voltage to be written to the holding capacitor Cst and a second electrode connected to the first electrode of the drive transistor M1), a threshold compensation transistor, as a switching element, arranged between the second conduction terminal and the control terminal of the drive transistor, and configured to put the drive transistor in a diode-connected state when in ON state ([0099], e.g., the threshold compensation transistor M3 is configured to put the drive transistor M1 in a diode-connected state when in ON state), at least one emission control transistor, as a switching element, arranged in series with the display element and the drive transistor ([0103], e.g., at least one emission control transistor M5), and a bias application circuit configured to apply, to the first conduction terminal of the drive transistor, a bias voltage for reducing threshold voltage shift caused by a hysteresis characteristic of the drive transistor ([0102], [0126], e.g., the bias application circuit M4 is configured to apply a bias voltage for reducing threshold voltage shift),
wherein in each of the plurality of pixel circuits, the bias application circuit has a first terminal configured to receive one of signals provided to control terminals of transistors each of which is included in the each of the plurality of pixel circuits or in another pixel circuit, but none of which are included in the bias application circuit, or to receive one of the power supply voltages of the plurality of pixel circuits (Fig. 2; [0020], [0126], e.g., the bias application circuit M4 has a first terminal configured to receive a power supply voltage Vbs), and a second terminal connected to the first conductive terminal of the drive transistor (e.g., a second terminal connected to the first electrode of the drive transistor M1), and the bias application circuit is configured to apply the bias voltage to the first conductive terminal of the drive transistor based on the signal or the voltage received at the first terminal ([0126], e.g., apply the bias voltage Vbs to the first electrode of the drive transistor based on the voltage received at the first terminal).
Regarding claim 14, IN discloses a method for driving a display device using a display element driven by a current (Figs 1-2; [0055], [0094]-[0095], e.g., the display device 1000 using the light emitting device LD driven by a current), wherein the display device comprises a display portion including a plurality of pixel circuits (e.g., display potion 100 comprises a plurality of PX), each of the plurality of pixel circuits including:
a display element driven by a current (Fig. 2; [0094]-[0095], e.g., the light emitting device LD generates light with a predetermined luminance corresponding to an amount of current supplied from the first transistor M1);
a drive transistor having a control terminal, a first conduction terminal, and a second conduction terminal, and arranged in series with the display element ([0097], e.g., the drive transistor M1 includes a gate electrode, a first electrode and a second electrode);
a holding capacitor having one terminal connected to the control terminal of the drive transistor and thus being configured to hold a voltage at the control terminal of the drive transistor ([0094], the storage capacitor Cst is configured to store a voltage of the gate electrode of the drive transistor M1);
a write control transistor, as a switching element, having a first conduction terminal configured to receive a data voltage to be written to the holding capacitor and a second conduction terminal connected to the first conduction terminal of the drive transistor ([0098], [0134], e.g., the write control transistor M2 having a first electrode configured to receive a data voltage to be written to the holding capacitor Cst and a second electrode connected to the first electrode of the drive transistor M1);
a threshold compensation transistor, as a switching element, arranged between the second conduction terminal and the control terminal of the drive transistor, and configured to put the drive transistor in a diode-connected state when in ON state ([0099], e.g., the threshold compensation transistor M3 is configured to put the drive transistor M1 in a diode-connected state when in ON state);
at least one emission control transistor, as a switching element, arranged in series with the display element and the drive transistor ([0103], e.g., at least one emission control transistor M5), and
a bias application circuit configured to apply, to the first conductive terminal of the drive transistor, a bias voltage for reducing threshold voltage shift caused by a hysteresis characteristic of the drive transistor ([0102], [0126], e.g., the bias application circuit M4 is configured to apply a bias voltage for reducing threshold voltage shift),
wherein in each of the plurality of pixel circuits, the bias application circuit having a first terminal configured to receive one of signals provided to control terminals of transistors each of which is included in the each of the plurality of pixel circuits or in another pixel circuit, but none of which are included in the bias application circuit, or to receive one of the power supply voltages of the plurality of pixel circuits (Fig. 2; [0020], [0126], e.g., the bias application circuit M4 has a first terminal configured to receive a power supply voltage Vbs), and having a second terminal connected to the first conductive terminal of the drive transistor (e.g., a second terminal connected to the first electrode of the drive transistor M1),
the method comprising performing a pause driving by driving the plurality of pixel circuits such that a drive period and a pause period alternately appear (Figs 3-4; [0072]-[0073], [0079]-[0081], [0144]-[0147], e.g., a drive period P1 and a pause period P2 alternately appear),
the drive period consisting of one or more refresh frame periods in which voltage of a plurality of data signals is written, as data voltage, to the plurality of pixel circuits ([0073], e.g., the drive period P1 consist one refresh frame period in which a data signal corresponding to an image is written to the pixels PX), the pause period consisting of one or more non-refresh frame periods in which writing of data voltage to the plurality of pixel circuits is stopped ([0079]-[0081], [0147]-[0148], e.g., the pause period P2 consists one or more non-refresh frame periods in which the writing of the data signal is stopped),
wherein the performing the pause driving includes performing a bias application by driving the plurality of pixel circuits such that the bias application circuit applies the bias voltage to the first conduction terminal of the drive transistor based on the signal or the voltage received at the first terminal within a period during which the emission control transistor in each of the plurality of pixel circuits is in OFF state in both the refresh frame period and the non-refresh frame period (Figs 2-4; [0126], e.g., apply the bias voltage Vbs to the first electrode of the drive transistor based on the voltage received at the first terminal).
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claim(s) 2, 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over IN et al. (US 2021/0134210) in view of Sano (WO 2022/157822, the examiner is using US 2024/0304144 as the English Translation of WO 2022/157822).
Regarding claim 2, IN further discloses the display device according to claim 1, wherein the display control circuit controls the drive circuit such that the emission control transistor turns on to cause the display element to emit light during the refresh frame period and to emit light during the non-refresh frame period (Figs 2-4; [0120], e.g., the emission control transistor M5 is turned on to cause the display element LD to emit light during the emission period EP of the refresh frame period P1 and the emission period EP of the non-refresh frame period P2), and such that the bias voltage is applied to the first conduction terminal of the drive transistor within a period during which the emission control transistor is in OFF state in each of the plurality of pixel circuits in both the refresh frame period and the non-refresh frame period (Figs 3-4; [0122], [0126], [0138], [0149], e.g., apply the bias voltage Vbs to the first electrode of the drive transistor M1 within a period during which the emission control transistor M5 is in OFF state in both the refresh frame period P1 and the non-refresh frame period P2); and
controls the drive circuit in the refresh frame period such that in each of the plurality of pixel circuits, the write control transistor and the threshold compensation transistor are each in ON state for a predetermined period within a period during which the emission control transistor is in OFF state (Fig. 3; e.g., in the refresh frame period P1, the write control transistor M2 and the threshold compensation transistor M3 are each in ON state for a predetermined period within a period during which the emission control transistor T5 is in OFF state), and such that in each of the plurality of pixel circuits, the bias application circuit applies the bias voltage to the first conduction terminal of the drive transistor based on the signal or voltage received at the first terminal during a bias period that is set to include at least a portion of a period from when the emission control transistor changes to OFF state until when the write control transistor changes to ON state (Fig. 3; [0126], e.g., the first bias period BP1 is set to include a portion of a period from when the emission control transistor changes to OFF state until when the write control transistor changes to ON state).
IN does not specifically disclose wherein the emission control transistor turns on and off to cause the display element to emit light with a predetermined light emission duty during the refresh frame period and to emit light with a predetermined light emission duty during the non-refresh frame period.
However, Sano discloses a display device (Fig. 1; [0084], e.g., display device 10) comprising:
a display portion including a plurality of pixel circuits ([0084]-[0085], e.g., display potion 11 comprises a plurality of pixel circuits 15);
a drive circuit configured to drive the plurality of pixel circuits (e.g., a data-side drive circuit 30, a scanning-side drive circuit 40); and
a display control circuit (e.g., display control circuit 20) configured to control the drive circuit such that a drive period and a pause period alternately appear (Fig 12; [0084], e.g., a drive period TD and a pause period TP alternately appear),
the drive period consisting of one or more refresh frame periods in which voltage of a plurality of data signals is written, as data voltage, to the plurality of pixel circuits ([0084], e.g., the drive period TD consists of one refresh frame period Trf in which a data signal corresponding to an image is written to the pixel circuits 15), the pause period consisting of one or more non- refresh frame periods in which writing of data voltage to the plurality of pixel circuits is stopped ([0084], e.g., the pause period TP consists of a plurality of non-refresh frame periods Tnrf for stopping the rewriting of the image data in the display portion),
wherein each of the plurality of pixel circuits includes a display element configured to be driven by a current (Fig. 3; [0111], e.g., the organic EL element OL is driven by current),
a drive transistor arranged in series with the display element and including a control terminal, a first conduction terminal, and a second conduction terminal ([0104], e.g., the drive transistor T4 includes a gate terminal, a first terminal, and a second terminal), and
at least one emission control transistor, as a switching element, arranged in series with the display element and the drive transistor ([0104], e.g., the first emission control transistor T5),
wherein the display control circuit controls the drive circuit such that the emission control transistor turns on and off to cause the display element to emit light with a predetermined light emission duty during the refresh frame period (Figs 3-4 and 12; [0098], e.g., the emission control transistorT5 turns on and off to cause the organic EL element OL to emit with a predetermined light emission duty during the refresh frame period Trf) and to emit light with a predetermined light emission duty during the non-refresh frame period (e.g., emit light with a predetermined light emission duty during the non-refresh frame period Tnrf).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Sato in the invention of IN for turning an emission control transistor on and off to cause a display element to emit light with a predetermined light emission duty during a refresh frame period and to emit light with a predetermined light emission duty during a non-refresh frame period in order to display a satisfactory image free from flickering across all areas of the image even when pause drive is performed (see [0060] of Sato).
Regarding claim 5, IN further discloses the display device according to claim 2, wherein the bias application circuit includes a bias application transistor, as a switching element, having first and second conductive terminals respectively connected to the first and second terminals of the bias application circuit (Fig. 2; [0126], e.g., the bias application transistor M4), the display control circuit is further configured to control the drive circuit such that the bias application transistor is in ON state during the bias period (Figs 3-4; e.g., the bias application transistor M4 is in ON state during the bias period BP1, BP2 and BP3), and each of the plurality of pixel circuits is configured such that either a signal having a voltage equivalent to the bias voltage during the bias period among signals provided to control terminals of transistors other than the bias application transistor in the each of the plurality of pixel circuit or in another pixel circuit, or a voltage equivalent to the bias voltage among the power supply voltages, is provided to the first terminal of the bias application circuit ([0126], e.g., the voltage Vbs is equivalent to the bias voltage is provided to the first terminal of the bias application transistor M4).
Regarding claim 15, IN further discloses the method according to claim 14, wherein the performing the pause driving further includes:
performing an emission control by turning on and off the emission control transistor such that the display element emits light during the refresh frame period and the display element emits light during the non-refresh frame period (Figs 2-4; [0120], e.g., the emission control transistor M5 is turned on to cause the display element LD to emit light during the emission period EP of the refresh frame period P1 and the emission period EP of the non-refresh frame period P2); and
performing a data writing by driving the plurality of pixel circuits such that the write control transistor and the threshold compensation transistor are each in ON state for a predetermined period within the period during which the emission control transistor is in OFF state in the refresh frame period (Fig. 3; e.g., in the refresh frame period P1, the write control transistor M2 and the threshold compensation transistor M3 are each in ON state for a predetermined period within a period during which the emission control transistor T5 is in OFF state); wherein
wherein in the performing the bias application, the plurality of pixel circuits is driven such that the bias application circuit applies the bias voltage to the first conduction terminal of the drive transistor based on the signal or the voltage received at the first terminal during a bias period that is set to include at least a portion of the period from when the emission control transistor changes to OFF state until when the write control transistor changes to ON state in each of the plurality of pixel circuits in the refresh frame period (Fig. 3; [0126], e.g., the first bias period BP1 is set to include a portion of a period from when the emission control transistor changes to OFF state until when the write control transistor changes to ON state).
IN does not specifically disclose wherein the emission control transistor turns on and off to cause the display element to emit light with a predetermined light emission duty during the refresh frame period and to emit light with a predetermined light emission duty during the non-refresh frame period.
However, Sano discloses a display device (Fig. 1; [0084], e.g., display device 10) comprising:
a display portion including a plurality of pixel circuits ([0084]-[0085], e.g., display potion 11 comprises a plurality of pixel circuits 15);
a drive circuit configured to drive the plurality of pixel circuits (e.g., a data-side drive circuit 30, a scanning-side drive circuit 40); and
a display control circuit (e.g., display control circuit 20) configured to control the drive circuit such that a drive period and a pause period alternately appear (Fig 12; [0084], e.g., a drive period TD and a pause period TP alternately appear),
the drive period consisting of one or more refresh frame periods in which voltage of a plurality of data signals is written, as data voltage, to the plurality of pixel circuits ([0084], e.g., the drive period TD consists of one refresh frame period Trf in which a data signal corresponding to an image is written to the pixel circuits 15), the pause period consisting of one or more non- refresh frame periods in which writing of data voltage to the plurality of pixel circuits is stopped ([0084], e.g., the pause period TP consists of a plurality of non-refresh frame periods Tnrf for stopping the rewriting of the image data in the display portion),
wherein each of the plurality of pixel circuits includes a display element configured to be driven by a current (Fig. 3; [0111], e.g., the organic EL element OL is driven by current),
a drive transistor arranged in series with the display element and including a control terminal, a first conduction terminal, and a second conduction terminal ([0104], e.g., the drive transistor T4 includes a gate terminal, a first terminal, and a second terminal), and
at least one emission control transistor, as a switching element, arranged in series with the display element and the drive transistor ([0104], e.g., the first emission control transistor T5),
wherein the display control circuit controls the drive circuit such that the emission control transistor turns on and off to cause the display element to emit light with a predetermined light emission duty during the refresh frame period (Figs 3-4 and 12; [0098], e.g., the emission control transistorT5 turns on and off to cause the organic EL element OL to emit with a predetermined light emission duty during the refresh frame period Trf) and to emit light with a predetermined light emission duty during the non-refresh frame period (e.g., emit light with a predetermined light emission duty during the non-refresh frame period Tnrf).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Sato in the invention of IN for turning an emission control transistor on and off to cause a display element to emit light with a predetermined light emission duty during a refresh frame period and to emit light with a predetermined light emission duty during a non-refresh frame period in order to display a satisfactory image free from flickering across all areas of the image even when pause drive is performed (see [0060] of Sato).
9. Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over IN et al. (US 2021/0134210) in view of Sano (WO 2022/157822, the examiner is using US 2024/0304144 as the English Translation of WO 2022/157822), and further in view of Kim et al. (US 2021/0027696).
Regarding claim 6, IN further discloses the display device according to claim 5, wherein the display portion further includes a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of emission control lines, a plurality of bias control lines, a first power supply line, and a second power supply line (Figs 1-2; [0060], e.g., data lines D, scan lines S1, emission control lines E, bias control lines S3, a first power supply VDD and a second power supply line VSS); the drive circuit includes:
a data-side drive circuit configured to generate and apply a plurality of data signals to the plurality of data signal lines ([0059]-[0061], e.g., the data driver 600 generates and applies a plurality of data signal to the data signal lines D); and
a scanning-side drive circuit configured to selectively drive the plurality of first scanning signal lines and selectively inactivates the plurality of emission control lines ([0056], [0059]-[0066], e.g., the scan driver and the emission driver selectively drive the plurality of first scanning signal lines S1 and selectively inactivates the plurality of emission control lines E);
each of the plurality of pixel circuits corresponds to one of the plurality of data signal lines, one of the plurality of first scanning signal lines, one of the plurality of emission control lines, and one of the plurality of bias control lines (Figs 1-2; e.g., each of the pixel circuits PX corresponding to one of data signal lines D, one of the plurality of first scanning signal lines S1, one of the plurality of emission control lines E, and one of the plurality of bias control lines S3);
the at least one emission control transistor includes first and second emission control transistors each having control terminals connected to a corresponding emission control line ([0103]-[0104], e.g., first and second emission control transistors M5 and M6 each having a control terminal connected to a corresponding emission control line E);
the write control transistor further has a control terminal connected to a corresponding first scanning signal line ([0098], e.g., the write control transistor M2 has a control terminal connected to a corresponding first scan signal line S1i);
the first conduction terminal of the drive transistor is connected to a corresponding data signal line via the write control transistor, and is connected to the first power supply line via the first emission control transistor ([0097], e.g., the first terminal (e.g., N1) of the drive transistor M1 is connected to a corresponding data signal line Dj via the write control transistor M2 and is connected to VDD via the first emission control transistor M5);
the second conductive terminal of the drive transistor is connected to a first terminal of the display element via the second emission control transistor (e.g., the second terminal (e.g., N3) of the drive transistor M1 is connected to a first terminal of LD via the second emission control transistor M6);
the bias application transistor has a control terminal connected to a corresponding bias control line (Fig. 2; e.g., the bias application transistor M4 has a control terminal connected to a corresponding bias control line S3i);
a second terminal of the display element is connected to the second power supply line (e.g., a second terminal of the display element LD is connected to VSS); and
the scanning-side drive circuit (Fig. 1; e.g., the scanning-side drive circuit (e.g., 400)) is further configured to drive the plurality of bias control lines during the refresh frame period such that the bias application transistor in a pixel circuit corresponding to each of the plurality of bias control lines is in ON state during the bias period (Figs 1-4; e.g., the bias application transistor M4 in a pixel circuit is in ON state during the bias period BP1 and BP3 in the refresh frame period P1).
IN in view of Sano does not specifically disclose wherein the first terminal of the bias application circuit is connected to the corresponding first scanning signal line.
However, Kim discloses a display device wherein a display portion includes a plurality of first scanning signal lines (Fig. 1; [0048]-[0072], e.g., scan lines S1), wherein a first terminal of a bias application circuit is connected to a corresponding first scanning signal line (Fig. 9B; [0097]-[0098], [0203], e.g., a first terminal of a bias application transistor M4 is connected to a corresponding first scan signal line S1i).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Kim in the invention of IN in view of Sano for connecting a first terminal of a bias application transistor to a corresponding first scanning signal line so that the corresponding first scanning signal can be used as a voltage for on-biasing a drive transistor ([0105] and [0204] of Kim).
10. Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over IN et al. (US 2021/0134210) in view of Sano (WO 2022/157822, the examiner is using US 2024/0304144 as the English Translation of WO 2022/157822), and further in view of Kim et al. (US 2021/0027696) and Park et al. (US 2014/0028648).
Regarding claim 7, IN further discloses the display device according to claim 5, wherein the display portion further includes a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of emission control lines, a first power supply line, and a second power supply line (Figs 1-2; [0060], e.g., data lines D, scan lines S1, emission control lines E, a first power supply VDD and a second power supply line VSS); the drive circuit includes:
a data-side drive circuit configured to generate and apply a plurality of data signals to the plurality of data signal lines ([0059]-[0061], e.g., the data driver 600 generates and applies a plurality of data signal to the data signal lines D); and a scanning-side drive circuit configured to selectively drive the plurality of first scanning signal lines and selectively inactivate the plurality of emission control lines ([0056], [0059]-[0066], e.g., the scan driver and the emission driver selectively drive the plurality of first scanning signal lines S1 and selectively inactivates the plurality of emission control lines E),
each of the plurality of pixel circuits corresponds to one of the plurality of data signal lines, one of the plurality of first scanning signal lines, and one of the plurality of emission control lines (Figs 1-2; e.g., each of the pixel circuits PX corresponding to one of data signal lines D, one of the plurality of first scanning signal lines S1, and one of the plurality of emission control lines E),
the at least one emission control transistor includes first and second emission control transistors each having control terminals connected to a corresponding emission control line ([0103]-[0104], e.g., first and second emission control transistors M5 and M6 each having a control terminal connected to a corresponding emission control line E),
the write control transistor further has a control terminal connected to a corresponding first scanning signal line ([0098], e.g., the write control transistor M2 has a control terminal connected to a corresponding first scan signal line S1i),
the first conduction terminal of the drive transistor is connected to a corresponding data signal line via the write control transistor, and is connected to the first power supply line via the first emission control transistor ([0097], e.g., the first terminal (e.g., N1) of the drive transistor M1 is connected to a corresponding data signal line Dj via the write control transistor M2 and is connected to VDD via the first emission control transistor M5), the second conductive terminal of the drive transistor is connected to a first terminal of the display element via the second emission control transistor (e.g., the second terminal (e.g., N3) of the drive transistor M1 is connected to a first terminal of LD via the second emission control transistor M6);
a second terminal of the display element is connected to the second power supply line (e.g., a second terminal of LD is connected to VSS); and
a bias control line (e.g., a scanning line S3) is rendered in a selected state within a period from when the corresponding emission control line changes to an inactivated state until when the corresponding first scanning signal line changes to the selected state in the refresh frame period (Figs 1-4; e.g., the bias application transistor M4 in a pixel circuit is in ON state during the bias period BP1 and BP3 in the refresh frame period P1).
IN in view of Sano does not specifically disclose wherein the first terminal of the bias application circuit is connected to the corresponding first scanning signal line; the bias application transistor has a control terminal connected to a predetermined preceding first scanning signal line; and the predetermined preceding first scanning signal line is a first scanning signal line that is selected for each of the plurality of pixel circuits from among first scanning signal lines becoming a selected state before the corresponding first scanning signal line among the plurality of first scanning signal lines, and that is rendered in the selected state within a period from when the corresponding emission control line changes to an inactivated state until when the corresponding first scanning signal line changes to the selected state in the refresh frame period.
However, Kim discloses a display device wherein a display portion includes a plurality of first scanning signal lines (Fig. 1; [0048]-[0072], e.g., scan lines S1), wherein a first terminal of a bias application circuit is connected to a corresponding first scanning signal line (Fig. 9B; [0097]-[0098], [0203], e.g., a first terminal of a bias application transistor M4 is connected to a corresponding first scan signal line S1i).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Kim in the invention of IN in view of Sano for connecting a first terminal of a bias application transistor to a corresponding first scanning signal line so that the corresponding first scanning signal can be used as a voltage for on-biasing a drive transistor ([0105] and [0204] of Kim).
IN in view of Sano does not specifically disclose wherein the bias application transistor has a control terminal connected to a predetermined preceding first scanning signal line; and the predetermined preceding first scanning signal line is a first scanning signal line that is selected for each of the plurality of pixel circuits from among first scanning signal lines becoming a selected state before the corresponding first scanning signal line among the plurality of first scanning signal lines, and that is rendered in the selected state within a period from when the corresponding emission control line changes to an inactivated state until when the corresponding first scanning signal line changes to the selected state in the refresh frame period.
However, Park discloses a display device wherein a display portion includes a plurality of first scanning signal lines and a plurality of emission control lines (Fig. 2; [0032]-[0033], e.g., first scanning signal lines S1-SNn and emission control lines E1-En); and one of a plurality of pixel circuits corresponds to one of the plurality of first scanning signal lines (Figs 2-3; [0040], e.g., one of the pixel circuits 140 corresponds to one of the plurality of first scanning signal lines), wherein each of the plurality of plurality of pixel circuit includes
at least one emission control transistor including first and second emission control transistors each having control terminals connected to a corresponding emission control line (Fig. 3; [0048]-[0049], e.g., first and second emission control transistors M6 and M7 each having a control terminal connected to a corresponding emission control line E);
a write control transistor connected to a corresponding first scanning signal line ([0046], e.g., the write control transistor M4 has a control terminal connected to a corresponding first scan signal line Sn); and
a bias application transistor having a control terminal connected to a predetermined preceding first scanning signal line, wherein the predetermined preceding first scanning signal line is a first scanning signal line that is selected for each of the plurality of pixel circuits from among first scanning signal lines becoming a selected state before the corresponding first scanning signal line among the plurality of first scanning signal lines, and that is rendered in the selected state within a period from when the corresponding emission control line changes to an inactivated state until when the corresponding first scanning signal line changes to the selected state in a refresh frame period (Figs 3-4; [0016], [0045], [0054]-[0055], [0060], e.g., the bias application transistor M3 has a control terminal connected to a predetermined preceding first scanning signal line Sn-1 which is rendered in a selected state before the corresponding first scanning signal line Sn and which is rendered in the selected state from when the corresponding emission control line En changes to an inactivated state until when the corresponding first scanning line Sn changes to the selected state).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Park in the invention of IN in view of Sano for connecting a control terminal of a bias application transistor to a predetermined preceding first scanning signal line which is selected from first scanning signal lines rendered in a selected state before a corresponding first scanning signal line among a plurality of first scanning signal lines in order to supply a bias voltage to a drive transistor before a data signal is supplied to initialize a threshold voltage of the driving transistor (see [0016] of Park).
11. Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over IN et al. (US 2021/0134210) in view of Sano (WO 2022/157822, the examiner is using US 2024/0304144 as the English Translation of WO 2022/157822), and further in view of Park et al. (US 2014/0028648).
Regarding claim 8, IN further discloses the display device according to claim 5, wherein the display portion further includes a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of second scanning signal lines, a plurality of emission control lines, a first power supply line, and a second power supply line (Figs 1-2; [0060], e.g., data lines D, scan lines S1-S3, emission control lines E, bias control lines S3i, a first power supply VDD and a second power supply line VSS);
the drive circuit includes:
a data-side drive circuit configured to generate and apply a plurality of data signals to the plurality of data signal lines ([0059]-[0061], e.g., the data driver 600 generates and applies a plurality of data signal to the data signal lines D); and
a scanning-side drive circuit configured to selectively drive the plurality of first scanning signal lines and selectively inactivates the plurality of emission control lines ([0059]-[0066], e.g., the scan driver and the emission driver 200, 300, 400 and 500 selectively drive the plurality of first scanning signal lines and selectively inactivates the plurality of emission control lines);
each of the plurality of pixel circuits corresponds to one of the plurality of data signal lines, one of the plurality of first scanning signal lines, one of the plurality of emission control lines, and one of the plurality of bias control lines (Figs 1-2; e.g., each of the pixel circuits PX corresponding to one of data signal lines Dj, one of the plurality of first scanning signal lines SLi, one of the plurality of emission control lines Ei, and one of the plurality of bias control lines S3i);
the at least one emission control transistor includes first and second emission control transistors that are both of a P-channel type and each have control terminals connected to a corresponding emission control line ([0103]-[0104], e.g., first and second emission control transistors M5 and M6);
the write control transistor is of a P-channel type and further has a control terminal connected to a corresponding first scanning signal line ([0098], e.g., the write control transistor M2 has a control terminal connected to a corresponding first scan signal line SLi);
the threshold compensation transistor is of an N-channel type and further has a control terminal connected to a corresponding second scanning signal line ([0099]-[0100], e.g., the threshold compensation transistor M3 has a control terminal connected to a corresponding second scanning signal line S2i);
the drive transistor is of a P-channel type, and has the first conduction terminal connected to a corresponding data signal line via the write control transistor and to the first power supply line via the first emission control transistor, and the second conduction terminal connected to a first terminal of the display element via the second emission control transistor ([0097], e.g., e.g., the first terminal (e.g., N1) of the drive transistor M1 is connected to a corresponding data signal line Dj via the write control transistor M2 and is connected to VDD via the first emission control transistor M5 and the second terminal (e.g., N3) of the drive transistor M1 is connected to a first terminal of LD via the second emission control transistor M6), and
a second terminal of the display element connected to the second power supply line (e.g., a second terminal of LD is connected to VSS); and
the bias application transistor has a control terminal connected to a scanning signal line (Fig. 2; e.g., the bias application transistor M4 has a control terminal connected to the scanning signal line S3i), the scanning signal line turning on the bias application transistor within a period from when the corresponding emission control line changes to an inactivated state until when the corresponding first scanning signal line changes to the selected state in the refresh frame period (Fig. 3; e.g., in the refresh frame period P1, the scanning line S3i turns on the bias application transistor M4 within a period BP1);
the first terminal of the bias application circuit is connected to either the first power supply line, the corresponding first scanning signal line, or the corresponding emission control line (Fig. 11; e.g., the first terminal of the bias application transistor M4 is connected to the emission control line Ei).
IN in view of Sano does not specifically disclose wherein the control terminal of the bias application transistor is connected to a scanning signal line which is selected from first scanning signal lines rendered in a selected state before the corresponding first scanning signal line among the plurality of first scanning signal lines and second scanning signal lines rendered in the selected state before the corresponding second scanning signal line among the plurality of second scanning signal lines.
However, Park discloses a display device wherein a display portion includes a plurality of first scanning signal lines (Fig. 2; [0032]-[0033], e.g., first scanning signal lines S1-SNn); and one of a plurality of pixel circuits corresponds to one of the plurality of first scanning signal lines (Figs 2-3; [0040], e.g., one of the pixel circuits 140 corresponds to one of the plurality of first scanning signal lines), wherein each of the plurality of plurality of pixel circuit includes
a write control transistor connected to a corresponding first scanning signal line ([0046], e.g., the write control transistor M4 has a control terminal connected to a corresponding first scan signal line Sn); and
a bias application transistor connected to a scanning signal line which is selected from first scanning signal lines rendered in a selected state before the corresponding first scanning signal line among the plurality of first scanning signal lines (Figs 3-4; [0016], [0045], [0054]-[0055], [0060], e.g., the bias application transistor M3 has a control terminal connected to a first scanning signal line Sn-1 which is rendered in a selected state before the corresponding first scanning signal line Sn).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Park in the invention of IN in view of Sano for connecting a control terminal of a bias application transistor to a scanning signal line which is selected from first scanning signal lines rendered in a selected state before a corresponding first scanning signal line among a plurality of first scanning signal lines in order to supply a bias voltage to a drive transistor before a data signal is supplied to initialize a threshold voltage of the driving transistor (see [0016] of Park).
Allowable Subject Matter
12. Claims 3-4 and 9-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
13. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Noh et al. (US 2024/0257739) discloses a display device comprising a bias application transistor configured to apply a bias voltage to a first terminal of a drive transistor, wherein the bias application transistor has a first terminal configured to receive a signal provided to control terminals of transistors each of which is included in the each of the plurality of pixel circuits or in another pixel circuit, but none of which are included in the bias application circuit, and a second terminal connected to the first terminal of the drive transistor, and the bias application transistor is configured to apply the bias voltage to the first conductive terminal of the drive transistor based on the signal received at the first terminal (Figs 1-3).
Yuan (US 2021/0383743) discloses a method comprising performing a pause driving by driving a plurality of pixel circuits such that a drive period and a pause period alternately appear, the drive period consisting of one or more refresh frame periods in which voltage of a plurality of data signals is written, as data voltage, to the plurality of pixel circuits, the pause period consisting of one or more non-refresh frame periods in which writing of data voltage to the plurality of pixel circuits is stopped, wherein the performing the pause driving includes performing a bias application by driving the plurality of pixel circuits such that the bias application circuit applies a bias voltage to a first conduction terminal of a drive transistor based on a voltage received at a first terminal within a period during which an emission control transistor in each of the plurality of pixel circuits is in OFF state in both the refresh frame period and the non-refresh frame period (see Figs 17 and 22).
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/HONG ZHOU/Primary Examiner, Art Unit 2629
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