DETAILED ACTION
This is the first office action on the merits for 19/149,194, filed 7/18/2025, which is a national stage entry of PCT/CN2025/075203, filed 1/26/2025, which claims priority to Chinese applications CN202410175669.8, filed 2/7/2024, and CN202410175657.5, filed 2/7/2024.
Claims 1-4, 8, 10-13, 16-17, 20-22, 24, 27, 29-30, and 38-39 are pending; Claims 1-4, 8, 10-13, 16-17, 20-22, 24, 27, 29-30 are examined herein.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the invention of Group I, Claims 1-4, 8, 10-13, 16-17, 20-22, 24, 27, and 29-30, in the reply filed on 3/10/2026 is acknowledged.
Additional Prior Art
The Examiner wishes to apprise the Applicant of the following references, which are not currently applied in a rejection.
Chen, et al. (Solar Energy, 178, (2019) 308-313): This reference teaches an interdigitated back contact solar cell with a focus on the separation of adjacent back contacts.
Franklin, et al. (Prog. Photovolt: Res. Appl. 2016: 24: 411-417): This reference teaches an interdigitated back contact solar cell with a rear passivation layer and point contacts.
Claim Objections
Claim 1 is objected to because of the following informalities: Claim 1 recites the term “dopes” in line 18. It is the Examiner’s position that this limitation should read “doped.” Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 8, 10-13, 16-17, 20-22, 24, 27, and 29-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a width of a strip-shaped doped region corresponding to the conductive semiconductor structure in the first doped region” and “a width of a strip-shaped doped region corresponding to the conductive semiconductor structure in the second doped region” in lines 20-22.
These limitations are indefinite, because the structure required by “a strip-shaped doped region corresponding to the conductive semiconductor structure in the first doped region” and “a strip-shaped doped region corresponding to the conductive semiconductor structure in the second doped region” are unclear. Specifically, it is unclear how the strip shaped doped regions “correspond” to the respective conductive semiconductor structures.
Claims 2-4, 8, 10-13, 16-17, 20-22, 24, 27, and 29-30 are indefinite, because of their dependence on Claim 1.
Claim 8 recites “wherein a disposition manner corresponding to the second conductive semiconductor portion is electrical disposition.” This limitation is indefinite, because it is unclear what structure is required by this limitation.
Claim 11 recites “wherein a width of the connection regions corresponding to the conductive semiconductor structure in the first doped region and the second doped region is W1.” This limitation is indefinite, because it is unclear what structure is required by “the connection regions corresponding to the conductive semiconductor structure in the first doped region and the second doped region.” The indefiniteness of this claim prevents the application of prior art at this time.
Claim 12 recites “a width of the connection region that belongs to one of the first doped region and the second doped region and corresponds to the conductive semiconductor structure is W1.” This limitation is indefinite, because it is unclear what structure is required by “the connection region that belongs to one of the first doped region and the second doped region and corresponds to the conductive semiconductor structure.” The indefiniteness of this claim prevents the application of prior art at this time.
Claim 13 recites “wherein a disposition manner corresponding to the second conductive semiconductor portion is insulation disposition.” This limitation is indefinite, because it is unclear what structure is required by this limitation. The indefiniteness of this claim prevents the application of prior art at this time.
Claim 20 recites “the different plurality of conductive semiconductor structures.” There is insufficient antecedent basis for this limitation, because there is no prior recitation of “different plurality of conductive semiconductor structures.”
Claim 21 recites “the different plurality of conductive semiconductor structures.” There is insufficient antecedent basis for this limitation, because there is no prior recitation of “different plurality of conductive semiconductor structures.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 8, 10, 16, 20, 27, and 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hasegawa, et al. (U.S. Patent Application Publication 2014/0020740 A1).
In reference to Claim 1, Hasegawa teaches a back contact solar cell (Fig. 2, paragraphs [0022]-[0057]).
The back contact solar cell comprises a semiconductor substrate 10 (paragraph [0024]), a first doped region 12n (paragraph [0026]), a second doped region 13p (paragraph [0028]), and at least one conductive semiconductor structure (corresponding to the portions of layers 12i and 12n indicated in the inset below).
Hasegawa teaches that the first doped region 12n and the second doped region 13p are alternately spaced apart on a back surface of the semiconductor substrate 10 (Fig. 2).
Hasegawa teaches that the first doped region 12n and the second doped region 13p have opposite conduction types (paragraphs [0026] and [0028]).
Hasegawa teaches that a spacer region 18 is located between the first doped region 12n and the second doped region 13p along an arrangement direction of the first doped region 12n and the second doped region 13p (Fig. 2, paragraph [0035]).
Fig. 1 teaches that the first doped region 12n and the second doped region 13p each comprise a plurality of strip-shaped doped regions.
The inset below teaches that the conductive semiconductor structure comprises a first conductive semiconductor portion 12n and a second conductive semiconductor portion 12i in electrical contact with each other.
The inset below teaches that the first conductive semiconductor portion 12n is located in the spacer region 18 (i.e. above and in the vicinity of spacer 18).
Hasegawa teaches that a conduction type of the first conductive semiconductor portion 12n is opposite to a conduction type of the second doped region 13p (paragraph [0026]).
Hasegawa teaches that at least a part of the first doped region 12n and at least a part of the second doped region 13p are electrically connected to the first conductive semiconductor portion (corresponding to the portion of layer 12n indicated in the inset below). It is the Examiner’s position that all of these structures are electrically connected to each other at minimum via the substrate 10.
Fig. 2 teaches that the second conductive semiconductor portion 12i is disposed above a part of the second doped region 13p, wherein the part of the second doped region 13p faces away from the semiconductor substrate 10 (i.e. has a surface facing away from the semiconductor substrate 10).
Hasegawa teaches that a width of a strip-shaped doped region corresponding to the conductive semiconductor structure (which corresponds to the portions of layers 12i and 12n indicated in the inset below) in the first doped region (i.e. overlapping with layer 12n) is D2 (as indicated in the inset below).
Hasegawa teaches that a width of a strip-shaped doped region corresponding to the conductive semiconductor structure (which corresponds to the portions of layers 12i and 12n indicated in the inset below) in the second doped region 13p (i.e. overlapping with layer 13p) is D3 (indicated in the inset below).
Hasegawa teaches that a width of a part of the second conductive semiconductor portion 12i is X1. As indicated below, X1 corresponds to a width of 1/3 of D3.
The inset below teaches that the part of the second conductive semiconductor portion 12i is disposed above the strip-shaped doped regions comprised in the second doped region 13p along a width direction of the strip-shaped doped regions 13p.
Hasegawa teaches that, when the second conductive semiconductor portion 12i is disposed above the strip- shaped doped regions comprised in the second doped region 13p, 0.1≤D3≤X1<0.5D3. Specifically, X1 is shown in the inset below to be 1/3 of the width of D3. It is noted that Claim 1 does not provide limits on how to select the dimension of portion X1.
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In reference to Claim 2, the inset below teaches that the solar cell comprises a contact surface between the second doped region 13p that has a conduction type opposite to that of the conductive semiconductor structure, and the conductive semiconductor structure (indicated in the inset below). This “contact surface” corresponds to the electrode 15 connecting the conductive semiconductor structure and its corresponding layer 13p.
The inset below teaches that this contact surface comprises a side effective electrical contact surface, wherein a height of the side effective electrical contact surface is a side effective electrical contact height Z2 and an extension direction of the side effective electrical contact surface is parallel to a thickness direction of the semiconductor substrate.
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In reference to Claim 3, Figs. 1-2 teach that the strip-shaped doped regions comprised in the first doped region (with dopant regions 12n) and the strip-shaped doped regions comprised in the second doped region (i.e. with doped regions 13p) are spaced apart in parallel.
The inset of Fig. 2 under the rejection of Claim 1 above teaches that the first conductive semiconductor portion 12n comprised in the conductive semiconductor structure is located between two adjacent strip-shaped doped regions respectively belonging to the first doped region 12n and the second doped region 13p.
The inset of Fig. 2 under the rejection of Claim 1 above teaches that a width direction of the conductive semiconductor structure is parallel to an extension direction of the strip-shaped doped regions (i.e. a direction in which these doped regions extend).
In reference to Claim 4, Hasegawa teaches that the first doped region 12n and the second doped region alternate interdigitatedly (Fig. 1).
Fig. 1 teaches that each of the first doped region 12n and the second doped region 13p comprises a plurality of strip-shaped doped regions and at least one connection region.
Figs. 1 and 2 teaches that the strip-shaped doped regions comprised in the first doped region 12n and the strip-shaped doped regions comprised in the second doped region 13p are alternately spaced apart in parallel.
Fig. 1 teaches that each connection region is electrically connected to the corresponding strip-shaped doped region having a same conduction type as the connection region.
Fig. 1 teaches that an extension direction of the connection region is different from an extension direction of the strip-shaped doped regions.
Figs. 1-2 teach that the first conductive semiconductor portion comprised in at least one conductive semiconductor structure is located between one strip-shaped doped region comprised in one of the first doped region and the second doped region and an adjacent connection region comprised in the other doped region, wherein a width direction of the conductive semiconductor structure is parallel to a distribution direction of the strip-shaped doped regions having the opposite conduction types.
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In reference to Claim 8, it is noted that Claim 8 is indefinite, as described above.
The following rejection represents the Examiner’s best understanding of the indefinite claim limitations.
The inset below teaches that a width of the conductive semiconductor structure along an extension direction of the spacer region is W, wherein W = D3.
The inset below teaches that a disposition manner corresponding to the second conductive semiconductor portion is electrical disposition (i.e. that the second conductive semiconductor portion is electrically connected to layer 15).
As described in the rejection of Claim 1 above, X1 = 1/3 of D3, so X1 = 1/3 of W.
Therefore, X1≤W≤40X1.
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In reference to Claim 10, the inset of Fig. 2 under the rejection of Claim 1 below teaches that a width of a part of the second conductive semiconductor portion is X2, wherein the part of the second conductive portion is disposed above the strip-shaped doped regions comprised in the second doped region 13p along the extension direction of the strip- shaped doped regions, and wherein: when the second conductive semiconductor portion is disposed above the strip- shaped doped regions comprised in the second doped region, 0.1D3<X2<1.2D3. Specifically, X2 is shown in the inset below to be 2/3 of the width of D3. It is noted that Claim 10 does not provide limits on how to select the dimension of portion X1.
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In reference to Claim 16, the inset of Fig. 2 of Hasegawa above teaches that the back contact solar cell comprises a plurality of conductive semiconductor structures, wherein adjacent conductive semiconductor structures are spaced apart.
In reference to Claim 20, Figs. 1-2 teach that orthographic projection areas of the different plurality of conductive semiconductor structures on the back surface are equal; and/or the different plurality of conductive semiconductor structures are evenly distributed on the back surface.
In reference to Claim 27, Fig. 2 of Hasegawa teaches that a width of a spacer region located between the first doped region 12n and the second doped region 13p is D1 (which corresponds to “W3” in Fig. 2, paragraph [0036]).
Fig. 2 teaches that a width of the conductive semiconductor structure along an extension direction of the spacer region is W (which corresponds to the value of W3 – W5, as shown in the inset below).
Hasegawa teaches that, in his Fig. 2, W5 has a dimension of 1/3 of W3 (paragraph [0043]).
Therefore, a width of the conductive semiconductor structure along an extension direction of the spacer region (i.e. D1) is equal to W3 – W5 = W3 – 1/3 W3 = 2/3 W3
This disclosure teaches the limitations of Claim 27, wherein 0.5D1<W<6D1, because W = 0.67 D1.
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In reference to Claim 30, Fig. 2 of Hasegawa teaches that at least one of the first doped region 12n, the second doped region 13p, and the conductive semiconductor structure (which is indicated in the inset above) comprises a doped semiconductor layer 12n located on the back surface of the semiconductor substrate (paragraphs [0022]-[0057]).
Hasegawa further teaches that the back contact solar cell further comprises a passivation layer, corresponding to the portion of layer 12i indicated in the inset below (Fig. 2, paragraph [0027]), located between the semiconductor substrate 10 and the doped semiconductor layer 12n. Hasegawa teaches that this layer is a several Ångstrom thick intrinsic silicon layer (paragraph [0027]).
Paragraph 182 of the instant specification recognizes intrinsic Si as a passivation layer.
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 17, 24, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa, et al. (U.S. Patent Application Publication 2014/0020740 A1).
In reference to Claim 17, Hasegawa does not teach that the solar cell of his invention necessarily has the structure required by Claim 17.
However, he teaches that the width of the p-type electrodes 15 should be 50-2000 microns (paragraph [0034]).
He further teaches that the width of the n-type electrodes 14 should be controlled, to suppress the disappearance of minority carriers (paragraph [0056]), and to ensure good electrical resistance (paragraph [0057]).
Therefore, absent a showing of persuasive secondary considerations, it would have been obvious to one of ordinary skill in the art at the time the instant invention was filed to have optimized the number and spacing of the electrodes on the rear surface of the device of Hasegawa, in order to optimize the minority carrier collection and electrical resistance.
It is the Examiner’s position that this routine optimization would have led one of ordinary skill in the art at the time the instant invention was filed to have arrived at a structure that meets the limitations of Claim 17, without undue experimentation.
In reference to Claim 24, Hasegawa does not teach that the solar cell of his invention necessarily has the structure required by Claim 24.
However, he teaches that the width of the p-type electrodes 15 should be 50-2000 microns (paragraph [0034]).
He further teaches that the width of the n-type electrodes 14 should be controlled, to suppress the disappearance of minority carriers (paragraph [0056]), and to ensure good electrical resistance (paragraph [0057]).
Therefore, absent a showing of persuasive secondary considerations, it would have been obvious to one of ordinary skill in the art at the time the instant invention was filed to have optimized the number and spacing of the electrodes on the rear surface of the device of Hasegawa, in order to optimize the minority carrier collection and electrical resistance.
It is the Examiner’s position that this routine optimization would have led one of ordinary skill in the art at the time the instant invention was filed to have arrived at a structure that meets the limitations of Claim 24, without undue experimentation.
In reference to Claim 29, Fig. 2 teaches that the back contact solar cell further comprises a surface passivation layer 12i and an electrode structure 14/15 (paragraphs [0027] and [0043]-0045]).
Hasegawa teaches that this layer is a several Ångstrom thick intrinsic silicon layer (paragraph [0027]).
Paragraph 182 of the instant specification recognizes intrinsic Si as a passivation layer.
Fig. 2 teaches that the surface passivation layer 12i is formed on (i.e. disposed on) at least the first doped region 12n, the second doped region 13p, and the conductive semiconductor structure (which is indicated in the inset under the rejection of Claim 1 above).
Fig. 2 teaches that the electrode structure 14/15 extends through the surface passivation layer 12i, and is separately in ohmic contact with the first doped region 12n (via electrode regions 14) and the second doped region (via electrode regions 15).
Fig. 2 teaches that a first part 14 of the electrode structure and a second part 15 of the electrode structure are isolated from each other.
Fig. 2 teaches that the first part 14 of the electrode structure is electrically connected to the first doped region 12n, and the second part 15 of the electrode structure is electrically connected to the second doped region 13p.
Hasegawa teaches that, along a direction parallel to the back surface, a minimum spacing between the electrode structure (i.e. layer 15) and a part of the surface passivation layer 12i is W5 (Fig. 2). Fig. 2 teaches that this “part of the surface passivation layer” 12i covers (i.e. is disposed over) the conductive semiconductor structure (which is indicated in the inset under the rejection of Claim 1 above)
The value of W5 is 1/3 of the value of W3 (paragraph [0043]), the value of W3 is 1/3 of the value of W1, and W1 is taught to be 50-2000 microns (paragraph [0034]).
Therefore, the value of W5 is in the range of 5.6-222 microns.
This disclosure teaches the limitations of Claim 29, wherein a minimum spacing between the electrode structure and a part of the surface passivation layer 12i is greater than or equal to 30 μm and is less than or equal to 250 μm.
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. See MPEP 2144.05 I.
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Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa, et al. (U.S. Patent Application Publication 2014/0020740 A1), in view of Westerberg, et al. (U.S. Patent Application Publication 2016/0087122 A1).
In reference to Claim 21, Hasegawa does not teach that the different plurality of conductive semiconductor structures are distributed on the back surface in the matrix form recited in Claim 21.
To solve the same problem of providing a back contact solar cell, Westerberg teaches a solar cell in which rear contact structures are formed to have a dot shape arranged in a matrix (Fig. 8B, with additional details given in Fig. 5, paragraphs [0043]-]0044] and [0052]-[0053]), instead of in a stripe shape, as in Hasegawa.
Westerberg teaches that the dot-shaped contact structures in the device of his invention provide the benefit of improved breakdown performance of the device and increased junction area (paragraph [0029]).
Therefore, absent a showing of persuasive secondary considerations, it would have been obvious to one of ordinary skill in the art at the time the instant invention was filed to have formed the rear contact structure of the device of Hasegawa to have the matrix shape taught by Westerberg, in order to realize the taught benefits of this structure.
Forming the rear contact structure of the device of Hasegawa to have the matrix shape taught by Westerberg, teaches the limitations of Claim 21, wherein the different plurality of conductive semiconductor structures are distributed on the back surface in a matrix form (Westerberg, Figs. 5 and 8), wherein adjacent rows of the conductive semiconductor structures distributed in the matrix form are aligned with each other.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa, et al. (U.S. Patent Application Publication 2014/0020740 A1), in view of Abiko, et al. (U.S. Patent Application Publication 2011/0197951 A1).
In reference to Claim 21, Hasegawa does not teach that the different plurality of conductive semiconductor structures are distributed on the back surface in the matrix form recited in Claim 21.
To solve the same problem of providing a back contact solar cell, Abiko teaches a solar cell in which rear contact structures are formed to have a dot shape arranged in a matrix (Fig. 16, paragraph [0016])), instead of in a stripe shape, as in Hasegawa.
Abiko teaches that the dot-shaped contact structures in the device of his invention provide the benefit of improved passivation and output (paragraph [0066]).
Therefore, absent a showing of persuasive secondary considerations, it would have been obvious to one of ordinary skill in the art at the time the instant invention was filed to have formed the rear contact structure of the device of Hasegawa to have the matrix shape taught by Abiko, in order to realize the taught benefits of this structure.
Forming the rear contact structure of the device of Hasegawa to have the matrix shape taught by Abiko, teaches the limitations of Claim 21, wherein the different plurality of conductive semiconductor structures are distributed on the back surface in a matrix form (Abiko, Fig. 16), wherein adjacent rows of the conductive semiconductor structures distributed in the matrix form are staggered from each other.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa, et al. (U.S. Patent Application Publication 2014/0020740 A1), in view of Abiko, et al. (U.S. Patent Application Publication 2011/0197951 A1), and further in view of Carlson (U.S. Patent Application Publication 2006/0130891 A1).
In reference to Claim 22, modified Hasegawa as applied to Claim 21 teaches that the adjacent rows of the conductive semiconductor structures distributed in the matrix form are staggered from each other (as described above).
Modified Hasegawa as applied to Claim 21 is silent regarding the spacing of the point contacts; therefore, he does not teach the remaining limitations of Claim 22.
To solve the same problem of providing a back contact solar cell with back point contacts, Carlson teaches that the spacing between point contacts of opposite polarities should be less than the diffusion distance of minority carriers (paragraph [0034]), and that the spacing of adjacent point contacts should be optimized to minimize series resistance of the solar cell and maximize solar cell performance (paragraph [0047]).
Therefore, absent a showing of persuasive secondary considerations, it would have been obvious to one of ordinary skill in the art at the time the instant invention was filed to have optimized the spacing of the point contacts of modified Hasegawa, in order to minimize series resistance of the solar cell and maximize solar cell performance, as taught by Carlson (Carlson, paragraph [0047]).
It is the Examiner’s position that this routine optimization would have led one of ordinary skill in the art at the time the instant invention was filed to have arrived at a structure meeting the limitations of Claim 22, without undue experimentation.
Conclusion
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/SADIE WHITE/Primary Examiner, Art Unit 1721
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