DETAILED ACTION
Status of the Claims
The filing dated 4/3/25 is entered. Claims 1-20 are pending.
Foreign Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statements
The information disclosure statement (IDS) submitted on 4/3/25 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7-12, and 14-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hong, US-20230137365.
In regards to claim 1, Hong discloses a display device (Par. 0002 “display device”) comprising: a display panel (Fig. 1, 100 display panel) comprising sub-pixels (Fig. 1, 101 pixels); and a panel driver (Par. 0049 “a display panel driver for writing pixel data to pixels 101 in the display panel 100”) configured to sequentially apply data voltages to the sub-pixels in units of rows in an active period of one frame (Par. 0075 “The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130 in the display mode. The gate driver 120 may sequentially supply the gate signals to the gate lines 103 by shifting the gate signals using a shift register.”, i.e. sequential driving in a display mode, i.e. active period; Par. 0067 “The sensing mode may be activated in at least one of a power on sequence in which the display device is powered on and the display panel driver starts driving, a vertical blank VB between frame periods”), and to perform a sensing operation (Par. 0099 sensing mode) on first sub-pixels emitting light of a first color among sub-pixels (Fig. 2, R G B pixels) arranged on any one row among the sub-pixels (Fig. 8, BL pixel block; Par. 0111 “a block BL may be set to a size of 30 pixels×30 pixels, but is not limited thereto”) in a blank period of the one frame (Par. 0067 “The sensing mode may be activated in at least one of a power on sequence in which the display device is powered on and the display panel driver starts driving, a vertical blank VB between frame periods”), wherein the panel driver is configured to apply preliminary data voltages to the first sub-pixels before (Fig. 6, sensing mode with Tw data writing period and application of Vsdata; Par. 0100 “the sensing data voltage Vsdata may be set to a full white voltage (e.g., white image data) or a full gray voltage of pure colors (R, G, and B) in order to increase the gate-source voltage Vgs of the driving element DT. The full white voltage is a maximum voltage of R, G, and B data applied to the R, G, and B sub-pixels. The full gray voltage of the pure colors is a maximum voltage applied to a sub-pixel having any one of R, G, and B colors.”) the sensing operation in the blank period (Fig. 6, Tvsc non-light emission sensing period).
In regards to claim 7, Hong discloses method of driving a display device (Par. 0002 “display device”; Par. 0026 “a driving signal for each mode of a pixel circuit”; Fig. 9), the method comprising: sequentially driving sub-pixels in units of rows in an active period of one frame (Par. 0075 “The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130 in the display mode. The gate driver 120 may sequentially supply the gate signals to the gate lines 103 by shifting the gate signals using a shift register.”, i.e. sequential driving in a display mode, i.e. active period; Par. 0067 “The sensing mode may be activated in at least one of a power on sequence in which the display device is powered on and the display panel driver starts driving, a vertical blank VB between frame periods”); driving first sub-pixels emitting light of a first color among sub-pixels (Fig. 2, R G B pixels) arranged on any one row among the sub-pixels (Fig. 8, BL pixel block; Par. 0111 “a block BL may be set to a size of 30 pixels×30 pixels, but is not limited thereto”) in a preliminary emission period of the one frame (Fig. 6, sensing mode with Tw data writing period and application of Vsdata; Par. 0100 “the sensing data voltage Vsdata may be set to a full white voltage (e.g., white image data) or a full gray voltage of pure colors (R, G, and B) in order to increase the gate-source voltage Vgs of the driving element DT. The full white voltage is a maximum voltage of R, G, and B data applied to the R, G, and B sub-pixels. The full gray voltage of the pure colors is a maximum voltage applied to a sub-pixel having any one of R, G, and B colors.”); and sensing the first sub-pixels in a sensing period of the one frame (Fig. 6, Tvsc non-light emission sensing period).
In regards to claim 14, Hong discloses electronic device (Par. 0002 “display device”), comprising: a processor configured to provide input image data (Par. 0004, receiving input image data, which is provided by a “processor”, i.e. device); and a display device (Par. 0002 “display device”) configured to display an image based on the input image data (Par. 0050 “The display panel 100 includes a pixel array that displays an input image on a screen”), the display device comprising: a display panel (Fig. 1, 100 display panel) comprising sub-pixels (Fig. 1, 101 pixels); and a panel driver (Par. 0049 “a display panel driver for writing pixel data to pixels 101 in the display panel 100”) configured to sequentially drive the sub-pixels in units of rows in an active period of one frame (Par. 0075 “The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130 in the display mode. The gate driver 120 may sequentially supply the gate signals to the gate lines 103 by shifting the gate signals using a shift register.”, i.e. sequential driving in a display mode, i.e. active period; Par. 0067 “The sensing mode may be activated in at least one of a power on sequence in which the display device is powered on and the display panel driver starts driving, a vertical blank VB between frame periods”), and to sense (Par. 0099 sensing mode) first sub-pixels emitting light of a first color among sub-pixels (Fig. 2, R G B pixels) arranged on any one row among the sub-pixels (Fig. 8, BL pixel block; Par. 0111 “a block BL may be set to a size of 30 pixels×30 pixels, but is not limited thereto”) in a sensing period of the one frame (Par. 0067 “The sensing mode may be activated in at least one of a power on sequence in which the display device is powered on and the display panel driver starts driving, a vertical blank VB between frame periods”), the panel driver being configured to drive the first sub-pixels in a preliminary emission period (Fig. 6, sensing mode with Tw data writing period and application of Vsdata; Par. 0100 “the sensing data voltage Vsdata may be set to a full white voltage (e.g., white image data) or a full gray voltage of pure colors (R, G, and B) in order to increase the gate-source voltage Vgs of the driving element DT. The full white voltage is a maximum voltage of R, G, and B data applied to the R, G, and B sub-pixels. The full gray voltage of the pure colors is a maximum voltage applied to a sub-pixel having any one of R, G, and B colors.”) between the active period (Par. 0075 “The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130 in the display mode. The gate driver 120 may sequentially supply the gate signals to the gate lines 103 by shifting the gate signals using a shift register.”, i.e. sequential driving in a display mode, i.e. active period; Par. 0067 “The sensing mode may be activated in at least one of a power on sequence in which the display device is powered on and the display panel driver starts driving, a vertical blank VB between frame periods”) and the sensing period (Fig. 6, Tvsc non-light emission sensing period).
In regards to claim 2, Hong discloses the panel driver is configured to apply black data voltages to sub-pixels arranged on the same row as the first sub-pixels before the sensing operation in the blank period (Fig. 6, sensing mode with Tw data writing period and application of Vsdata; Par. 0100 “the sensing data voltage Vsdata may be set to a full white voltage (e.g., white image data) or a full gray voltage of pure colors (R, G, and B) in order to increase the gate-source voltage Vgs of the driving element DT. The full white voltage is a maximum voltage of R, G, and B data applied to the R, G, and B sub-pixels. The full gray voltage of the pure colors is a maximum voltage applied to a sub-pixel having any one of R, G, and B colors.”; Par. 0112 “the sensing data voltage Vsdata is sequentially applied to the blocks BL in units of blocks. The sensing data voltage Vsdata is applied to the pixels 101 in a target block BL for the current measurement, whereas a black grayscale voltage is applied to the pixels 101 in other blocks BL not being sensed. Since the driving element DT is turned off in the pixels 101 to which the black grayscale voltage is applied, no current flow in the pixels 101.”).
In regards to claim 9, Hong discloses in the driving of the first sub-pixels, sub-pixels arranged on the same row as the first sub-pixels are not driven (Fig. 6, sensing mode with Tw data writing period and application of Vsdata; Par. 0100 “the sensing data voltage Vsdata may be set to a full white voltage (e.g., white image data) or a full gray voltage of pure colors (R, G, and B) in order to increase the gate-source voltage Vgs of the driving element DT. The full white voltage is a maximum voltage of R, G, and B data applied to the R, G, and B sub-pixels. The full gray voltage of the pure colors is a maximum voltage applied to a sub-pixel having any one of R, G, and B colors.”; Par. 0112 “the sensing data voltage Vsdata is sequentially applied to the blocks BL in units of blocks. The sensing data voltage Vsdata is applied to the pixels 101 in a target block BL for the current measurement, whereas a black grayscale voltage is applied to the pixels 101 in other blocks BL not being sensed. Since the driving element DT is turned off in the pixels 101 to which the black grayscale voltage is applied, no current flow in the pixels 101.”, i.e. not driven).
In regards to claim 16, Hong discloses the panel driver does not drive sub-pixels arranged on the same row as the first sub-pixels in the preliminary emission period (Fig. 6, sensing mode with Tw data writing period and application of Vsdata; Par. 0100 “the sensing data voltage Vsdata may be set to a full white voltage (e.g., white image data) or a full gray voltage of pure colors (R, G, and B) in order to increase the gate-source voltage Vgs of the driving element DT. The full white voltage is a maximum voltage of R, G, and B data applied to the R, G, and B sub-pixels. The full gray voltage of the pure colors is a maximum voltage applied to a sub-pixel having any one of R, G, and B colors.”; Par. 0112 “the sensing data voltage Vsdata is sequentially applied to the blocks BL in units of blocks. The sensing data voltage Vsdata is applied to the pixels 101 in a target block BL for the current measurement, whereas a black grayscale voltage is applied to the pixels 101 in other blocks BL not being sensed. Since the driving element DT is turned off in the pixels 101 to which the black grayscale voltage is applied, no current flow in the pixels 101.”, i.e. not driven).
In regards to claim 3, Hong discloses the panel driver is further configured to apply the preliminary data voltages to second sub-pixels that are arranged on the same row as the first sub-pixels and emit light of a second color before the sensing operation in the blank period (Fig. 6, sensing mode with Tw data writing period and application of Vsdata; Par. 0100 “the sensing data voltage Vsdata may be set to a full white voltage (e.g., white image data) or a full gray voltage of pure colors (R, G, and B) in order to increase the gate-source voltage Vgs of the driving element DT. The full white voltage is a maximum voltage of R, G, and B data applied to the R, G, and B sub-pixels. The full gray voltage of the pure colors is a maximum voltage applied to a sub-pixel having any one of R, G, and B colors.”; a red green and blue subpixel are driven to create a white image data; Par. 0067 “The sensing mode may be activated in at least one of a power on sequence in which the display device is powered on and the display panel driver starts driving, a vertical blank VB between frame periods”).
In regards to claim 10, Hong discloses driving second sub-pixels that are arranged on the same row as the first sub-pixels and emit light of a second color in the preliminary emission period, before the sensing the first sub-pixels (Fig. 6, sensing mode with Tw data writing period and application of Vsdata; Par. 0100 “the sensing data voltage Vsdata may be set to a full white voltage (e.g., white image data) or a full gray voltage of pure colors (R, G, and B) in order to increase the gate-source voltage Vgs of the driving element DT. The full white voltage is a maximum voltage of R, G, and B data applied to the R, G, and B sub-pixels. The full gray voltage of the pure colors is a maximum voltage applied to a sub-pixel having any one of R, G, and B colors.”; a red green and blue subpixel are driven to create a white image data; Par. 0067 “The sensing mode may be activated in at least one of a power on sequence in which the display device is powered on and the display panel driver starts driving, a vertical blank VB between frame periods”).
In regards to claim 17, Hong discloses the panel driver is further configured to drive second sub-pixels that are arranged on the same row as the first sub-pixels and emit light of a second color in the preliminary emission period (Fig. 6, sensing mode with Tw data writing period and application of Vsdata; Par. 0100 “the sensing data voltage Vsdata may be set to a full white voltage (e.g., white image data) or a full gray voltage of pure colors (R, G, and B) in order to increase the gate-source voltage Vgs of the driving element DT. The full white voltage is a maximum voltage of R, G, and B data applied to the R, G, and B sub-pixels. The full gray voltage of the pure colors is a maximum voltage applied to a sub-pixel having any one of R, G, and B colors.”; a red green and blue subpixel are driven to create a white image data; Par. 0067 “The sensing mode may be activated in at least one of a power on sequence in which the display device is powered on and the display panel driver starts driving, a vertical blank VB between frame periods”).
In regards to claim 4, Hong discloses the panel driver is configured to apply black data voltages to sub-pixels arranged on the same row as the first sub-pixels and the second sub-pixels before the sensing operation in the blank period (Par. 0112 “the sensing data voltage Vsdata is sequentially applied to the blocks BL in units of blocks. The sensing data voltage Vsdata is applied to the pixels 101 in a target block BL for the current measurement, whereas a black grayscale voltage is applied to the pixels 101 in other blocks BL not being sensed. Since the driving element DT is turned off in the pixels 101 to which the black grayscale voltage is applied, no current flow in the pixels 101.”).
In regards to claim 11, Hong discloses in the driving of the second sub-pixels, sub-pixels arranged on the same row as the first sub-pixels and the second sub-pixels are not driven (Par. 0112 “the sensing data voltage Vsdata is sequentially applied to the blocks BL in units of blocks. The sensing data voltage Vsdata is applied to the pixels 101 in a target block BL for the current measurement, whereas a black grayscale voltage is applied to the pixels 101 in other blocks BL not being sensed. Since the driving element DT is turned off in the pixels 101 to which the black grayscale voltage is applied, no current flow in the pixels 101.”, i.e. not driven).
In regards to claim 18, Hong discloses the panel driver does not drive sub-pixels arranged on the same row as the first sub-pixels and the second sub-pixels in the preliminary emission period (Par. 0112 “the sensing data voltage Vsdata is sequentially applied to the blocks BL in units of blocks. The sensing data voltage Vsdata is applied to the pixels 101 in a target block BL for the current measurement, whereas a black grayscale voltage is applied to the pixels 101 in other blocks BL not being sensed. Since the driving element DT is turned off in the pixels 101 to which the black grayscale voltage is applied, no current flow in the pixels 101.”, i.e. not driven).
In regards to claim 5, Hong discloses the panel driver is further configured to apply the preliminary data voltages to third sub-pixels that are arranged on the same row as the first sub-pixels and the second sub-pixels and emit light of a third color before the sensing operation in the blank period (Fig. 6, sensing mode with Tw data writing period and application of Vsdata; Par. 0100 “the sensing data voltage Vsdata may be set to a full white voltage (e.g., white image data) or a full gray voltage of pure colors (R, G, and B) in order to increase the gate-source voltage Vgs of the driving element DT. The full white voltage is a maximum voltage of R, G, and B data applied to the R, G, and B sub-pixels. The full gray voltage of the pure colors is a maximum voltage applied to a sub-pixel having any one of R, G, and B colors.”; a red green and blue subpixel are driven to create a white image data; Par. 0067 “The sensing mode may be activated in at least one of a power on sequence in which the display device is powered on and the display panel driver starts driving, a vertical blank VB between frame periods”).
In regards to claim 12, Hong discloses driving third sub-pixels that are arranged on the same row as the first sub-pixels and the second sub-pixels and emit light of a third color in the preliminary emission period, before the sensing of the first sub-pixels (Fig. 6, sensing mode with Tw data writing period and application of Vsdata; Par. 0100 “the sensing data voltage Vsdata may be set to a full white voltage (e.g., white image data) or a full gray voltage of pure colors (R, G, and B) in order to increase the gate-source voltage Vgs of the driving element DT. The full white voltage is a maximum voltage of R, G, and B data applied to the R, G, and B sub-pixels. The full gray voltage of the pure colors is a maximum voltage applied to a sub-pixel having any one of R, G, and B colors.”; a red green and blue subpixel are driven to create a white image data; Par. 0067 “The sensing mode may be activated in at least one of a power on sequence in which the display device is powered on and the display panel driver starts driving, a vertical blank VB between frame periods”).
In regards to claim 19, Hong discloses the panel driver is further configured to drive third sub-pixels that are arranged on the same row as the first sub-pixels and the second sub-pixels and emit light of a third color in the preliminary emission period (Fig. 6, sensing mode with Tw data writing period and application of Vsdata; Par. 0100 “the sensing data voltage Vsdata may be set to a full white voltage (e.g., white image data) or a full gray voltage of pure colors (R, G, and B) in order to increase the gate-source voltage Vgs of the driving element DT. The full white voltage is a maximum voltage of R, G, and B data applied to the R, G, and B sub-pixels. The full gray voltage of the pure colors is a maximum voltage applied to a sub-pixel having any one of R, G, and B colors.”; a red green and blue subpixel are driven to create a white image data; Par. 0067 “The sensing mode may be activated in at least one of a power on sequence in which the display device is powered on and the display panel driver starts driving, a vertical blank VB between frame periods”).
In regards to claim 8, Hong discloses a blank period of the one frame comprises the preliminary emission period and the sensing period (Fig. 6, sensing mode with Tw data writing period and Tvsc non-light emission sensing period; Par. 0067 “The sensing mode may be activated in at least one of a power on sequence in which the display device is powered on and the display panel driver starts driving, a vertical blank VB between frame periods”).
In regards to claim 15, Hong discloses a blank period of the one frame comprises the preliminary emission period and the sensing period (Fig. 6, sensing mode with Tw data writing period and Tvsc non-light emission sensing period; Par. 0067 “The sensing mode may be activated in at least one of a power on sequence in which the display device is powered on and the display panel driver starts driving, a vertical blank VB between frame periods”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6, 13, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong, US-20230137365, in view of Lee, US-20200388230.
In regards to claim 6, Hong does not disclose expressly the sub-pixels have a two-or-more-stack tandem structure.
Lee discloses sub-pixels have a two-or-more-stack tandem structure (Par. 0146 “the emission layer may have a multilayer structure in which a red emission layer, a green, emission layer, and a blue emission layer are stacked to emit white light”, wherein the emission layer is of a sub-pixel).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art that the sub-pixels of Hong could be stacked multilayer subpixels in the manner of Lee. The motivation for doing so would have been for saving space and each sub-pixel can emit red, green, and blue light in any mixture as needed.
In regards to claim 13, Hong does not disclose expressly the sub-pixels have a two-or-more-stack tandem structure.
Lee discloses sub-pixels have a two-or-more-stack tandem structure (Par. 0146 “the emission layer may have a multilayer structure in which a red emission layer, a green, emission layer, and a blue emission layer are stacked to emit white light”, wherein the emission layer is of a sub-pixel).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art that the sub-pixels of Hong could be stacked multilayer subpixels in the manner of Lee. The motivation for doing so would have been for saving space and each sub-pixel can emit red, green, and blue light in any mixture as needed.
In regards to claim 20, Hong does not disclose expressly the sub-pixels have a two-or-more-stack tandem structure.
Lee discloses sub-pixels have a two-or-more-stack tandem structure (Par. 0146 “the emission layer may have a multilayer structure in which a red emission layer, a green, emission layer, and a blue emission layer are stacked to emit white light”, wherein the emission layer is of a sub-pixel).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art that the sub-pixels of Hong could be stacked multilayer subpixels in the manner of Lee. The motivation for doing so would have been for saving space and each sub-pixel can emit red, green, and blue light in any mixture as needed.
Conclusion
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/CORY A ALMEIDA/Primary Examiner, Art Unit 2628 12/29/25