DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)(l) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claims 1, 7, 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tagawa et al., (US 2020/0382735 A1).
Regarding claim 1, Tagawa et al., disclose an image sensor comprising:
a pixel array (Fig. 6 shows the adjacent pixels 230, 240, 250, 260, or [0117], “In the pixel array unit 220, a plurality of basic units 225 is arranged, each containing 4 unit pixels 230, 240, 250, 260) including a plurality of unit pixel circuits (see Fig.6 , [0121], “In the basic unit 225, the pixel 230 includes a photodiode 231, a transfer transistor 232, a charge storage unit 233, reset transistors 234 and 235, an amplification transistor 236, and a selection transistor 237”, showing each pixel includes multiple pixel circuits);
a plurality of readout lines (vertical signal lines VSL2j−1, VRD2j−1, VPX2j−1, VSL2j, VPX2j, VRD2j, Fig. 6 and [0137]-[0139]) connected to the plurality of unit pixel circuits (see Fig.6, the vertical signal lines directly connect to the unit pixel circuits);
a plurality of bias circuits (310, Figs 3-4, and [0096], “The unit readout circuit 310 includes… current sources 341 to 344”);
a first path selection circuit (326/327, Fig.4) coupled between the plurality of readout lines (vertical signal lines VSL2j−1, VRD2j−1, VPX2j−1, VSL2j, VPX2j, VRD2j, see Figs.4 and 6) and the plurality of bias circuits (341, 343), and suitable for selectively connecting the plurality of readout lines (the vertical signal lines) to the plurality of bias circuits ( current sources 341, 343) on the basis of a plurality of first control signals (SW22, SW23)( [0167], “The unit readout circuit 310 connects the vertical signal lines VSL2j−1, VSL2j, and VRD2j”, and [0181], “the unit readout circuit 310 connects the vertical signal lines VSL2j−1, VRD2j−1, VSL2j, and VRD2j to the current sources 341, 343, 342, and 344, respectively”);
a plurality of readout circuits (270 includes the Vout1- Vout4, 273, 276-278, Fig. 7); and
a second path selection circuit (315/320, Fig.4) coupled between the plurality of readout lines (the vertical signal lines VSL2j−1, VSL2j, VRD2j−1, and VRD2j ) and the plurality of readout circuits (270), and suitable for selectively connecting the plurality of readout lines ( the vertical signal lines) to the plurality of readout circuits (270) on the basis of a plurality of second control signals (SW1/SW2) (see Fig.4, the switches 315 or 320 selectively route lines, the vertical signal lines VSL2j−1, VSL2j VRD2j−1, and VRD2j to the processing unit 270 under control signals SW1/SW2).
Regarding claim 7, Tagawa et al., as discussed in claim 1, disclose the second path selection circuit (315/320, Fig. 4) connecting at least two readout lines of the plurality of readout lines (VSL2j−1, VSL2j, or VRD2j and VSL2J, Fig. 4 and [0097]) to one readout circuit (273) of the plurality of readout circuits (270) (the processing unit 270 includes the ADC 273 via output node Vout1, see Figs. 4 and 7).
Regarding claim 8, Tagawa et al., as discussed in claim 7, disclose the at least two readout lines (VSL2j−1, VSL2j, or VRD2j and VSL2J, see Fig. 16 and [0181]) are connected to an input terminal of the one readout circuit ([0144], “an analog signal of the voltage Vout1 from the column readout circuit is input to the ADC 273”, Figs 4 -7 show the terminal/line connecting the unit readout having at least two readout lines to the processing unit 270 including the ADC 273).
4. Claims 1, 4-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bock (US 2006/0243890 A1).
Regarding claim 1, Bock discloses an image sensor comprising:
a pixel array (200, Fig.2) including a plurality of unit pixel circuits (pixels 201, see Fig.2); a plurality of readout lines connected to the plurality of unit pixel circuits ([0025], “FIG. 3, each pixel 201 is connected to a column line 301 a, 301 b” and [0032], “lines 701 a, 701 b’, Fig. 7); a plurality of bias circuits (Figs 3, 7 and [0028], “the loads on the column lines 301 a, 301 b” a PMOS load transistor 765, and/or Vdd/ground);
a first path selection circuit (761, 762 or 763, Fig. 7, [0032], switches 761, 762, 763”) coupled between the plurality of readout lines (301 a, 301 b, 701 a, 701 b) and the plurality of bias circuits (765 and Vdd), and suitable for selectively connecting the plurality of readout lines (301 a, 301 b, 701 a, 701 b) to the plurality of bias circuits (765 and Vdd ) on the basis of a plurality of first control signals (NBin, Bin, see Figs. 7-8);
a plurality of readout circuits (116 includes column circuit 111, output lines 777, 778, and/or converter (ADC) 118, see Figs. 1, 7, and 8); and
a second path selection circuit ( switches 768, 769 and 115, Figs.1, 4, and [0022], “The pixels of the columns can be read out in a specified order using a horizontal addressing circuit 115”) coupled between the plurality of readout lines (701 a, 701 b) and the plurality of readout circuits (777, 778), and suitable for selectively connecting the plurality of readout lines (701 a, 701 b) to the plurality of readout circuits (777, 778) on the basis of a plurality of second control signals (NBin, Bin, Figs. 7-8).
Regarding claim 4, Bock, as discussed in claim 1, disclose the first path selection circuit (switches 761, 762, 763, Fig. 7) selectively connecting two or more readout lines (701a, 701b) to one of the bias circuits during a single row time in a binning mode (Fig. 7, [0032], “ For the binning mode, switches 761, 762 which receive a Bin signal, are conductive, connecting lines 701a, 701b to the load transistor 765”), and selectively connects one readout line (301a/301b) to one bias circuit (the individual column load) during the single row time in a normal mode (non-binning mode or NBin, [0028], and [0033], “In the non-binning mode, the Bin signal remains low … the loads on the column lines 301 a, 301 b are not connected to each other”).
Regarding claim 5, Bock as discussed in claim 1, disclose the first path selection circuit (switches 761, 762, 763, Fig.7) selectively connects one readout line to one bias circuit during a single row time in a binning mode (Fig.7 and [0032], binned signals route to the transistor 765), and selectively connects some of the plurality of bias circuits to some of the plurality of readout lines during the single row time in a normal mode ([0022], “selects a particular row or rows of pixels in the array 200 by controlling the operation of vertical addressing circuit 114 “, then [0028], “Referring to FIG. 4, a row 1 select (ROW 1) signal is pulsed high…connect pixels of row 1 to column lines 301 a, 301 b for readout”, showing the in the normal mode, during a single row readout pulse such as the ROW1 high, the column path selection circuit connects active column readout line across the array or subset/some of all readout lines to the corresponding column loads (subset/some of all bias circuits)).
Regarding claim 6, Bock as discussed in claim 1, disclose the second path selection circuit (switches 768, 769 and 115, Figs.1, 4, 7) selectively connects two or more readout lines ( 701a, 701b) to one of the readout circuits (ADC118) during a single row time in a binning mode ([0032], “For the binning mode, switches 761, 762, and 768, which receive a Bin signal, are conductive” and [0034], “when Bin goes high, switch 768 is closed to permit the output of binned pixel signals through binning output line 778” to the ADC 118), and selectively connects one readout line (701a) to one readout circuit (ADC 118) during the single row time in a normal mode (Figs. 1, 7, 8, [0022], and [0033], “When NBin is high, switch 769 is also conductive to permit output of individual pixel signals such as routing one readout line 701a/701b to the non-binning output line 777, leading to downstream readout circuit ADC 118).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Tagawa et al., in view of Yoo (US 2012/0006972 A1).
Regarding claim 9, Tagawa et al., as discussed in claim 1, do not disclose the second path selection circuit performing an analog binning operation on a plurality of unit pixel signals generated from the plurality of unit pixel circuits to output a plurality of selection pixel signals to the plurality of readout circuits as claimed. Yoo discloses the second path selection circuit (SSW0/ SSW1, Fig.3 and [0029]) performing an analog binning operation on a plurality ([0041]-[0043], switch AV0 is closed (e.g., turned on), “charges are shared between the first capacitor C1 and the second capacitor C2. Therefore, binning data obtained into a digital value through an analog-to-digital conversion by the ADC 140”)of unit pixel signals generated from the plurality of unit pixel circuits ([0024], “(i, j) pixel 210, an (i+2, j) pixel 220, an (i, j+2) pixel 230, and an (i+2, j+2) pixel 240”) to output a plurality of selection pixel signals to the plurality of readout circuits ([0043], “The binning data stored in the first capacitor C1 and the second capacitor C2 is converted into a digital value through an analog-to-digital conversion by the ADC 140”, showing the selected binned inputs to the ADC 140). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tagawa et al., by utilizing the teaching of Yoo, to improve low light SNR by combining pixel signal in the analog binning operation.
Allowable Subject Matter
7. Claims 2-3 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, the prior art fails to disclose a number of the plurality of readout circuits being less than a number of the plurality of readout lines, and a number of the plurality of bias circuits is equal to the number of the plurality of readout circuits.
Regarding claim 3, the prior art fails to disclose a number of the plurality of readout circuits being less than a number of the plurality of readout lines, and a number of the plurality of bias circuits is equal to the number of the plurality of readout lines.
Conclusion
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/M.T.T./Examiner, Art Unit 2878
/GEORGIA Y EPPS/Supervisory Patent Examiner, Art Unit 2878
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