DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 12293052. Although the claims at issue are not identical, they are not patentably distinct from each other because the systems of this application contains similar structures adequate to perform the functions recited in the patent application. The claims are as follows with the differences highlighted:
19170153
12293052
With reference to claim 1: An electronic device comprising: an input sensing part on an active area of a display panel, wherein the input sensing part includes a first area, a second area around the first area, and a third area surrounding the first area and the second area, wherein the input sensing part comprises first to third nodes disposed on the first to third areas, respectively; wherein each of the first to third nodes comprises: a first connection pattern; a first sensing pattern comprising a first pattern and a second pattern spaced apart from each other in a first direction with the first connection pattern therebetween; a second connection pattern; and a second sensing pattern comprising a third pattern and a fourth pattern spaced apart from each other in a second direction crossing the first direction with the second connection pattern therebetween, wherein an outer line of the third area is defined by a first closed line, an outer line of the first area is defined by a second closed line, the second area and the third area are divided by a third closed line, wherein the third closed line comprises at least a portion not parallel to a side of the second closed line, and wherein at least a projection of the portion of the third closed line overlaps a corresponding side of the second closed line in the first direction,
in a plan view.
With reference to claim 1: An electronic device comprising: an input sensing part on an active area of a display panel, wherein the input sensing part includes a first area, a second area around the first area, and a third area surrounding the first area and the second area, wherein the input sensing part comprises first to third nodes disposed on the first to third areas, respectively; wherein each of the first to third nodes comprises: a first connection pattern; a first sensing pattern comprising a first pattern and a second pattern spaced apart from each other in a first direction with the first connection pattern therebetween; a second connection pattern; and a second sensing pattern comprising a third pattern and a fourth pattern spaced apart from each other in a second direction crossing the first direction with the second connection pattern therebetween, wherein at least a portion of the second nodes has a shape different from that of each of the first nodes, and at least a portion of the third nodes have a shape different from that of each of the first nodes, wherein an outer line of the first area is defined by a second closed line, the second area and the third area are divided by a third closed line, wherein the third closed line comprises: first division lines facing sides of the second closed line, respectively; and second division lines configured to connect the first division lines to each other, wherein at least a portion of the first division lines comprises a portion extending in a direction different from an extending direction of a facing side of the sides of the second closed line, wherein a projection of the portion of the at least a portion of the first division lines overlaps the facing side of the sides of the second closed line in the first direction, in a plan view, and wherein the portion of the at least a of the first division lines is an upper boundary of a second node of the second nodes, in a plan view.
Claim 1 of this application is being anticipated by claim 1 of patent 12293052 with similar variation in the non-highlighted limitation above.
19170153
12293052
With reference to claim 11: An electronic device comprising: a display panel comprising an active area and a peripheral area adjacent to the active area; and an input sensing part on the display panel and comprising a first area, a second area configured to surround the first area, and a third area configured to surround the second area, wherein the first area, the second area, and the third area overlap the active area, wherein the input sensing part comprises first to third nodes, which are disposed on the first to third areas, respectively; wherein each of the first to third nodes comprises: a first connection pattern; a first sensing pattern comprising a first pattern and a second pattern spaced apart from each other in a first direction with the first connection pattern therebetween; a second connection pattern; and a second sensing pattern comprising a third pattern and a fourth pattern spaced apart from each other in a second direction crossing the first direction with the second connection pattern therebetween, wherein the second nodes comprise a first sub-node and a second sub-node, which have areas different from each other, each of the first and second sub-nodes comprises two sides extending in direction different from each other, wherein an outer line of the third area is defined by a first closed line, an outer line of the first area is defined by a second closed line, the second area and the third area are divided by a third closed line, wherein the third closed line comprises at least a portion not parallel to a side of the second closed line, and wherein at least a projection of the portion of the third closed line overlaps a corresponding side of the second closed line in the first direction, in a plan view.
With reference to claim 10: An electronic device comprising: a display panel comprising an active area and a peripheral area adjacent to the active area; and an input sensing part on the display panel and comprising a first area, a second area configured to surround the first area, and a third area configured to surround the second area, wherein the first area, the second area, and the third area overlap the active area, wherein the input sensing part comprises first to third nodes, which are disposed on the first to third areas, respectively; wherein each of the first to third nodes comprises: a first connection pattern; a first sensing pattern comprising a first pattern and a second pattern spaced apart from each other in a first direction with the first connection pattern therebetween; a second connection pattern; and a second sensing pattern comprising a third pattern and a fourth pattern spaced apart from each other in a second direction crossing the first direction with the second connection pattern therebetween, wherein the second nodes comprise a first sub-node and a second sub-node, which have areas different from each other, each of the first and second sub-nodes comprises two sides extending in direction different from each other, wherein at least a portion of the second nodes has a shape different from that of each of the first nodes, and at least a portion of the third nodes have a shape different from that of each of the first nodes, wherein an outer line of the first area is defined by a second closed line, the second area and the third area are divided by a third closed line, wherein the third closed line comprises: first division lines facing sides of the second closed line, respectively; and second division lines configured to connect the first division lines to each other, wherein at least a portion of the first division lines comprises a portion extending in a direction different from an extending direction of a facing side of the sides of the second closed line, wherein a projection of the portion of the at least a portion of the first division lines overlaps the facing side of the sides of the second closed line in the first direction, in a plan view, and wherein the portion of the at least a portion of the first division lines is an upper boundary of the second sub-node, in a plan view.
Claim 11 of this application is being anticipated by claim 10 of patent 12293052 with similar variation in the non-highlighted limitation above.
19170153
12293052
With reference to claim 20: An electronic device comprising: a display panel comprising an active area and a peripheral area adjacent to the active area; and an input sensing part disposed on the display panel and comprising a first area, a second area configured to surround the first area, and a third area configured to surround the second area, wherein each of the first area, the second area, and the third area overlaps the active area, wherein the first area is divided into a plurality of first nodes, the second area is divided into a plurality of second nodes, and the third area is divided into a plurality of third nodes, wherein the second nodes comprise a first sub-node and a second sub-node, which have areas different from each other, and the third nodes comprise a third sub-node and a fourth sub-node, which have areas different from each other, wherein an outer line of the third area is defined by a first closed line, an outer line of the first area is defined by a second closed line, the second area and the third area are divided by a third closed line, wherein the third closed line comprises at least a portion not parallel to a side of the second closed line, and wherein at least a projection of the portion of the third closed line overlaps a corresponding side of the second closed line in the first direction, in a plan view.
With reference to claim 19: An electronic device comprising: a display panel comprising an active area and a peripheral area adjacent to the active area; and an input sensing part disposed on the display panel and comprising a first area, a second area configured to surround the first area, and a third area configured to surround the second area, wherein each of the first area, the second area, and the third area overlaps the active area, wherein the first area is divided into a plurality of first nodes, the second area is divided into a plurality of second nodes, and the third area is divided into a plurality of third nodes, wherein the second nodes comprise a first sub-node and a second sub-node, which have areas different from each other, and the third nodes comprise a third sub-node and a fourth sub-node, which have areas different from each other, wherein an outer line of the first area is defined by a second closed line, the second area and the third area are divided by a third closed line, wherein the third closed line comprises: first division lines facing sides of the second closed line, respectively; and second division lines configured to connect the first division lines to each other, wherein at least a portion of the first division lines comprises a portion extending in a direction different from an extending direction of a facing side of the sides of the second closed line, wherein a projection of the portion of the at least a portion of the first division lines overlaps the facing side of the sides of the second closed line in the first direction, in a plan view, and wherein the portion of the at least a portion of the first division lines is an upper boundary of the second sub-node, in a plan view.
Claim 20 of this application is being anticipated by claim 19 of patent 12293052 with similar variation in the non-highlighted limitation above.
19170153
12293052
With reference to claim 2:
With reference to claim 1:
With reference to claim 3:
With reference to claim 2:
With reference to claim 4:
With reference to claim 3:
With reference to claim 5:
With reference to claim 4:
With reference to claim 6:
With reference to claim 5:
With reference to claim 7:
With reference to claim 6:
With reference to claim 8:
With reference to claim 7:
With reference to claim 9:
With reference to claim 8:
With reference to claim 10:
With reference to claim 9:
With reference to claim 12:
With reference to claim 10:
With reference to claim 13:
With reference to claim 11:
With reference to claim 14:
With reference to claim 12:
With reference to claim 15:
With reference to claim 13:
With reference to claim 16:
With reference to claim 14:
With reference to claim 17:
With reference to claim 15:
With reference to claim 18:
With reference to claim 16:
With reference to claim 19:
With reference to claim 17:
Claims 2-10 and 12-19 of this application is being anticipated by claims 1-17 of patent 12293052 with similar variation in the non-highlighted limitation above.
Conclusion
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/IFEDAYO B ILUYOMADE/Primary Examiner, Art Unit 2624 01/20/2026