DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because Figs 6 and 7 do not show “a first capacitor including a first electrode which receives the high gate voltage and a second electrode connected to the inverted control node” claimed in claim 8. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 18 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 18 recites “a fourth transistor including a gate electrode connected to the control node, a first electrode which receives the (M-1)-th clock signal, and a second electrode connected to the inverted control node.” Figs 6-7 of the specification disclose the fourth transistor, however, nowhere is it disclosed a first electrode of the fourth transistor receives the (M-1)-th clock signal as claimed. While the Summary section generally mentioned language as claimed, the Detailed Description section and the Drawings do not provide any specific implementation or detailed description of the claimed 18 invention. The closest related disclosure is in [0096] and Fig. 6 which disclose that the first electrode of the fourth transistor receiving Mth (4th) clock signal, not (M-1)th clock signal as claimed, while Fig. 7 and [00119] disclose a different embodiment in which the gate electrode of the fourth transistor is connected to a different signal (input signal IN[N]).
Allowable Subject Matter
Claims 1-17 and 19-21 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for indicating allowable subject matter in claims 1 and 15 is that the claims recite “wherein each of the stages receives first to M-th clock signals, respectively, wherein M is a positive integer greater than or equal to 3, wherein the control circuit receives an input signal in response to one of the first to M-th clock signals, and controls a voltage of a control node and a voltage of an inverted control node based on the input signal, and the first to (M- 1)-th gate output circuits sequentially outputs clock signals different from the one of the first to M-th clock signals received by the control circuit among the first to M-th clock signals as first to (M- 1)-th gate signals in response to the voltage of the control node and the voltage of the inverted control node” which, in combination with the other recited features, is not taught and/or suggested either singularly or I combination within the prior art.
In the closest prior art:
Feng et al. (US 2021/0201753) discloses a gate driver (Fig. 5; e.g., driver 20) including a plurality of stages (e.g., stages A1-A3), wherein each of the stages comprises a control circuit (Fig. 1A; e.g., control circuit 100 and 300) and first to (M- 1)-th gate output circuits (Fig. 2; e.g., a first output sub-circuit 211, a second output sub-circuit 212, and a third output sub-circuit 213), wherein each of the stages receives first to (M-1)-th clock signals (Fig. 5; e.g., CLKA-CLKC), respectively, wherein M is a positive integer greater than or equal to 3, wherein the control circuit receives an input signal (Fig. 3B), and controls a voltage of a control node and a voltage of an inverted control node based on the input signal (e.g., when the input signal is at the high level, the first node Q is at the high level and the potential of the second node QB is at the low level), and the first to (M- 1)-th gate output circuits outputs clock signals received by the control circuit as first to (M- 1)-th gate signals in response to the voltage of the control node and the voltage of the inverted control node.
WU et al. (US 2023/0059832) discloses a gate driver (Figs 8-10) including a plurality of stages, wherein each of the stages comprises a control circuit and first to (M−1)-th gate output circuits, wherein each of the stages receives first to M-th clock signals, respectively (e.g., clock signals CKV11, CKV12 and CKV2), wherein M is a positive integer greater than or equal to 3, wherein the control circuit receives an input signal in response to one of the first to M-th clock signals (e.g., receives an input signal VGL in response to the clock signal CK2), and controls a voltage of a control node and a voltage of an inverted control node based on the input signal (e.g., a control node N1and an inverted control node N2), and the first to (M−1)-th gate output circuits sequentially outputs first to (M−1)-th gate signals in response to the voltage of the control node and the voltage of the inverted control node.
However, the closest prior art fails to teach and/or suggest, either singularly or in combination, the specifically claimed features as highlighted above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Seo et al. (US 2023/0186825); DU (US 2017/0256223) and Bai et al. (US 2015/0170592) are cited to disclose a gate driver including a plurality of stages, wherein each of the stages comprises a control circuit and first to M gate output circuits, wherein each of the stage receives a plurality of clock signals, respectively, wherein the control circuit receives an input signal and controls a voltage of a control node based on the input signal, and the first to M gate output circuits sequentially outputs the plurality of clock signals as first to M-th gate signals in response to the voltage of the control node.
Park (US 2019/0287458) discloses a gate driver including a plurality of stages, wherein each of the stages comprises a control circuit and an output circuit, wherein the control circuit receives an input signal receives an input signal in response toa clock signal, and controls a voltage of a control node and a voltage of an inverted control node based on the input signal.
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/HONG ZHOU/Primary Examiner, Art Unit 2629