DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including Microsoft Team Meeting, are encouraged to fill out the online Automated Interview Request (AIR) form
(https://www.uspto.gov/sites/default/files/documents/PTOL413A.pdf). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1, 10 and 17.
b. Pending: 1-20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4 are rejected under 35 U.S.C. 103 as being unpatentable over Hu PG PUB 20180374551 (hereinafter Hu), in view of Goda PG PUB 20240347126 (hereinafter Goda126).
Regarding independent claim 1, Hu teaches a storage controller comprising:
a host interface configured to receive a read request or a program request from a host device (220 in figure 2 of Hu, [0047], “…a host interface 220 …host interface 220 typically facilitates transfer for data, control signals, and timing signals…”);
a flash conversion layer (238 in figure 2 of Hu) configured to collect deterioration information on a non-volatile memory device and log the deterioration information in a unit of a sub-block (Hu, figure 2 and 11, [0117]-[0118] of Hu, Hu teaches maintains individual sub-block erase-disturb counts in metadata, with records maintained in the FTL layer, [0118] of Hu, “…data structure for the erase disturb counts for the sub-blocks can be maintained in block metadata… For two sub-blocks per full physical block, this would 2 bytes per physical block and can be kept as part of the Flash Translation Layer (FTL) or Media Management Layer (MML 238, FIG. 2))…”); and a flash interface configured to transfer the command to the non-volatile memory device (Hu teaches in figure 2 and [0048] command sequencer 226 generates memory-command sequences, and memory interface 230 transmits those sequences to non-volatile memory die 108).
But Hu does not teach that its FTL selects the read/program target and adjacent sub-block and generate a command adjusting the adjacent sub-block’s core based on deterioration information.
Goda126 supplies the neighboring-sub-block voltage-adjustment teaching:
select a first sub-block and a second sub-block adjacent to the first sub- block based on the read request or the program request (Goda126 teaches in figure 3A and [0036]-[0039] upper and lower decks 305-1/305-2, each comprising a separate group of word lines and independently programmable and erasable. Figure 6 step 661 and [0059] teaches an aggressor deck for a read operation and its corresponding victim deck. Map aggressor 305-1 to the first subblock and adjacent 305-2 to the second).
generate a command that adjusts a core of the second sub-block based on the deterioration information (Goda126 teaches in figure e8 and [0067] controller 891, through adjustment component 897, determines victim pass voltage based on elapsed time, victim P/E cycling, temperature or threshold-voltage characteristics. Figure 6 step 662-664 and [0059]-[0060] teaches determines victim elapsed time and selects its pass voltage. Figure 3B and 5B, [0049], [0057] apply the adjusted pass voltage to the victim’s word line. [0068] teaches supplies controller conversion of host operations into memory commands).
It would have been obvious to incorporate Goda126’s victim-deck deterioration tracking and pass-voltage-selection functions into Hu’s FTL 238, maintaining the victim’s elapsed-time or P/E information alongside Hu’s existing sub-block deterioration metadata. Upon a host read request the modified FTL would identify the target sub-block and its adjacent victim, determine the victim pass-voltage setting from that victim’s deterioration information, and generate the corresponding adjustment command for transmission through Hu’s memory interface 230.
Both references manage deterioration in separately erasable portions of NAND memory. Hu places sub-block deterioration records within its flash-management layer; Goda126 uses victim-specific deterioration information to control neighboring-deck voltage. Implementing the decision in that layer would allow the firmware managing the sub-block records and host accesses to coordinate the voltage setting, reducing further victim disturb while maintaining string conduction.
Regarding claim 4, the combination of Hu and Goda126 teaches the storage controller of claim 1, wherein the flash conversion layer comprises a sub-block program/erase cycle checking circuit configured to generate a second command that adjusts a pass voltage applied to the second sub-block based on a program/erase cycle count, the second command included in the command, and the program/erase cycle count included in the deterioration information (Goda126 teaches in [0057] monitoring the victim deck’s P/E cycle count and using that count to determine its adjusted read-pass voltage. [0060] of Goda126 further teaches voltage selection using P/E range, [0067]/figure 8 places adjustment functionality in controller component 897. These teachings supply checking the second sub-block P/E count and selecting its pass voltage accordingly. It would have been obvious to incorporate this P/E based adjustment into Hu’s FTL sub-block management and generate a corresponding flash command, so that the controller selects the victim voltage using its recorded wear information before accessing the neighboring aggressor sub-block).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Hu PG PUB 20180374551 (hereinafter Hu), in view of Goda PG PUB 20240347126 (hereinafter Goda126), further in view of Goda PG PUB 20240168880 (hereinafter Goda880).
Regarding claim 2, the combination of Hu and Goda126 teaches the storage controller of claim 1, wherein the flash conversion layer comprises a sub-block read disturb checking circuit (Hu FTL 238 maintains sub-block deterioration records in figure 2/[0118], Goda880 teaches in [0046]-[0047]/[0060]-[0064] victim-deck read disturb counting and threshold checking, see figure 6 and 9. Incorporating this checking functionality into Hu’s FTL us the proposed modification) configured to generate a first command that adjusts a pass voltage applied to the second sub-block based on a read disturb count (Goda880 teaches in [0076]/figure 9 to trigger a corrective action, including scanning, when the victim count reaches a threshold. Goda16 teaches in [0050]/figure 3B and 5A-5B to use a victim scan to determine a reduced victim pass voltage. Goda126 teaches in [0067]-[0068]/figure 8 supplies controller adjustment and command adjustment functionality. Generating the voltage-adjustment command from the threshold triggered scan is the proposed combination), the first command included in the command, and the read disturb count included in the deterioration information.
Regarding claim 3, the combination of Hu, Goda126 and Goda880 teaches the storage controller of claim 2, wherein the first command is configured to lower the pass voltage applied to the second sub-block based on a number of read disturbs generated in the second sub-block being greater than or equal to a first reference value, and the number of read disturbs generated in the second sub-block is determined based on the read disturb count (Goda880 teaches in [0076] and figure 9 to initiating corrective action when the victim-deck read disturb count is “greater than or equal to the read disturb count threshold”. Goda126 in [0050] teaches reducing the victim’s pass voltage based on the scanned threshold voltage characteristics. Thus the proposed combined controller would initiate the scan at the claimed count threshold and issue the command lowering the second sub-block’s pass voltage using the scan result. It would have been obvious to combine these teachings because both Goda references address aggressor-induced stress in independently erasable decks sharing NAND strings. Using Goda880’s accumulated victim count to initiate Goda126’s scan and voltage adjustment would provide a stress-based trigger for reducing subsequent victim disturbance. Implementing that decision within HU’s FTL would coordinate the adjustment with its existing sub-block metadata management).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Hu PG PUB 20180374551 (hereinafter Hu), in view of Goda PG PUB 20240347126 (hereinafter Goda126), further in view of Yuan PG PUB 20120314499 (hereinafter Yuan).
Regarding claim 5, the combination of Hu and Goda126 teaches the storage controller of claim 4, Goda126 further teaches adjustment based on P/E count. However, the combination does not teach wherein the second command is configured to increase the pass voltage applied to the second sub-block based on a number of program/erase cycles occurring in the second sub-block being greater than or equal to a first reference value, and the number of program/erase cycles occurring in the second sub-block is determined based on the program/erase cycle count.
Yuan teaches in [0100] and figure 13 the additional direction and threshold behavior: its read-pass voltage increases in steps at successive P/E cycle boundaries, including every 20 cycles. Applying that step function to Goda126 victim deck P/E count would increase its pass voltage when the count reaches a selected reference value.
It would have been obvious to apply Yuan’s wear dependent increase to the victim-deck voltage selection, using Ph’s logic and generator to implement the increased setting when the victim P/E count exceed a selected boundary.
Claims 10, 17, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Goda PG PUB 20240347126 (hereinafter Goda126), in view of Goda PG PUB 20240168880 (hereinafter Goda880).
Regarding independent claim 10, Goda126 teaches a storage device (figure 8 of Goda126, [0065]-[0066]) comprising:
a storage controller (891 in figure 8 of Goda126) configured to select a first sub-block (305-1 in figures 3A-3B of Goda126, figure 3A-3B, [0036]/[0043]/[0059]/[0068], “…aggressor deck (e.g., 305-1)…”) and a second sub-block (305-2 in figures 3A-3B of Goda126, figure 3A-3B, [0036]/[0043]/[0059]/[0068], “…victim deck (e.g., 305-2)…”) adjacent to the first sub- block among a plurality of sub-blocks based on a read request or a program request from a host device, and generate a command that adjusts a core of the second sub-block based on a disturb generated in the second sub-block exceeding a first reference value (Goda880 teaches in figure 6/[0063]-[0064] that when victim disturb count “exceed a threshold count”, initiate corrective action, including scanning, Goda126 teaches in [0050] use a victim scan to select a reduced pass voltage. Command generation is the proposed implementation of that combined operation); and
a non-volatile memory device (800 in figure 8 of Goda126) that includes the plurality of sub-blocks, the non- volatile memory device configured to adjust a size of a pass voltage applied to a word line included in the second sub-block based on the command and an address of the second sub-block (Goda126 teaches in figures 1, 3B and 8/[0023]-[0025]/[0067]-[0068] command/address handling and victim-voltage adjustment provide the architecture for applying the selected voltage to the addressed victim deck).
Goda126 and Goda880 supply complimentary functions: Goda880supplies when to initiate corrective action, and Goda126 supplies scan-based voltage reduction. It would have been obvious to use Goda880 threshold-triggered victim scan to determine Goda126 reduced victim pass voltage, and communicate that setting through the existing command/address interface, to reduce subsequent aggressor-induced stress on the victim deck.
Regarding independent claim 17, the combination of Goda126 and Goda880 teaches a method of operating a storage device (figure 8 of Goda126, [0065]-[0066]), comprising: selecting a first sub-block (305-1 in figures 3A-3B of Goda126, figure 3A-3B, [0036]/[0043]/[0059]/[0068], “…aggressor deck (e.g., 305-1)…”) configured to be a target of a read operation or a program operation among a plurality of sub-blocks, the plurality of sub-blocks distinguished from each other through a plurality of word lines; determining whether deterioration information of a second sub-block (305-2 in figures 3A-3B of Goda126, figure 3A-3B, [0036]/[0043]/[0059]/[0068], “…victim deck (e.g., 305-2)…”) adjacent to the first sub-block is greater than or equal to a first reference value (Goda126 teaches in [0059]-[0060]/figure 6 victim-deck time after programming (TAP), voltage selection depends on the “TAP reaching respective threshold levels”); and
adjusting a core of the second sub-block based on the deterioration information of the second sub-block being greater than or equal to the first reference value (Goda126 teaches in [0060]/figures 3A-3B to select and apply the corresponding reduced victim pass voltage).
Regarding claim 18, the combination of Goda126 and Goda880 teaches the method of claim 17, wherein the first sub-block is configured to be the target of the read operation, determining whether the deterioration information of the second sub-block is greater than or equal to the first reference value comprises determining whether a read disturb occurring in the second sub-block is greater than or equal to the first reference value, and adjusting the core of the second sub-block based on the deterioration information of the second sub-block being greater than or equal to the first reference value comprises generating a first command that lowers a pass voltage applied to the second sub-block based on the read disturb occurring in the second sub- block being greater than or equal to the first reference value (Goda880 teaches in figure 9 and [0076] to compare the victim read-disturb count with a threshold and initiates corrective action when the count is greater than or equal to that threshold. The action can include a victim scan. Goda126 teaches in [0050] scan based selection of a reduced victim pass voltage, Goda126 and Goda880 supply complimentary functions: Goda880supplies when to initiate corrective action, and Goda126 supplies scan-based voltage reduction. It would have been obvious to use Goda880 threshold-triggered victim scan to determine Goda126 reduced victim pass voltage, and communicate that setting through the existing command/address interface, to reduce subsequent aggressor-induced stress on the victim deck).
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Goda PG PUB 20240347126 (hereinafter Goda126), in view of Goda PG PUB 20240168880 (hereinafter Goda880), further in view of Oh PG PUB 20140136765 (hereinafter Oh).
Regarding claim 11, the combination of Goda126 and Goda880 teaches the storage device of claim 10, wherein the non-volatile memory device comprises a voltage generator (circuit responsible for generating Vpass in [0050] of Goda880) configured to generate the pass voltage (Alternatively, Oh teaches figure 17 and [0158]-[0161] nonvolatile memory 400 containing voltage generator 460, which generates adjusted word-line voltage, including pass voltage).
Regarding claim 12, the combination of Goda126, Goda880 and Oh teaches the storage device of claim 11, wherein the non-volatile memory device includes a control logic configured to provide the voltage generator with a voltage control signal, the voltage control signal changing the pass voltage applied to the word line included in the second sub-block based on the command and the address of the second sub-block (Oh teaches in figure 17 and [0159]-[0161] command/address input through buffer 440, control logic 450, read-voltage adjuster 455, and generator 460. [0160] of Oh teaches the generator is configured according to the adjusted read bias. The signal by which logic 450/adjuster 455 configures generator 460 is the proposed voltage control signal).
Regarding claim 13, the combination of Goda126, Goda880 and Oh teaches the storage device of claim 12, wherein the storage controller is configured to generate a first command that lower the pass voltage applied to the second sub-block based on a read disturb occurring in the second sub-block exceeding a first reference value, the control logic is configured to provide the voltage generator with the voltage control signal that lowers the pass voltage applied to the second sub-block based on the first command, and the voltage generator is configured to generate the pass voltage applied to the word line of each memory cell included in the second sub-block based on the voltage control signal (combination of Goda126/Goda880 teaches threshold-triggered victim pass voltage reduction. Oh teaches on-device logic/adjuster/generator implementation for producing and applying the rescued voltage. It would have been obvious to implement combined voltage setting operation using Oh’s on-device voltage generator and control circuitry, thereby generating the selected bias locally and applying it to the addressed word lines).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Goda PG PUB 20240347126 (hereinafter Goda126), in view of Goda PG PUB 20240168880 (hereinafter Goda880), further in view of Oh PG PUB 20140136765 (hereinafter Oh), further in view of Yuan PG PUB 20120314499 (hereinafter Yuan).
Regarding claim 14, the combination of Goda126, Goda880 and Oh teaches the storage device of claim 12, Goda126 further teaches adjustment based on P/E count. However, the combination does not teach wherein the storage controller is configured to generate a second command that increases the pass voltage applied to the second sub-block based on a number of program/erase cycles occurring in the second sub-block exceeding a first reference value, the control logic is configured to provide the voltage generator with the voltage control signal that increases the pass voltage applied to the second sub-block based on the second command, and the voltage generator is configured to generate the pass voltage applied to the word line of each memory cell included in the second sub-block based on the voltage control signal.
Yuan teaches in [0100] and figure 13 the additional direction and threshold behavior: its read-pass voltage increases in steps at successive P/E cycle boundaries, including every 20 cycles. Applying that step function to Goda126 victim deck P/E count would increase its pass voltage when the count reaches a selected reference value.
It would have been obvious to apply Yuan’s wear dependent increase to the victim-deck voltage selection, using Oh’s logic and generator to implement the increased setting when the victim P/E count exceeds a selected boundary.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Goda PG PUB 20240347126 (hereinafter Goda126), in view of Goda PG PUB 20240168880 (hereinafter Goda880), further in view of Yuan PG PUB 20120314499 (hereinafter Yuan).
Regarding claim 19, the combination of Goda126 and Goda880 teaches the method of claim 17, wherein the first sub-block is configured to be the target of the read operation, determining whether the deterioration information of the second sub-block is greater than or equal to the first reference value comprises determining whether a number of program/erase cycles occurring in the second sub-block is greater than or equal to the first reference value, and adjusting the core of the second sub-block based on the deterioration information of the second sub-block being greater than or equal to the first reference value comprises generating a second command that increases a pass voltage applied to the second sub-block based on the number of program/erase cycles occurring in the second sub-block being greater than or equal to the first reference value (Goda126 teaches aggressor-read/victim-deck arrangement and victim P/E based voltage selection. Yuan teaches in [0100] and figure 13 the additional direction and threshold behavior: its read-pass voltage increases in steps at successive P/E cycle boundaries, including every 20 cycles. Applying that step function to Goda126 victim deck P/E count would increase its pass voltage when the count reaches a selected reference value).
Allowable Subject Matter
Claims 6-9, 15-16, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The closest prior art to the present invention is Hu (US 20180374551 Al).
Hu discloses a non-volatile memory is configured to allow programming and erase at the sub-block level. In a sub-block erase, some of the memory cells can be selected for erase while others are not selected for erase, such as by leaving their word lines to float while applying the erase voltage to the well structure of the physical block to which the sub-blocks belong. Although a sub-block erase applies a lower electric field across the non-selected memory cells than the erase selected memory cells, it still places the non-selected memory cells under some degree of stress and can lead to erase disturb. To help manage this erase disturb, each sub-block has an associated erase disturb count, which is incremented when another sub-block of the same physical block is erased, but reset when the sub-block itself is erase. Once a count reaches a threshold value, the sub-block can be marked for remedial action, such as refresh or garbage collection.
Regarding claim 6 (and the respective dependent claims), the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: the flash conversion layer comprises a sub-block retry checking circuit configured to generate a third command that adjusts a pass voltage applied to the second sub-block based on a retry count, the third command included in the command, and the retry count included in the deterioration information.
Regarding claim 15 (and the respective dependent claims), the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: the storage controller is configured to generate a third command that changes a type of a memory cell included in the first sub-block based on a number of retries occurring in the second sub-block.
Regarding claim 20, the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: generating a third command that changes a type of a memory cell included in the first sub-block to a single level cell (SLC) type based on the number of retries occurring in the second sub-block being greater than or equal to the first reference value.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOCHUN L CHEN whose telephone number is (571)272-0941. The examiner can normally be reached on M-F: 9AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/XIAOCHUN L CHEN/Examiner, Art Unit 2824
Prosecution Insights